Digitally Controlled DC-DC Converters with Fast and Smooth Load Transient Response

by

Jing Wang

Supervisors: Wai Tung Ng and Aleksandar Prodi

A thesis submitted in conformity with the requirements for the degree of Doctor of Philosophy

Department of Electrical and Computer Engineering University of Toronto

Copyright by Jing Wang 2013

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Digitally Controlled DC-DC Converters with Fast and Smooth Load Transient Response

Jing Wang

Doctor of Philosophy

Department of Electrical and Computer Engineering University of Toronto

2013

Abstract

Modern switch-mode power supplies (SMPS) used for point-of-load (PoL) applications need to

meet increasingly stringent requirements on voltage regulation, while minimizing physical

volume and optimizing conversion efficiency. The focus of this thesis is the voltage regulation

capability of low-power PoL converters during load transients. The main objective is to

investigate converter topologies and control techniques that can achieve fast and smooth

transient performance without significant penalty in volume and efficiency. The digital control

method is used due to its ability to implement sophisticated control algorithms. The first part of

this thesis investigates a dual output stages converter, with a small auxiliary output stage

connected in parallel with the main output stage. While the main output stage is responsible for

steady-state operation and designed to achieve optimum efficiency, the auxiliary stage is

activated when a load transient occurs, to help suppress voltage deviation. Experimental results

on a 6 V-to-1 V, 3W buck converter shows 35% improvement in peak transient voltage deviation

while maintaining the same efficiency profile, compared to an equivalent buck converter. The

second part of this thesis introduces a flyback-transformer based buck (FTBB) converter. In this

topology, the conventional buck inductor is replaced with the primary winding of the flyback

transformer, an extra switch, and a set of small auxiliary switches on the secondary side. During

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heavy-to-light load transients the inductor current is steered away from the output capacitor to

the input port, achieving both energy recycling and savings due to reduced voltage overshoots.

The light-to-heavy transient response is improved by reducing the equivalent inductance of the

primary transformer winding to its leakage value. Compared to an equivalent buck converter,

experiment results on a 6 V-to-1 V, 3 W prototype show three times smaller maximum output

voltage deviation during load transients and, for frequently changing loads, about 7% decrease in

power losses.

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AcknowledgmentsAcknowledgmentsAcknowledgmentsAcknowledgments

First and foremost, I would like to express my sincere gratitude to my co-supervisors, Professor Wai Tung Ng and Professor Aleksandar Prodi. It is my greatest honor to work with

them. And I cannot imagine a better combination of supervisors.

Professor Ng has been an excellent advisor in academia and a great mentor in life. I really enjoy working in the Smart Power Integration and Semiconductor Devices research group under his leadership. And our talks and conference trips together will never be forgotten. From

him there is a lot for me to learn. I always admire him being very successful in career while having a loving family life. I always try to learn from his logical thinking and problem solving

skills. And I am thankful of him being cool under all circumstances, even when I burnt my test chips.

I started working with Professor Prodi in my second year of study but I got to know him since my first power electronic course. His teaching opens my eyes to the world of power

electronics and shapes my interest in it. Working with him teaches me how a little perfectionism can make a huge difference in outcome. Our discussion has always been inspiring. And he is so encouraging and supportive when I have doubts and/or difficulties.

I thank Professor Oliver Trescases, who is a former student of Professor Ng and Professor Prodi and a role model of the research group long after he graduated. I feel fortunate to work with Olivier for an extended period of time. I would like to thank him for sharing his skills and experience. And I really appreciate his confidence in me.

I thank all my long-time friends and colleagues in the research group: Marian Chang, Pearl Cao, Armin Fomani, Junmin Lee, Kendy Ng, Amy Shen, Andrew Shorten, Stella Tang, Hao Wang, Gang Xie, Sherrie Xie, William Yu, Abraham Yoo, April Zhao. We collaborated on various projects and/or volunteering works. Its always a pleasant experience to work with them. And their friendship makes my first few years in Toronto more than enjoyable. Special thanks to

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Amy, Andrew, Armin and Kendy, without whom some of my work would be much more difficult to accomplish.

Many thanks to Fuji Electric, who technically and financially support my research works. I feel honored to work with some of their top engineers: Haruhiko Nishio-san, Masahiro Sasaki-

san and Tetsuya Kawashima-san. I am very impressed by their dedication to work and keen focus on details. And I thank them for all valuable experience we shared in Japan.

I thank Jaro Pristupa, for his patient and timely technical support on CAD tools. I thank my colleagues and friends in Prof. Prodis group: Conny Huerta Oliviares, Amir Parayandeh, S.M. Ahsanuzzaman, Behzad Mahdavikhah, Mahmoud Shousha, for their help in my studies and research. I also want to thank all course instructors in the Department of Electrical and Computer Engineering, for the valuable knowledge and experience that I have received.

Last but not the least, I thank my family for their unconditional love and support all through my PhD endeavour. I thank Oscar, for his friendship and love that has been accompanying me even during the toughest times. We have been close friends for so many years and I feel happy and fortunate that we finally come together. I would like to dedicate this thesis to my parents, Xubin Wang and Yi Liu, for their love, understanding, patience and support when I decided to move to Canada; to my loving mother, who just went through probably the hardest time in her life but still stays so strong and is always there when I need her; to my father, who

has always been a role model, a friend, a mentor of me, who unfortunately passed away when I was still editing this thesis and cannot witness my graduation. His love will be with me forever

and I will miss him forever. May he rest in peace.

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Table of ContentsTable of ContentsTable of ContentsTable of Contents

Chapter 1Chapter 1Chapter 1Chapter 1 ................................................................................................................... 1

1.1 Point-of-load Converter Fundamentals ................................................................... 2

1.1.1 Basic Architecture and Operating Principle .............................................. 3

1.1.2 Power Losses in Buck Converter .............................................................. 5

1.1.3 Load Transient Response of Buck Converter ........................................... 9

1.2 Design Requirement and Challenges .................................................................... 13

1.2.1 Small Converter Volume ......................................................................... 13

1.2.2 High Efficiency ....................................................................................... 14

1.2.3 Fast Load Transient Response ................................................................ 15

1.3 Digital Controllers ................................................................................................. 16

1.4 Design for Fast and Smooth Transient Response: Prior Arts ................................ 17

1.4.1 Time-Optimal Control Technique ........................................................... 18

1.4.2 Minimum Deviation Control Technique ................................................. 18

1.4.3 Steered-Inductor and Three-level Buck Converter ................................. 19

1.4.4 Converter Augmentation ......................................................................... 21

1.4.5 Buck Converter with Stepping Inductor ................................................. 23

1.5 Thesis Overview .................................................................................................... 24

Chapter 2Chapter 2Chapter 2Chapter 2 ................................................................................................................. 27

2.1 System Structure and Operating Principle ............................................................ 27

2.2 Steady State Compensator Design ........................................................................ 31

2.3 Controller Implementation .................................................................................... 39

2.3.1 Steady State Operation ............................................................................ 40

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2.3.2 Transient Detection and Load Step Estimation ....................................... 41

2.3.3 Predicting the New Steady-State Duty-cycle .......................................... 43

2.3.4 Generating the Switching Command ...................................................... 44

2.3.5 Blocking State after Transient Suppression ............................................ 45

2.3.6 Soft Starting after Power-on .................................................................... 45

2.4 Selecting the Auxiliary Stage Inductor ................................................................. 47

2.5 Sizing the Auxiliary Stage Transistors .................................................................. 51

2.5.1 Influence of Ron_A on the Inductor Current Model .................................. 51

2.5.2 Influence of Ron_A on the Dynamic Performance .................................... 53

2.5.3 Auxiliary Stage Sizing Consideration ..................................................... 56

2.6 Prototype Design and Experimental Results ......................................................... 58

2.6.1 Prototype Converter Using Discrete Output Stages ................................ 58

2.6.2 Prototype Converter Using Integrated Output Stages ............................. 63

2.7 Chapter Summary .................................................................................................. 68

Chapter 3Chapter 3Chapter 3Chapter 3 ................................................................................................................. 71

3.1 System Structure and Operating Principle ............................................................ 72

3.1.1 Steady-State Operation ............................................................................ 74

3.1.2 Heavy-to-light Load Transient Suppression ........................................... 75

3.1.3 Light-to-heavy Load Transient Suppression ........................................... 81

3.1.4 Inductor Volume ..................................................................................... 86

3.1.5 Conceptual Verification .......................................................................... 86

3.2 Steady State Controller Design ............................................................................. 90

3.3 Design of the Dual-mode Digital Control Unit ..................................................... 97

3.3.1 Heavy-to-Light Transient Operation ....................................................... 99

3.3.2 Light-to-Heavy Load Transient Operation ............................................ 100

3.3.3 Seamless Transition to Steady State ..................................................... 100

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3.3.4 Prevention of Undesired Mode Transitions .......................................... 102

3.4 Energy Recycling and Losses of the Auxiliary Switches ................................... 104

3.5 Prototype Design and Experimental Results ....................................................... 109

3.5.1 Prototype Implementation and Set-up ................................................... 109

3.5.2 Transient Performance .......................................................................... 112

3.5.3 Efficiency Comparison .......................................................................... 116

3.6 Chapter Summary ................................................................................................ 121

Chapter 4Chapter 4Chapter 4Chapter 4 ............................................................................................................... 123

4.1 Contributions ....................................................................................................... 123

4.2 Future Work ........................................................................................................ 126

4.2.1 Precise Load Step Estimation ................................................................ 126

4.2.2 Calibration Against Inductor Current Slew Rate Variation .................. 127

4.2.3 Design for Integration: Sizing the Auxiliary Switches ......................... 127

4.2.4 Integrated Controller ............................................................................. 128

References ............................................................................................................... 130

Appendix A ............................................................................................................... 140

Appendix B ............................................................................................................... 144

Appendix C ............................................................................................................... 147

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List of TablesList of TablesList of TablesList of Tables

TABLE 1.1 Typical PoL Converter Application and Critical Design Requirements 13

TABLE 1.2 Trade-offs Between Different Power Losses 14

TABLE 1.3 Trade-offs Between Converter Volume, Conversion Efficiency and Peak Load Transient Deviation 15

TABLE 2.1 Design Parameters of the Main Converter 32

TABLE 2.2 Design Parameters of ADC and DPWM Blocks 34

TABLE 2.3 Design Parameters of the Simulated Converter 54

TABLE 2.4 Component List of the Discrete Prototype 59

TABLE 2.5 Simulated On-Resistances of the Power Transistors 64

TABLE 2.6 Summary of Test Conditions 65

TABLE 2.7 Summary of Transient Performance 67

TABLE 3.1 Design Parameter of the Simulated Converter 86

TABLE 3.2 Design Parameters of the CPM Buck Converter 94

TABLE 3.3 Component List of the Prototype Converter 111

TABLE 4.1 Comparison of Converter Topology and Control Methods 124

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List of FiguresList of FiguresList of FiguresList of Figures

Figure 1.1 Typical PoL architecture for PCB power supplies. 2

Figure 1.2 Typical buck converter topology. 3

Figure 1.3 Steady state waveforms of a conventional buck converter in continuous conduction mode. 4

Figure 1.4 A typical Vgs vs. Qg curve for a power MOSFET. 7

Figure 1.5 Turn-on and turn-off waveforms of a power MOSFET. 8

Figure 1.6 Buck converter with a voltage mode control loop. 9

Figure 1.7 Best-case heavy-to-light load transient response. 11

Figure 1.8 Transient current and voltage waveforms of a buck converter using time-optimal control method to recover a heavy-to-light load transient. 17

Figure 1.9 Transient current and voltage waveforms of a buck converter using minimum deviation control method to recover a heavy-to-light load transient. 19

Figure 1.10 Improving heavy-to-light load transient response using (a) steered inductor topology, (b) three-level buck converter and (c) buck-derived converter. 20

Figure 1.11 Improving load transient response through converter augmentation. 21

Figure 1.12 Theoretical waveforms for auxiliary stage controlled as (a) constant current source and (b) current source with adaptive slope. 22

Figure 1.13 Improving load transient response through using stepping inductor. 23

Figure 2.1 A digitally controlled DC-DC converter with an auxiliary output stage for fast load transient recovery. 28

Figure 2.2 Theoretical waveforms of load current iload(t), main stage inductor current iLM(t), auxiliary stage inductor current iLA(t) and output voltage deviation vout(t) VREF under a heavy-to-light load transient. 29

Figure 2.3 (a) Architecture of the digital voltage mode controller for regulating steady-state output voltage, and (b) linearized model of the closed-loop system. 31

Figure 2.4 Bode plot of the uncompensated system. 35

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Figure 2.5 Block diagram of the digital PID compensator. clkfs is the steady-state clock signal. It is synchronized with the switching cycle of the converter. 36

Figure 2.6 Bode plots of the compensated system using (a) continuous-time domain compensator and (b) discontinuous-time domain compensator. 37

Figure 2.7 Block diagram of the controller. 39

Figure 2.8 State diagram of the digital controller. 40

Figure 2.9 Estimating load current step iload from vout(t) deviation. 41

Figure 2.10 Equivalent circuit of the converter during the load current estimation period. 42

Figure 2.11 Compensate for the extra charge Q1 by increasing ton and toff. 44

Figure 2.12 Larger LM/LA ratio, e.g. smaller LA, results in smaller voltage overshoot but bigger voltage undershoot during heavy-to-light load transient recovery. 47

Figure 2.13 Capacitor and inductor currents during heavy-to-light load transient recovery. 48

Figure 2.14 Finding proper LM/LA ratio by trading off vOvershoot and vUndershoot during the heavy-to-light load transient recovery. 50

Figure 2.15 Finding proper LM/LA ratio by trading off vOvershoot and vUndershoot during the light-to-heavy load transient recovery. 50

Figure 2.16 On-resistance causes voltage drop across auxiliary stage transistor. 51

Figure 2.17 Theoretical waveforms of load current (iload), main stage inductor current (iLM), auxiliary stage inductor current (iLA) under heavy-to-light load transient taking into account the auxiliary switches' on-resistance. 52

Figure 2.18 Transient output voltage waveforms of converters using auxiliary switches with different on-resistances. 55

Figure 2.19 Transient current in the auxiliary and main stage. 56

Figure 2.20 Comparison of the active time for auxiliary output stages with different on-resistances. 57

Figure 2.21 Prototype converter to verify the transient suppression method and block diagram of the switching loads. 58

Figure 2.22 Steady-state conversion efficiency of a 6V-to-1V prototype converter. 60

Figure 2.23 Heavy-to-light load transient performance using (a) & (b) single-stage time-optimal control method and (c) proposed transient suppression method. 62

Figure 2.24 Block diagram of (a) the integrated dual output stage and (b) the gate driver. 63

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Figure 2.25 Micrograph of the integrated dual output stage. 64

Figure 2.26 Steady state efficiency of the integrated output stage. 65

Figure 2.27 Heavy-to-light load transient performance using (a) single-stage time-optimal control method and (b) transient suppression method using dual output stage. 66

Figure 3.1 The flyback-transformer based buck (FTBB) converter and the mixed-signal controller. 72

Figure 3.2 Equivalent circuit in steady-state operation. 74

Figure 3.3 Key current and voltage waveforms during a heavy-to-light load transient recovery process. 76

Figure 3.4 Equivalent circuit during during leakage inductance energy release (t1~t2) for large LLEAK. 77

Figure 3.5 Equivalent circuit during leakage inductance energy release (t1~t2) for small LLEAK. 78

Figure 3.6 Equivalent circuit showing that the energy in LLEAK is absorbed by the RC snubber circuit. 79

Figure 3.7 Equivalent circuit during heavy-to-light load transient recovery (t2 ~ t3). 80

Figure 3.8 Key current and voltage waveforms during a heavy-to-light load transient recovery process. 82

Figure 3.9 Equivalent circuit of the converter when current pulses in ip(t) suppress voltage undershoot (t1~t2). 83

Figure 3.10 Equivalent circuit of the converter when extra energy in LLEAK is recycled to the input power source (t2~t3). 84

Figure 3.11 Equivalent circuit of the converter when currents iLM(t) and ip(t) increase with a slew rate equal to an equivalent conventional buck converter (t3~t4). 85

Figure 3.12 Simulation waveforms of a buck converter using (a) conventional minimum-deviation control method and (b) the proposed method under a 3 A load current transient. 88

Figure 3.13 Simulation waveforms of a buck converter using (a) conventional minimum-deviation control method and (b) the proposed method under a +3 A load current transient. 89

Figure 3.14 (a) Architecture of the current mode controller that regulates the steady state operation, and (b) linearized model of the closed loop system. 90

Figure 3.15 Theoretical waveforms of the current-programmed control loop. 91

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Figure 3.16 Block diagram of the digital PI compensator. 93

Figure 3.17 Bode plots of (a) the uncompensated loop transfer function and (b) the continous time-domain PI compensator. 95

Figure 3.18 Bode plots of the compensated loop transfer function using (a) continous-time PI compensator and (b) the digital PI compensator. 96

Figure 3.19 Block diagram of the controller. 97

Figure 3.20 State diagram of the digital controller. 98

Figure 3.21 Simplified equivalent circuits of the converter during the load current estimation period: (a) for a heavy-to-light load transient; (b) for a light-to-heavy load transient. 101

Figure 3.22 Simulation results for a full-load to no-load transient for the FTBB converter (left) and a buck converter (right). Top waveforms: output voltages vout(t); Middle waveforms: load currents iload(t); Bottom waveforms: input currents iin(t) of the converters. 107

Figure 3.23 Simulation results for a 100% to 33% load transient for the FTBB converter (left) and a buck converter (right). Top waveforms: output voltages vout(t); Middle waveforms: load currents iload(t); Bottom waveforms: input currents iin(t) of the converters. 108

Figure 3.24 Block diagram of the FTBB converter prototype. 109

Figure 3.25 Picture of the prototype FTBB converter. 110

Figure 3.26 Transient response of the conventional buck converter for a 3 A heavy-to-light load transient. Top: the buck-inductor current iL(t), scale 4 A/div; Middle: ac component of the output voltage vout(t), scale 100 mV/div; Bottom: load step command iload(t). Time scale is 20 s/div. 113

Figure 3.27 Transient response of the FTBB converter for a 3 A heavy-to-light load transient. Top: the primary current ip(t), scale 4 A/div; Middle: ac component of the output voltage vout(t), scale 100 mV/div; Bottom: load step command iload(t). Time scale is 20 s/div. 113

Figure 3.28 Transient response of the conventional buck converter for a 3 A light-to-heavy load transient. Top: the buck-inductor current iL(t), scale 4 A/div; Middle: ac component of the output voltage vout(t), scale 50 mV/div; Bottom: load step command iload(t). Time scale is 5 s/div. 115

Figure 3.29 Transient response of the FTBB converter for a 3 A light-to-heavy load transient. Top: the primary current ip(t), scale 4 A/div; Middle: ac component of the output voltage vout(t), scale 50 mV/div; Bottom: load step command iload(t). Time scale is 5 s/div. 115

xiv

Figure 3.30 Test setup for power consumption measurement. 116

Figure 3.31 Steady-state efficiency of the conventional single stage buck converter and the FTBB converter. 118

Figure 3.32 Dynamic power consumption of the FTBB converter and the conventional single stage buck converter. 120

Figure 3.33 Comparison of effective efficiency of the conventional buck and the FTBB converters under frequently changing load conditions. 120

Figure A.1 Ideal waveforms of load current iload(t), main stage inductor current iLM(t), auxiliary stage inductor current iLA(t) and output voltage deviation vout(t)-VREF under a heavy-to-light load transient. 140

Figure A.2 Waveforms of main stage inductor current iLM(t), auxiliary stage inductor current iLA(t) and output voltage deviation vout(t)-VREF under a heavy-to-light load transient, taking into account the transient detection and load estimation delays. 141

Figure A.3 Equivalent circuit during the current steering phase of a heavy-to-light load transient recovery with auxiliary switches' on-resistances included. 145

Figure A.4 Equivalent circuit during light-to-heavy load transient recovery with auxiliary switches' on-resistance included. 146

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List of AppendicesList of AppendicesList of AppendicesList of Appendices

Appendix A A Practical Calculation of Auxiliary State On/Off Times .................................. 140

Appendix B Influence of the the Auxiliary Switches' On-resistance on the Transient Performance of the Flyback-Transformer Based Buck Converter ...................... 143

Appendix C List of Publications .............................................................................................. 147

1

Chapter 1Chapter 1Chapter 1Chapter 1

IntroductionIntroductionIntroductionIntroduction

In modern low-power applications such as mobile devices, consumer electronics, and communication equipment, point-of-load (PoL) switch-mode power supplies (SMPS) are required to provide tightly regulated voltage with small deviation during load transients. In these

systems, usually operating with no larger than 1V supply voltage, the SMPS output voltage deviation is typically limited to tens of millivolts, to ensure proper system performance [1]. It is also highly desirable to minimize the volume of the SMPS reactive components, i.e. their output filters, which in the targeted applications usually take a significant portion of the entire device.

As a guideline for the power supply designers, the Power Source Manufacturers Association (PSMA) published the 2011 PSMA Power Technology Roadmap (PTR). For non-isolated PoL DC-DC converters, PSMA provides an outlook on 2010-2015 technology trends that includes but not limited to: tighter voltage set point windows; lower output voltage ripple; faster transient response; higher efficiency and power density [2].

This thesis focuses on improving the transient response of sub-3 W PoL converters in

particular. These low-power PoL converters have wide usage in telecommunication and/or data-communication systems as well as battery-powered systems. In Chapter 1 of this thesis, a brief introduction to modern PoL power solutions will be provided, followed by an overview of the research work to be presented. Chapters 2 and 3 introduce two different approaches to improve the load transient performance of PoL converters without degrading the power conversion efficiency. Conclusions and suggestions for future work will be given in Chapter 4.

In this introductory chapter, fundamentals on DC-DC converters will be reviewed in Section 1.1. The design requirements proposed in the 2011 PSMA report, as well as various challenges will be analyzed in Section 1.2. The application of digital control technique in low

2

power DC-DC converters will be briefly reviewed in Section 1.3. Prior research work focusing on fast and smooth transient response for DC-DC converters will be summarized and discussed in Section 1.4. An overview of the research work conducted during the progress of this thesis

will be provided in Section 1.5.

1.1 Point-of-load Converter Fundamentals

With the development of modern semiconductor technology, higher level of integration enables electronic systems to incorporate more and more functions onto increasingly smaller printed circuit boards (PCB) [3]-[5]. As a result, the landscape of PCB has changed from multiple ICs with a single power supply voltage to a combination of microprocessors (Ps), DSPs, analog and digital circuits operating with multiple supply voltages ranging from 3.3V to less than 1V (see Figure 1.1). For power supply designers, it is inevitable to shift from the traditional distributed power architecture to a two-stage conversion scheme, which includes an

AC-DC converter that converts the AC line voltage to an intermediate DC bus voltage, and a set of DC-DC converters that convert the DC bus voltage to the desired value at the point-of-load

(PoL) [6]-[7]. By placing PoL converter near the load ICs, the long wiring between the DC bus and the load can be eliminated. This enables more precise regulation of the voltage supply while fulfilling low-voltage and high-current requirements.

Figure 1.1 Typical PoL architecture for PCB power supplies.

3

1.1.1 Basic Architecture and Operating Principle

In a typical point-of-load power supply architecture, PoL converter converts the bus voltage into a lower voltage required by the load, as shown in Figure 1.1. The PoL converter is usually implemented in a buck or step-down configuration as shown in Figure 1.2. Vin is the

input voltage, which can be supplied by batteries, DC bus, or other DC voltage sources. The switch that is connected between the input source and the inductor L is called the main switch

(MS). It is usually implemented with a power MOSFET. The other switch connected between the inductor L and the ground terminal is the rectifier. It can be implemented with either a power MOSFET (synchronous rectifier, SR) or a free-wheeling diode (asynchronous rectifier). MS and SR turn on alternatively within each switching period Ts, with a switching frequency, fs = 1/Ts. The common node in between the MS, SR switches and inductor L is called the switching node, which is denoted as vx.

Basic steady-state voltage and current waveforms of a conventional buck converter under continuous conduction mode (CCM) are as shown in Figure 1.3. Within each switching period Ts, the percentage of time when the MS is on while SR is off is denoted as the duty-cycle D. On the other hand, the percentage of time when the MS is off while SR is on is generally denoted as

D' or 1 D. When the MS switch is on, the switching node vx is pulled to Vin. The current iL(t) in the inductor ramps up with a slew-rate of kD. When the MS is off, the switching node vx is pulled to ground. The current iL(t) in the inductor ramps down with a slew-rate of kD'. The inductors ripple current iL is defined as half the magnitude of the peak-to-peak variation of

iL(t), which is determined by (1.1).

Figure 1.2 Typical buck converter topology [8].

4

( ) ( )12 2 2

in out s in outL D s

s

V V DT V V Di k DTL Lf

= = = (1.1)

For a buck converter operating in steady state, the inductor current iL(t) stays the same at the beginning and the end of each switching cycle. This phenomenon is called "inductor volt-second balance" [8], from which the relationship between the input voltage Vin and average output voltage Vout can be derived as

''

'

D s D s

in out outs s

out in

k DT k D TV V VDT D T

L LV V D

=

=

=

. (1.2)

As shown in Figure 1.3, the actual output voltage waveform vout(t) has small ripple superimposed on the average value Vout due to the charging and discharging of output capacitor

MS on

SR off

MS off

SR onVin

vx(t)

Iload

iL(t)

kD kD

vout(t)

iC(t)

iL

Vout vripple

DTs DTs

t

t

t

t0 t0+Ts

Figure 1.3 Steady state waveforms of a conventional buck converter in continuous conduction mode.

5

Cout within each switching period. The ripple voltage vripple is defined as half the peak-to-peak

variation of vout(t), which is proportional to the area of the grey triangle surrounded by the iC(t) waveform.

1 12 2 2 8

s L sripple L

out out

T i Tv i

C C = = (1.3)

In steady state, vout(t) will return to the same voltage after each switching period Ts due to "capacitor charge balance" [8], which implies that the averaged capacitor current iC within each Ts equals zero. As a result, the following expression can be deduced for the average inductor current IL, where Iload is the steady-state load current.

L loadI I= (1.4)

1.1.2 Power Losses in Buck Converter

Understanding different sources of power losses in buck converter helps power supply designers to analyze and optimize conversion efficiency. Mechanisms of converter's power losses have been comprehensively studied and illustrated in [10]-[11], among which the conduction loss, gate-drive loss and switching loss at the output power stage of the buck converter are the dominant ones [9] and thus will be illustrated in details below.

A Conduction Loss

The conduction loss mainly results from the on-resistance of power switches (Ron,MS and Ron,SR), equivalent series resistance (ESR) of output inductor (RL), and ESR of output capacitor (RESR).

The conduction loss on the power switches is given by

2 2, , , , ,cond SW on MS rms MS on SR rms SRP R I R I= + . (1.5)

Ron,MS and Ron,SR are inversely proportional to the aspect ratio (W/L) of the power MOSFETs. For a fixed channel length (L), power MOSFET with bigger width (W) has smaller on-resistance but occupies a larger chip area. Irms,MS and Irms,SR are the root-mean-square (rms) drain-to-source currents that flow through the MS and SR switches, respectively. Irms,MS and Irms,SR are evaluated

6

from the averaged inductor current (equals Iload for buck converters) as well as the amount of inductor current ripple (iL) defined by (1.1).

22

,( )

3L

rms MS loadiI D I = + (1.6)

22

,'( )

3L

rms SR loadiI D I = + (1.7)

The current flowing through the output inductor is the sum of the switch currents. Thus conduction loss on the inductor's ESR can be expressed as

22 2

, ,( )

3L

cond L L rms L L loadiP R I R I = = + . (1.8)

As shown in Figure 1.3, when a buck converter is in steady state, the current iC(t) flowing into the output capacitor Cout contains only the ripple portion of iL(t). Thus the conduction loss on the capacitor ESR is given by

2, 3

Lcond C ESR

iP R = . (1.9)

If we define the equivalent series resistance of the buck converter to be

, ,'eq on MS on SR LR DR D R R= + + , (1.10)

the total conduction loss obtained by combining (1.5), (1.8), and (1.9) can be simplified as

22 ( )

3L

cond eq load eq ESRiP R I R R = + + . (1.11)

For a given load current Iload, the first term on the right side of (1.11) can only be reduced by selecting power MOSFETs and inductors with small series resistances. The second term, according to (1.1), can be minimized by using a bigger inductor or switching at a higher frequency.

7

B Gate-drive Loss

In each switching cycle, the MS and SR power switches turn on and off alternatively, which requires periodic charging and discharging of the power MOSFETs gate capacitances. The amount of power provided by the gate driver during this process is usually called "gate-drive

loss" or "gating loss". It is independent of the gate driver's driving capability, but heavily dependent on the physical structure of the MOSFET switches and the switching frequency, fs. A generic expression of gate-drive loss is given in (1.12) [11]

gate g gs sP Q V f= , (1.12)

where Vgs is the gate-to-source voltage of a power MOSFET when it is ON. In conventional

buck converters, this voltage usually equals to the input voltage Vin. In converters adopting advanced control scheme [13]-[17], the Vgs swing can be dynamically adjusted to achieve efficiency optimization for different load conditions. Qg is the total gate charge under a given Vgs voltage. It is usually specified by MOSFET manufacturers using the Vgs vs. Qg curve as shown in Figure 1.4, which assumes the gate is driven by a constant current source. There are several aspects that influence Qg, such as the gate dielectric material and fabrication process [18]-[19],

00

5 10 15 20

2

4

6

8

10

12

Qg (nC)

Vg

s(V

)

Increasing Vds

Figure 1.4 A typical Vgs vs. Qg curve for a power MOSFET [12].

8

the layout of the MOSFET [20]-[21], and the size of the device, etc. Generally speaking, a MOSFET with larger gate area (WL) has bigger Qg and thus requires more gate-drive power to turn on.

C Switching Loss

Another major source of power loss is the power dissipated on the channel of power MOSFET switch during every turn-on and turn-off process. Due to the existence of parasitic capacitances, the actual power MOSFET switches have finite turn-on and turn-off time. During each switching action, both the drain-to-source voltage vds and drain-to-source current ids of the MOSFET ramp with finite slew-rates. Theoretical ids and vds waveforms during hard turn-on and turn-off for a power MOSFET is as shown in Figure 1.5. This is an approximation of the actual waveforms, which usually contain a significant amount of ringing, but is still accurate enough to estimate the switching loss. The shaded overlap areas of the ids and vds waveforms indicates switching loss. This is usually referred to as hard-switching loss. Assuming a turn-on time of tsw,on and a turn-off time of tsw,off, the switching loss in a conventional buck converter is given by

, ,

, ,

( )2

( )2

ds dsSW sw on sw off s

in loadsw on sw off s

V IP t t fV I

t t f

= +

+

. (1.13)

ids

vds

tsw,on tsw,off

Switching loss happens in the

shaded section

Vds Ids

Figure 1.5 Turn-on and turn-off waveforms of a power MOSFET [11].

9

1.1.3 Load Transient Response of Buck Converter

The transient response of a buck converter reflects its capability to adapt to sudden changes in input voltage (line transient) and/or load current (load transient). This work focuses on the load transient response, which is usually evaluated by the amount of peak output voltage

deviation as well as the time it takes for the output voltage to return to its steady state value (recovery time).

Load transient response of a conventional buck converter is mainly determined by the control loop bandwidth, phase margin and the characteristic of output LC filter.

A typical voltage-mode control loop is as shown in Figure 1.6. This negative feed-back scheme applies to both analog and digitally controlled buck converters. The output voltage vout is sampled and compared with a voltage reference VREF, generating an error signal e. A compensator module Gc is inserted to tune the closed-loop transfer function that ideally has

L

Coutvout

iloadvx

iL

Vin

MS

SR

cMS(t) cSR(t)

Gate

Drivers

Dead-time Controllerc(t)

sample vout

VREF

eGc

ecPWMc(t)

iC

Figure 1.6 Buck converter with a voltage mode control loop.

10

infinite DC gain, wide loop bandwidth and enough phase-margin to ensure system stability. The compensated signal ec is fed into a pulse-width modulation (PWM) block which generates a control signal c(t) that determines the duty-cycle. The dead-time module converts c(t) into two non-overlapping signals cMS(t) and cSR(t) to prevent simultaneous turn-on of the two power switches.

When vout deviates from the reference voltage, the control loop reacts by modulating the duty-cycle, i.e. the on and off time of MS and SR, trying to bring vout back to VREF. The close-loop system's cross-over frequency fc determines how fast the modulation can be performed. A phase margin of greater than 45 is usually required to ensure stability and to suppress output voltage ringing during transient recovery. For a voltage-mode controlled converter, increasing the close-loop bandwidth can also improve transient response provided that the phase margin is maintained. However, the maximum close-loop bandwidth of the controller is usually limited to

1/10th to 1/5th of the switching frequency [8], beyond which the control loop design based on small-signal linearization techniques is no longer valid and stability is difficult to guarantee [22].

For a buck converter, the recovery time after load current changes is inherently limited by the slew-rate of inductor current. A heavy-to-light load step example is as illustrated in Figure

1.7. In this best-case transient response, the inductor current iL(t) ramps down with maximum possible slew-rate immediately after the load step occurs. This usually cannot be achieved using a conventional linear controller based on small-signal model due to limited close-loop bandwidth. Instead, a number of non-linear controllers have been implemented [23]-[26] to address this issue.

After a sudden negative load current step with amplitude iload occurs at time t0, the MS

switch is turned off and the SR switch is turned on. The inductor current iL(t) ramps down with slew-rate k1 for a time period noted as toff. At this point the SR is turned off and the MS is turned on. The inductor current iL(t) ramps up with slew-rate k2 for a period of ton until it reaches the new load current level. Ideally, toff and ton are set such that the output voltage vout is brought back

to its steady-state value within a single on-off switching action. In this case, it is required that the excess charge Q1 injected to the output capacitor Cout is balanced by Q2, the amount of charge taken out, as represented by the shaded areas in Figure 1.7.

11

The inductor current slew-rates k1 and k2 are determined by

1

2

out

in out

VkL

V VkL

=

=

. (1.14)

Assuming that the magnitude of the load current step, iload is much larger than the steady-state

inductor current ripple, iL, the time intervals toff and ton can be calculated by equating Q1 and Q2:

1 1 2

1(1 )1 /

loadoff

it

k k k

= ++

(1.15)

2 1 2

11 /

loadon

it

k k k

=

+ (1.16)

Figure 1.7 Best-case heavy-to-light load transient response.

12

By combining (1.15) and (1.16) and replacing k1 and k2 with (1.14), the total recovery time TR is given by:

(1 1 )load outRout in out

i L VTV V V

= + +

. (1.17)

The best-case peak voltage deviation, vout during the transient recovery can be calculated from

21

2load

outout out out

i LQv

C C V = = . (1.18)

Equations (1.17) and (1.18) indicate that both the best-case transient recovery time TR and the peak voltage deviation vout are directly proportional to the inductance L in the buck output

stage. It is an inherent limitation regardless of controller architecture or switching frequency.

13

1.2 Design Requirement and Challenges

TABLE 1.1 outlines some of the typical applications of point-of-load (PoL) power converters and their critical design requirements. Generally speaking, small volume, high efficiency and fast reaction to load transients are the top preferred characteristics of PoL

converters, although different application environment may have different emphasis on each of these requirements. The trade-offs and design challenges will be discussed in details in the following subsections.

1.2.1 Small Converter Volume

Continuously shrinking printed circuit board (PCB) geometry and the increasing demand for more functions per unit area make it necessary for power converters to have high power

density and small physical size. Power-supply-in-a-package (PSiP) allows the integration of the DC-DC controller and the output power stage into the same package [2], [30]. There has also been a growing trend for PoL converters to be implemented with digital controllers [31]-[32]. Instead of using bulky external resistor-capacitor (RC) network as in most analog controlled converters [33]-[34], loop compensation in a digitally controlled converter is performed through algorithms programmed on-chip.

TABLE 1.1. TYPICAL POL CONVERTER APPLICATION AND CRITICAL DESIGN REQUIREMENTS

Applications Design Requirements

Portable electronic devices [22] Small volume, high efficiency

General purpose FPGA/Ps core power supply [27][28]

High efficiency, small volume, fast response to highly dynamic load

General purpose FPGA/Ps I/O power supply [27][28] High efficiency, small volume

Tele/Data communication system [29]

High efficiency, fast response to highly dynamic load

Digital media system [45] Fast response to highly dynamic load, small volume, high efficiency

14

On the other hand, virtually all commercial PoL converter ICs in the 3-W power level require off-chip output LC filters, which take up considerable percentage of the total converter volume [22]. Efforts have been made to reduce the size of passive components by running the converter at very high switching frequencies (e.g. multi-MHz). However, this often leads to increased frequency-related losses such as gate-drive loss and switching loss, which inevitably degrade the power conversion efficiency.

1.2.2 High Efficiency

The power conversion efficiency of DC-DC converters is defined as the ratio of the

output power over the input power. The major sources of efficiency degradation include conduction, gate-drive and switching losses, which have been introduced in Section 1.1.2.

Though the peak power-conversion efficiency of a PoL converter is typically advertised as the primary benchmark, a good efficiency profile with high efficiency over the entire load range is usually more desirable. For PoL converters under frequent load current changes, the overall efficiency, taking into account both steady state and transient conditions, is also an important specification.

Among the three major sources of power loss, the gate-drive and switching losses are proportional to the switching frequency and the size of power switches. Conduction loss increases with the inductor current and the ripple current. When designing a converter for high efficiency, trade-offs among different types of power loss are usually required. TABLE 1.2 summarizes these trade-offs qualitatively.

TABLE 1.2. TRADE-OFFS BETWEEN DIFFERENT POWER LOSSES

Actions Conduction Loss Gate-Drive Loss Switching Loss Increase switching

frequency fs Decrease due to

smaller iL Increase Increase

Decrease switching frequency fs

Increase due to bigger iL

Decrease Decrease

Increase channel width of power MOSFET

Decrease due to smaller Ron

Increase due to higher Qg

Increase due to longer tsw,on/off

Decrease channel width of power MOSFET

Increase due to bigger Ron

Decrease due to lower Qg

Decrease due to shorter tsw,on/off

15

1.2.3 Fast Load Transient Response

PoL converters, depending on application environment, may undergo frequent load current changes at a high repetition rate. For example, PoL converters in telecommunication

equipment can support a load transient repetition rate of 5 ~ 10 kHz [35]; and PoL converters in the voltage regulator module (VRM) for processors may experience a load transient repetition rate of over 200 kHz [4][36]. In order to guarantee proper performance of the load ICs, these PoL converters are required to provide a stable output voltage and keep the voltage fluctuation within a tight tolerance band. They must be able to respond to a load transient quickly without

significant disturbance at the output voltage.

Equation (1.18) indicates that a large output filter capacitor Cout could help suppressing the peak transient voltage deviation. But a large Cout normally results in higher cost and bigger physical volume. Fast transient response in the controller allows the converter to not solely rely

on a large Cout to maintain the output voltage within a certain tolerance during load transients. For a PoL converter using linear control methods, this usually requires the use of a small output LC filter and switching at high frequencies to ensure a wide control-loop bandwidth. However, the improvement in dynamic performance is usually traded-off by degradation in efficiency due to frequency related power losses [37].

The trade-offs between converter volume, conversion efficiency and peak voltage deviation during load transient are summarized in TABLE 1.3. These trade-offs make the design consideration of PoL converters non-trivial. Thus new converter topologies and control algorithms need to be explored in order to achieve an optimum performance balance.

TABLE 1.3. TRADE-OFFS BETWEEN CONVERTER VOLUME, CONVERSION EFFICIENCY AND PEAK LOAD TRANSIENT DEVIATION

Actions Volume Efficiency Peak Vout Increase switching

frequency fs - lower smaller Decrease output stage

inductance L smaller lower smaller

Increase output stage capacitance Cout

bigger - smaller

16

1.3 Digital Controllers

With the development of modern VLSI technology, the cost for implementing digital

integrated circuit continues to reduce over the years [1]. Digital controllers in power electronics are also gaining interests due to their well-known advantages such as re-programmability,

flexibility, IP re-use across different fabrication technologies, quick hardware verification via FPGA, low sensitivity to process, voltage and temperature (PVT) variations, direct interface with digital buses and other systems, ability to implement sophisticated control algorithms and achieve robust compensation over a wide-range of specifications [38].

Low-power digitally controlled DC-DC converters have shown steady improvement since the first counter-based digital pulse-width modulator (DPWM) design [39]. The introduction of the delay-line based DPWMs [40]-[41] made digital controllers a viable option in low power portable environment. Traditional digital controller designs are intended to mimic the functionality of analog compensators. Therefore, most digital controllers can only have similar performance as their analog counterparts, typically at a higher implementation cost and power consumption. The true capability of low-power digital control becomes apparent with the introduction of more flexible designs, such as the use of segmented output stage to dynamically

adjust the size of the output transistors according to load conditions to achieve high power conversion efficiency over a wide range of load current [16]-[17], [42]-[45], dead-time correction schemes to continuously optimize the dead-times for the power switches [46]-[50], digital spread-spectrum techniques that effectively suppress conductive electromagnetic interference (EMI) [51]-[53], and digital auto-tuning techniques that can adjust compensator parameters on-the-fly to accommodate passive component variations [54]-[58]. Digital controllers also have the ability to switch seamlessly between operating modes, such as pulse-width modulation (PWM), pulse-frequency modulation (PFM), pulse-skipping mode, etc. [59]. They are also capable of realizing advanced control algorithms to achieve near-optimal load transient response.

17

1.4 Design for Fast and Smooth Transient Response:

Prior Arts

Various novel strategies were proposed to improve the load transient response of PoL buck converters. In general, these techniques can be categorized into linear control techniques and non-linear control techniques.

Linear control techniques in [60]-[63] are based on the small-signal model. They re-shape the converter's close-loop transfer function during load transient to temporarily increase the loop bandwidth. However, only a moderate improvement in transient response is observed since the maximum loop bandwidth in these systems is still limited by the stability and phase margin requirement.

Non-linear control techniques are gaining popularity since they enable the converters to break the bottle-neck of control loop bandwidth, switching frequency and/or the physical constrains of output LC filter [64]. As a result, they can drastically improve the dynamic response of converters and, to some extent, mitigate the trade-offs in efficiency and physical volume.

In this section, existing non-linear control techniques are reviewed. The advantages and

iload(t) Q1

Q2Q1 = Q2

iL(t)

vout(t)

k1 = -Vout/L

vout Q1Vout

toff ton

iload

Figure 1.8 Transient current and voltage waveforms of a buck converter using time-optimal control method to recover a heavy-to-light load transient.

18

disadvantages of each solution are discussed.

1.4.1 Time-Optimal Control Technique

Time-optimal control, also known as one-step recovery control, has been proven to achieve the optimum load transient response for a given output LC filter, without modifying the topology of the buck output stage. Time-optimal controlled buck converters based on the capacitor charge-balance algorithm [24]-[26], [65]-[67] or state-space switching surface [68]-[71] have been demonstrated. Ideal transient waveforms are as illustrated in Figure 1.8. The controller responds to a load transient with a single on/off or off/on switching action. In the

heavy-to-light load transient example shown in Figure 1.8, the SR switch is kept on such that the inductor current iL(t) ramps down till it equals to the load current iload(t). At this point the output overshoot voltage, vout reaches its peak value, which is proportional to the amount of charges

injected into the output capacitor Cout, as indicated by Q1. The turn-off (toff) and turn-on (ton) times in a time-optimal controller are determined such that both the output voltage and inductor current are fully restored by the end of the recovery process. This method provides the shortest-possible recovery time and the minimum-possible transient voltage deviation for a conventional

buck converter. However, the peak output voltage deviation, vout during load transient is still

limited by the inductor current slew-rate, k1, which in turn is dependent on the output stage

inductance as well as the input and output voltages of the converter [74][75].

21

12load

outout out

iQv

C C k = =

(1.19)

1.4.2 Minimum Deviation Control Technique

Minimum deviation control provides a simpler solution compare to the time-optimal control method, aiming at minimizing the output voltage deviation but not the transient recovery

time. A minimum deviation controlled two-phase buck converter was demonstrated in [72][73]. Similar to the time-optimal control method, minimum deviation controller also responds to a load transient with a single on/off or off/on switching action. As shown in Figure 1.9, after a heavy-to-light load transient occurs, the controller turns on the SR switch to recover the inductor current iL(t) with maximum possible slew-rate, k1. After iL(t) catches up with the load current iload(t), the controller starts to regulate the output voltage with conventional linear control

19

method, rather than trying to achieve capacitor charge balance. The peak voltage deviation vout

obtained using this method is the same as (1.19), which is proportional to the amount of charge Q1 and inherently limited by the current slew-rate k1 in the power inductor.

1.4.3 Steered-Inductor and Three-level Buck Converter

In order to overcome the physical limitation of inductor current slew-rate in conventional buck output stages, several approaches were introduced in [76]-[79] where additional power transistors and/or diodes are used to increase the voltage applied across the power inductor during transient recovery.

Figure 1.10 (a) illustrates the equivalent circuit of a buck converter with steered-inductor during heavy-to-light load transient recovery [76]-[77]. Two additional switches S0 and S1 are used. In steady state, S0 is kept on and S1 is kept off while MS and SR transistors operate as in a conventional buck converter. To assist heavy-to-light load transient recovery, switches MS and S0 are turned off, SR and S1 are turned on to "steer" the inductor current back to the input voltage

source following the highlighted path. During this time period, the inductor current, iL ramps down with a slew-rate determined by k = Vin/L. For PoL converters with low voltage conversion ratio, this value is usually much higher than the slew-rate, k1 in a conventional buck converter as expressed in (1.14).

iload(t) Q1

iL(t)

vout(t)vout Q1

k1 = -Vout/Liload

Vout

Figure 1.9 Transient current and voltage waveforms of a buck converter using minimum deviation control method to recover a heavy-to-light load transient.

20

The three-level buck converter [78] makes use of the input capacitor, Cin in the buck converter to generate an auxiliary power supply during transient recovery. As shown in Figure 1.10 (b), Cin is charged to Vin through switches S1 and S0 during steady state. During transient recovery, the polarity of Cin is reversed through switches S2 and SR. As a result, the voltage at switching node vx = Vin, which allows rapid drop of inductor current iL.

A buck-derived converter was introduced in [79]. An extra switch S0 is inserted between the ground terminal of the output LC filter and the negative terminal of the input power supply. A power diode D0 is also connected to assist transient recovery. When a heavy-to-light load

L

Coutvout

iloadiL

Vin

MS

SR

S0

S1

(a)

(b)

(c) Figure 1.10 Improving heavy-to-light load transient response using (a) steered inductor topology, (b) three-level buck converter and (c) buck-derived converter.

21

transient occurs, the MS and S0 switches are turned off while the SR switch is turned on. The inductor current, iL will flow from the ground terminal of D0 towards the output node. The voltage at the switching node, vx is clamped to (Vin+VD), where VD is the forward voltage drop of the diode, D0. Therefore the inductor current slew-rate in this topology is k = (Vout+Vin+VD)/L.

The above-mentioned techniques aim at boosting the negative voltage across the power inductor to achieve high current slew-rate while reducing the energy storage requirements of the

output capacitor. However, these topologies have little impact on the light-to-heavy load transient response. More importantly, the conduction loss in steady state is increased due to the

additional switches in series with the main power conduction path.

1.4.4 Converter Augmentation

The augmented buck converter structures, connecting a small auxiliary power stage in

parallel with the main output stage, are introduced in [80]-[97]. The main converter output stage is responsible for steady-state operation. It can be implemented with a large inductor to achieve

optimum steady-state power conversion efficiency. The auxiliary stage examples include additional circuits consisting of power switches and an additional inductor [80]-[89], a transformer [90]-[92], an inductor-capacitor (LC) network [93]-[94], a resistor-capacitor (RC) network [95]-[96], or a pair of linearly controlled active clamps [97] to provide a secondary

Figure 1.11 Improving load transient response through converter augmentation.

22

conduction path with high current slew-rate. It is activated during transient recovery to help inject or remove charge from the output capacitor and suppress transient voltage deviation.

Analog-controlled augmented converter based on a pair of hysteresis comparators have been demonstrated in [80]-[84], [89]-[97]. Digital implementations where the auxiliary stage is controlled as a constant current source [88] or a current source with adaptive slope [85]-[86] were also investigated. These augmented converters achieve significant improvement in transient voltage deviation. However, for frequent transients, the auxiliary circuit usually negatively affects the converter efficiency due to high-frequency switching of the auxiliary switches [87]. Moreover, these auxiliary stages were implemented with discrete components. They took up comparable space on the circuit board as the main converter, which essentially doubles the size of the output stage.

(a)

(b) Figure 1.12 Theoretical waveforms for auxiliary stage controlled as (a) constant current source [88] and (b) current source with adaptive slope [85]-[86].

23

1.4.5 Buck Converter with Stepping Inductor

In [98]-[100], a stepping inductor based on switch and transformer network was applied to a single phase voltage regulator module (VRM). A three-winding transformer replaces the power inductor of a conventional buck converter. In steady state, the buck converter operates using the primary winding of the transformer as the power inductor L. It has large magnetizing inductance and thus results in low current ripple. When a load transient event is detected, the secondary LS or the tertiary winding LT of the transformer is shorted to the input power source to generate a constant voltage across the primary winding. This technique reduces the effective inductance in the buck converter to a much smaller leakage inductance of the transformer, which

allows rapid changes in current flow to suppress voltage over-/undershoot. In the meantime, the constant voltage generated across the primary winding forces the circulating current in the

magnetizing inductor to gradually catch up with the load current. The single phase VRM in [98]-[100] effectively minimizes the transient voltage deviation with a minor increase in the inductance volume and no extra switches added to the main conduction path. However, this previously reported solution is not the most suitable for the targeted low-voltage applications, due to the limitations of the power transistors blocking voltage. In low power applications, the transistors are usually integrated with the controller, and implemented in a cost-effective low voltage CMOS technology. These transistors can only handle a voltage slightly larger than the supply, limiting the ability of the stepping inductor systems to improve heavy-to-light transient

response. During the transients the reflected auxiliary winding voltage reduces the voltage

Figure 1.13 Improving load transient response through using stepping inductor [100].

24

across the leakage inductor [100] to a very low value. As a consequence, the benefit of an improvement in the current slew-rate using the stepping inductor is nullified. An attempt to minimize this problem by increasing the windings turns ratio would significantly increase the blocking voltage requirements for the auxiliary side transistors. The blocking voltage requirement could be several times higher than the supply voltage, preventing cost-effective implementation and possible on-chip integration.

1.5 Thesis Overview

The main goal of this thesis is to explore digital control techniques that allow PoL converters to have fast and smooth load transient response and maintain high overall efficiency. The majority of the research work is presented from a system-level perspective, though the feasibility for fully integrated solutions is also investigated.

The research work in this thesis consists of two parts. In the first part, a voltage-mode controlled buck converter with a small auxiliary output stage to improve load transient response is investigated. The main buck output stage is responsible for steady-state operation. It is designed to achieve high conversion efficiency using large inductor and power transistors with low on-resistance. The auxiliary stage is responsible for transient suppression and is only active

when a load transient occurs. A digital transient suppression circuit is implemented based on the capacitor charge balance principle [24]-[26], aiming at recovering the output voltage and current with only one on-off switching action. A fully integrated dual-output stage is designed and fabricated. Theoretical analysis and experiment show that the auxiliary output stage performs well with inductor and power transistors much smaller than those of the main switching stage.

The dual output stage converter achieves well balanced power conversion efficiency and

dynamic performance with a much smaller area penalty than most previously published augmented converters. However, the auxiliary power stage requires a separate inductor, which results in noticeable increase in the overall inductance size and volume. To mitigate this issue, in

the second part of this research, a flyback transformer based transient suppression method is proposed. The flyback-transformer based buck (FTBB) converter provides a simple, low-cost solution that overcomes current slew-rate limitations of the conventional buck with a low or no penalty in the power processing efficiency and the overall inductance volume. During load

25

transient recovery, the current slew-rate in the power stage is increased with the help of the secondary winding of the flyback transformer and several small auxiliary switches. Peak voltage deviation under both heavy-to-light and light-to-heavy load transients is successfully suppressed. Oscillation between operating modes is avoided through digital control technique. Power loss measurement shows that the proposed structure has slightly higher conduction loss compare to a conventional single stage buck converter under steady-state heavy-load conditions. However, for frequently changing loads, the overall averaged power loss of the proposed converter can be less than or comparable to that of a conventional buck due to the energy recycling ability of the

flyback transformer, that sends energy back to the source during heavy-to-light transients [101]. The proposed converter has a much simpler requirement on the design of the transformer

compare to the stepping inductor [98]-[100] and dual-current pump [90]-[91] approach. The penalty in the overall inductance volume is smaller than in other solutions [80]-[94]. The size of the magnetic core, the largest contributor to the overall magnetic size in the low-power applications [8], is no larger than that of the conventional buck and only a single auxiliary winding handling much smaller average current than the primary is needed. The presented converter does not experience problems of overly large transistor blocking voltages, an undesired characteristic for conventional stepping inductor solutions [98]-[100]. The blocking voltage of the power transistors is no larger than the input voltage Vin. Hence, the presented solution is

better suited for cost-effective integration.

The following 2 chapters deal with the design and implementation of the two buck converter structures introduced above, respectively.

In Chapter 2, the design methodology of the digitally controlled dual output stage DC-DC converter is addressed. Operating principle and design considerations of the digital control unit is described in details. Experimental results obtained on two prototype converters built with

discrete and fully integrated dual output stages, respectively, show about 35% reduction in peak voltage deviation during heavy-to-light load transients, compare to an equivalent conventional

time-optimal controlled [24]-[26] buck converter prototype. Practical limitations of the dual output stage structure are discussed at the end of this chapter, which leads to the introduction of the FTBB converter as a more comprehensive solution.

26

Chapter 3 is devoted to the implementation of the FTBB converter. Design and implementation of the mixed-signal dual-mode controller is presented. The energy recycling mechanism of the FTBB converter is studied. An experimental prototype is built using discrete off-the-shelf components. About 67% reduction in peak voltage deviation during heavy-to-light load transients and 25% reduction during light-to-heavy load transients are demonstrated, in comparison with a conventional minimum-deviation controlled [72][73] buck converter. Under frequent load transients, 7% reduction in averaged power loss is also observed.

Finally in Chapter 4, a summary of this thesis and future research topics are presented.

27

Chapter 2Chapter 2Chapter 2Chapter 2

Digital Digital Digital Digital ControlControlControlControl and Design and Design and Design and Design Strategy Strategy Strategy Strategy ofofofof

aaaa Buck Converter with an Auxiliary Buck Converter with an Auxiliary Buck Converter with an Auxiliary Buck Converter with an Auxiliary

Stage for Transient SuppressionStage for Transient SuppressionStage for Transient SuppressionStage for Transient Suppression

This chapter describes a digitally controlled buck converter with an auxiliary output stage to improve transient performance without jeopardizing steady-state conversion efficiency. The contents are organized as follows: Section 2.1 presents the system structure and briefly introduces the operating principle of the transient suppression method. Section 2.2 is dedicated to the design of the main output stage and the digital voltage mode controller that regulates the

output voltage during steady state. Section 2.3 addresses the design of the transient suppression controller. Architecture and state diagram of the controller will be described in details. Design

considerations such as the selection of auxiliary stage inductor and the size of auxiliary switches will be discussed and demonstrated with simulation results in Section 2.4 and Section 2.5, respectively. The design of two prototype converters using discrete and integrated output stages will be illustrated in Section 2.6. The improvement in transient performance using the proposed structure will be verified with experimental results.

2.1 System Structure and Operating Principle

In order to achieve fast and smooth transient response while maintaining high power

conversion efficiency in steady-state, a digitally controlled buck converter with an auxiliary output stage is investigated. The diagram of the system is as shown in Figure 2.1. It consists of

two output power stages (or dual output stage), an analog-to-digital converter (ADC) that continuously samples the output voltage, vout(t), and a dual-mode digital controller that generates the switching commands for the power switches in the dual output stages.

28

The dual output stages are made up of two conventional buck output stages connected in parallel, each of which has a main switch (MS), a synchronous rectifier (SR), and a filter inductor (L). Subscripts M and A are used to identify the main converter and the auxiliary stage, respectively. The main output stage is responsible for steady-state operation. It is designed to achieve high conversion efficiency, thus large inductor, LM and big power transistors with low

on-resistance are used. The auxiliary stage is responsible for transient suppression. It is only active when a load transient is detected. The auxiliary stage is implemented with a much smaller inductor, LA. During transient recovery, it assists in sinking or sourcing current with a higher

slew-rate than that of the main output stage and quickly brings the output voltage back to its steady-state value.

The digital controller continuously monitors the output of the ADC and determines the operating mode of the system. In steady state, switches MSA and SRA are kept off. The "Steady State Compensator" regulates the output voltage as in a conventional single stage buck converter

Figure 2.1 A digitally controlled DC-DC converter with an auxiliary output stage for fast load transient recovery.

29

[8]. When a load disturbance occurs, the "Transient Suppression Circuit" takes over and activates the auxiliary output stage. Both main and auxiliary output stages switch during transient recovery in order to restore the output voltage, vout(t) and main stage inductor current, iLM(t) to their desired steady-state value.

An example of the theoretical current and voltage waveforms during a heavy-to-light transient recovery process are as illustrated in Figure 2.2. A negative load current step with a

magnitude of iload occurs at time t0. It is assumed that the slew-rate of the load current step is

much higher than that of the inductor currents (k1~k3). It is also assumed that the converter reacts immediately after the load current transient occurs.

The proposed control method involves 3 control parameters: the main stage recovery time (TR), auxiliary stage turn-on time (ton) and turn-off time (toff), which represents the on-time for

k1

k2 k3

0

0

0

t

t

t

ton toff

0vout(t)-VREF

t

vOvershoot

vUndershoot

TR

iload(t)

iLM(t)

iLA(t)

iload

t0

iload

Figure 2.2 Theoretical waveforms of load current iload(t), main stage inductor current iLM(t), auxiliary stage inductor current iLA(t) and output voltage deviation vout(t) VREF under a heavy-to-light load transient.

30

transistors SRM, SRA, and MSA, respectively. In the heavy-to-light load transient recovery process shown in Figure 2.2, the inductor current, iLM(t) in the main output stage ramps down with a slope of k1 during TR, until it reaches the targeted load current. In the mean time, during ton the auxiliary stage inductor draws current, iLA(t) from the output capacitor with a slope of k2, and then ramps back to zero with a slope of k3 through toff. The switching commands for both the main and auxiliary output stages are determined based on the capacitor charge balance principle [24]-[26], such that the amount of capacitor charge dissipated through the auxiliary stage equals to the amount of excess charge injected from the main stage. This method aims at recovering the output voltage to steady state within one on-off switching action. By equating the areas of the two shaded triangles in Figure 2.2, the expressions for calculating these control parameters are

obtained as:

1

loadR

iTk

= , (2.1)

3

2 3 1 2( )on loadk

t ik k k k

= +

, (2.2)

2

2 3 1 3( )off loadk

t ik k k k

= +

, (2.3)

where k1, k2, and k3 are the inductor current slew-rates which are determined by the averaged input voltage, Vin and output voltage, Vout as well as the inductances in the main and auxiliary stages.

1out

M

VkL

= , 2out

A

VkL

= , 3in out

A

V VkL

= (2.4)

Provided that the system is under stable control and the variation of voltages is small when compared to their steady-state values, both Vin and Vout can be treated as constants during the short period of transient recovery. The same assumption also applies to k1, k2, and k3. As can be observed in (2.1)-(2.3), the only unknown parameter that is needed to determine the switching commands is the magnitude of load current step, iload.

31

2.2 Steady State Compensator Design

When the buck converter is in steady state, the auxiliary output stage is turned off while

the main converter switches to maintain output voltage regulation. The main converter is

controlled by a conventional digital voltage mode controller, the structure of which is shown in

Figure 2.3 (a). The design guidelines for the steady-state digital controller have been widely

LM

Cout

vout(t)Vin

MSMSRM

vxM

vout[n]

A/D

VREF[n]

e[n]

Gc(z)DPWMd[n]

Dead-time

c(t)

cMS(t) cSR(t)

Steady State Controller

Digital

Compensator

(a)

GDPWM Gc

d

Gvd GA/D

e

v

Digital

Compensator

DPWM

Module

Buck

Converter

A/D Convertor

and Adder

Steady State Controller

(b) Figure 2.3 (a) Architecture of the digital voltage mode controller for regulating steady-state output voltage, and (b) linearized model of the closed-loop system.

32

investigated in literatures, such as [22], and will be briefly reviewed in this section.

The specifications of the design example are given in TABLE 2.1. The system was

optimized to achieve around 90% conversion efficiency for mid-to-heavy load current range in [102]. The power stage parameters are selected to obtain 0.5A steady-state current ripple and 5mV voltage ripple according to the simulation results in [102].

The linearized small signal model shown in Figure 2.3 (b) is a simplified version of the one in [22], where the output voltage, vout(t) is directly fed-back to the analog-to-digital converter (A/D) instead of going through a voltage divider as in [22]. To design a closed-loop controller with sufficient bandwidth and phase margin, individual transfer functions for the A/D, the digital pulse-width modulation (DPWM) module and the buck converter need to be determined first.

The A/D converts the output voltage, vout(t) into an NA/D-bit signal, vout[n], which is then subtracted by the digital representation of the reference voltage, VREF[n] to generate the error signal, e[n]. According to [22], the combined transfer function of the A/D and the adder can be expressed as

//

1convstA D

A DG e

V

=

, (2.5)

TABLE 2.1. DESIGN PARAMETERS OF THE MAIN CONVERTER

Parameter Symbol Value Input Voltage

Vin 6 V

Nominal Output Voltage

Vout 1 V

Output Accuracy - 1%

Load Current iload 0.1 to 3 A

Output Inductance

LM 2.2 H

Output Capacitance Cout 200 F

Switching Frequency fs 390 kHz MS On-resistance Ron, MS 10 m

SR On-resistance Ron, SR 10 m

Inductor DC resistance RL 20 m

33

where VA/D is the quantization bin of the A/D and tconv is the conversion latency. The effect of

the sample-and-hold function is omitted, since when applied to the closed-loop system, it is already incorporated with the averaged model of the buck converter Gvd [103]. To fulfill the accuracy requirement on the output voltage, VA/D needs to be sufficiently small such that

/ 1%A D REFV V < . (2.6)

For a conventional A/D with quantization range of VA/D, the minimum resolution is thus given by

/ // 2 2

/log ( 1) log ( 1)

1%A D A D

A DA D REF

V VNV V

= + +

. (2.7)

The DPWM module converts an NDPWM-bit digital duty-cycle command, d[n] into a PWM pulse, c(t). Assuming that d[n] is represented by an unsigned binary integer number and that the duty-cycle of signal c(t) ranges between 0 and 1 (e.g. 100%), respectively, the small-signal gain of the DPWM module can be expresses as [41]

12 DPWM

DPWM NK = . (2.8)

To avoid limit-cycle oscillation [104], the change in the output voltage due to one least-significant bit (LSB) change in d[n] must be smaller than the quantization bin of the A/D under all load conditions. As a result, the minimum DPWM resolution can be obtained from [103]

2/

log ( )inDPWMA D

VNV

>

. (2.9)

Since the new duty-cycle command d[n] is usually updated at the beginning of each switching cycle, it does not influence the duty-cycle of c(t) until the output value of the DPWM counter [22] reaches the updated d[n]. Therefore a signal-dependent latency tDPWM is introduced by the DPWM module and can be approximated using the steady-state duty-cycle D [105].

DPWMs

Dt f= . (2.10)

Combining (2.8) and (2.10), the overall transfer function of the DPWM module is given by

34

12

s

DPWM

Ds fDPWM NG e

= . (2.11)

The control-to-output transfer function of the buck converter is given by [8]

2 1 1( ) (1 )

in

M outvd

eq eq

M load out M out load

VL CG R R

s sL R C L C R

=

+ + + +

, (2.12)

where Req is the equivalent series resistance of the converter, which can be approximated as

, ,(1 )eq on MS on SR LR DR D R R= + + . (2.13)

The uncompensated loop transfer function is obtained by multiplying (2.5), (2.11) and (2.12).

/u vd A D DPWMT G G G= (2.14)

Based on the design parameters in TABLE 2.1 and 2.2, the Bode plot of the worst-case uncompensated loop transfer function is generated as shown in Figure 2.4.

As a rule-of-thumb, the frequency response of the loop transfer function needs to have at

least 45 phase margin (m) and a cross-over frequency (fc) at 1/10th to 1/5th of the switching frequency in order to ensure proper performance. Thus loop compensation is usually required. There are multiple approaches to design a digital compensator. The most accurate, but least intuitive method is direct-digital design [106], where the modeling and compensator design are

TABLE 2.2. DESIGN PARAMETERS OF ADC AND DPWM BLOCKS

Parameter Symbol Value A/D Quantization Range VA/D 2 V

A/D Quantization Bin VA/D 7.85 mV A/D Resolution NA/D 8 bits

A/D Conversion Latency tconv 240 ns

DPWM Resolution NDPWM 12 bits

35

carried out in discrete-time domain. An alternative approach, which is applied in this work, is called digital re-design. The compensator is first designed in the continuous-time domain with traditional techniques. Then the coefficients for the digital compensator are obtained using continuous-to-discrete transformation methods such as bilinear transform and pole/zero mapping [22], [107].

A generic compensator is designed for the closed-loop system. It has two real zeros near the corner frequency of the output filter to compensate for the 180 phase shift caused by the quadratic pole in (2.12). It also has an inverting zero so that the closed-loop system has an infinite DC gain to eliminate the DC voltage error. The continuous-time domain transfer function of the compensator is given in (2.15). Parameter Kc is adjusted through simulation to achieve desired loop bandwidth.

1 2(1 ) (1 )ccc

z z

K s sGs

= + + (2.15)

The corresponding discrete-time transfer function of the compensator is as (2.16), where the coefficients a, b, and c are obtained through bilinear transform of (2.15).

Ma

gn

itu

de

(dB

)P

ha

se(d

eg)

Figure 2.4 Bode plot of the uncompensated system.

36

1 2

1( ) 1cda bz czG z

z

+ +=

(2.16)

The digital compensator is then implemented based on the differential equation given by (2.17). The terms ae[n], be[n-1] and ce[n-2] in (2.17) are usually generated using look-up tables (LUTs) [103]. This provides a low-power and fast solution compare to multipliers. A popular structure of the digital compensator is as shown in Figure 2.5.

[ ] [ 1] [ ] [ 1] [ 2]d n d n ae n be n ce n= + + + (2.17)

The compensated loop transfer function using continuous-time domain compensator and

equivalent discontinuous-time domain compensator are obtained as (2.18) and (2.19). Their Bode plots are compared in Figure 2.6 (a) and (b), respectively.

/( ) ( ) ( ) ( ) ( )c vd A D DPWM cc s jT j G s G s G s G s == (2.18)

/,

( ) ( ) ( ) ( ) ( ) jd vd A D DPWM cd s j z eT j G s G s G s G z = == (2.19)

Figure 2.5 Block diagram of the digital PID compensator. clkfs is the steady-state clock signal. It is synchronized with the switching cycle of the converter.

37

As can be observed, the process of digital re-design introduces a loss in accuracy at frequencies close to the switching frequency of the converter, which must be considered when designing the

Frequency (rad/s)

Magnit

ude

(dB

)P

hase

(deg

)

m=65 (at 61kHz)

(a)

Frequency (rad/s)

m=45 (at 48kHz)

(b) Figure 2.6 Bode plots of the compensated system using (a) continuous-time domain compensator and (b) discontinuous-time domain compensator.

38

compensator. It is usually a good practice to design the continuous-time domain compensator for a phase margin higher than 60 to ensure satisfactory performance when the compensator is later on implemented digitally [22].

39

2.3 Controller Implementation

The controller shown in Figure 2.1 is responsible for generating the switching commands

for both the main and auxiliary power stages and ensuring smooth transition between steady state and transient modes of operation.

The block diagram of the controller is as shown in Figure 2.7. It consists of an analog-to-digital converter (A/D) and a digital control unit. The A/D quantizes the output voltage, vout(t) to its digital equivalent, vout[n], at an oversampling frequency 16 times higher than the steady state switching frequency, fsw. The output voltage, vout[n] is processed by the digital control unit, where it is compared with the desired reference, VREF[n] to generate the error signal, e[n]. The digital control unit monitors and regulates the operation of the converter based on the sampled error signal e[n]. The main function blocks of the digital control unit include a steady-state PID

Figure 2.7 Block diagram of the controller.

40

compensator [103], transient detector, transient suppression logic, load step estimator, duty-cycle prediction, clock selector and a switch controller for main and auxiliary switches. Operation of the controller is described by the state diagram as shown in Figure 2.8, and will be elaborated in the following sub-sections.

2.3.1 Steady State Operation