Penn ESE370 Fall 2011 -- Townley & DeHon ESE370: Circuit-Level Modeling, Design, and Optimization...
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Transcript of Penn ESE370 Fall 2011 -- Townley & DeHon ESE370: Circuit-Level Modeling, Design, and Optimization...
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Penn ESE370 Fall 2011 -- Townley & DeHon
ESE370:Circuit-Level
Modeling, Design, and Optimization for Digital Systems
Day 13: October 5, 2011
Layout and Area
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Today
• Layout– Transistors– Gates
• Design rules
• Standard cells
Penn ESE370 Fall 2011 -- Townley & DeHon
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Transistor
Side view
Perspective view
Penn ESE370 Fall 2011 -- Townley & DeHon
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Layout
• Sizing & positioning of transistors
• Designer controls W,L
• tox fixed for process– Sometimes
thick/thin oxide “flavors”
Penn ESE370 Fall 2011 -- Townley & DeHon
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NMOS Geometry
Top view Perspective view
L
W
Penn ESE370 Fall 2011 -- Townley & DeHon
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NMOS Geometry
Top view
L
W
• Color scheme– Red: gate– Green: source and drain
areas (n type diffusion)S DG
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tox
• Transistors built by depositing materials– Constant rate of deposition (nm/min)– Time controls tox
• Oxides across entire chip deposited at same time– Same time interval– thickness is (roughly) constant– Process engineer sets value to:
• Assure yield• What does tox control?
– Field strength Vth, current– Achieve Performance, minimize leakage
Penn ESE370 Fall 2011 -- Townley & DeHon
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NMOS vs PMOS
Rabaey text, Fig 2.1Penn ESE370 Fall 2011 -- Townley & DeHon
• Mostly talked about NMOS so far– PMOS: “opposite” in some sense– NMOS built on p substrate, PMOS built on n
substrate– Name refers to bias/carriers when channel is
inverted
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PMOS Geometry
n well
L
W
• Color scheme– Red: gate– Orange: source and drain
areas (p type)– Green: n well
• NMOS built on p wafer– Must add n material to
build PMOS
S DG
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Body Contact
• “Fourth terminal”• Needed to set
voltage around device– PMOS: Vb = Vdd
– NMOS: Vb = GND
• At right: PMOS (orange) with body contact (dark green)
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Penn ESE370 Fall 2011 -- Townley & DeHon
From: http://www.bioee.ee.columbia.edu/courses/cad/html/layout.html
Rotate All butPMOS Transistor90 degrees
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Interconnect
• How to connect transistors– Different layers of metal Intermediate
layers• “Contact” - metal to transistor• “Via” - metal to metal
Rabaey text, Fig 2.7kPenn ESE370 Fall 2011 -- Townley & DeHon
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Interconnect Cross Section
ITRS 2007Penn ESE370 Fall 2011 -- Townley & DeHon
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Masks
• Define areas want to see in layer– Think of “stencil” for material deposition
• Use photoresist (PR) to form the “stencil”– Expose PR through mask– PR dissolves in exposed area– Material is deposited
• Only “sticks” in area w/ dissolved PR
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Masking Process
• Goal: draw a shape on the substrate– Simplest example: draw a rectangle
Silicon wafer
Mask
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Masking Process
• First: deposit photoresist
photoresist
Mask
Silicon wafer
Penn ESE370 Fall 2011 -- Townley & DeHon
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Masking Process
• Expose through mask– UV light
Penn ESE370 Fall 2011 -- Townley & DeHon
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Masking Process• Remove mask and
develop PR– Exposed area
dissolves– This is “positive
photoresist”
Penn ESE370 Fall 2011 -- Townley & DeHon
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Masking Process• Deposit metal through PR
window– Then dissolve remaining PR
• Why not just use mask?– Masks are expensive– Shine light through mask to
etch PR– Can reuse mask
Penn ESE370 Fall 2011 -- Townley & DeHon
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Logic Gates
• How to build compete inverter?– Connect NMOS,
PMOS using metal
• HW4, part 6: reverse engineer layouts into gates
Penn ESE370 Fall 2011 -- Townley & DeHon
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Inverter Layout Example
Penn ESE370 Fall 2011 -- Townley & DeHon
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Inverter Layout Example
• Start with PMOS, NMOS transistors
• Space for interconnect
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Inverter Layout Example
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Inverter Layout Example
• Add body contacts
• Connect gates of transistors
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Inverter Layout Example
Penn ESE370 Fall 2011 -- Townley & DeHon
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Inverter Layout Example
• Add contacts to source, drain, gate, body
• Connect using metal (blue)
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Design Rules• Why not adjacent
transistors?– Plenty of empty
space– If area is money,
pack in as much as possible
• Recall: processing imprecise– Margin of error for
process variation
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Design Rules• Contract between process engineer &
designer– Minimum width/spacing– Can be (often are) process specific
• Lambda rules: scalable design rules– In terms of = 0.5 Lmin (Ldrawn)– Can migrate designs from similar process– Limited scope: 45nm process != 1m
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Design Rules: Some Examples
Penn ESE370 Fall 2011 -- Townley & DeHon
2
66
3
2
2
1.5
n doping
p doping
gate
contact
metal 1
metal 2
via
Legend
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Layout Revisited
• How to “decode” circuit from layout?
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Penn ESE370 Fall2010 -- DeHon31
Layout to Circuit
• 1. Identify transistors
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Layout to Circuit
• 2. Add wires
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Layout to Circuit
• 2. Add wires
Penn ESE370 Fall 2010 -- Townley (DeHon)Penn ESE370 Fall 2011 -- Townley & DeHon
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Layout to Circuit
• 2. Add wires
Penn ESE370 Fall 2010 -- Townley (DeHon)Penn ESE370 Fall 2011 -- Townley & DeHon
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Layout to Circuit
• 2. Add wires
Penn ESE370 Fall 2010 -- Townley (DeHon)Penn ESE370 Fall 2011 -- Townley & DeHon
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Layout #2 (practice)
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Layout #2 (practice)
• How many transistors?– PMOS?– NMOS?
• How connected?– PMOS, NMOS?
• Inputs connected?• Outputs?• What is it?
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Standard Cells• Lay out gates so that heights match
– Rows of adjacent cells– Standardized sizes
• Motivation: automated place and route– EDA tools convert HDL to layout
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Penn ESE370 Fall 2011 -- Townley & DeHon
Standard Cell Area
inv nand3
All cellsuniformheight
Width ofchanneldeterminedby routing
Cell area
Identify the full custom and standard cell regions on 386DX diehttp://microscope.fsu.edu/chipshots/intel/386dxlarge.html
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Admin
• HW4 due Friday
• Exam next Wednesday– No class at noon that day
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Exam
• Function from CMOS circuit
• CMOS circuit to implement function
• Restoration / Noise Margins– Potentially including MOS equations– Might include variation
• CMOS gate switching delay
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Big Idea
• Layouts are physical realization of circuit– Geometry tradeoff
• Can decrease spacing at the cost of yield• Design rules
• Can go from circuit to layout or layout to circuit by inspection
Penn ESE370 Fall 2011 -- Townley & DeHon