PE_926_manualnew

Sethu institute of technology, Pulloor, Kariapatti PE 926 Power Electronics & Drives Lab

PE926- POWER ELECTRONICS AND DRIVES LAB

CIRCUIT DIAGRAM

Sl.No. LIST OF EXPERIMENTS

1.Micro controller based speed control of Chopper fed DC motor.

2.Micro controller based speed control of VSI fed three-phase induction motor.

3.Micro controller based speed control of Stepper motor.

4.Simulation of logic gates using VHDL and VERILOG HDL Programming

5.Simulation of 4-1 Multiplexer using VHDL and VERILOG HDL Programming

6.Simulation of ADDER using VHDL and VERILOG HDL Programming

7.Simulation of FLIP-FLOP using VHDL and VERILOG HDL Programming

8.Simulation Of Volts/ Hz control of 3-phase Induction Motor

9.Simulation Of Chopper fed speed control of DC Motor

10. Simulation Of Converter fed speed control of DC Motor

1


MODEL GRAPH

EX.NO: 1

Micro controller based speed control of

Chopper fed DC motor.

AIM:

To study the operation of Micro controller based speed control of Chopper

fed DC motor.

2

DUTY CYCLE

SPEED


APPARATUS REQUIRED

SL.NO ITEMS RANGE

1. Micro controller based IGBT Chopper

kit

2. DC Motor ½ HP

3. Patch chords

4. Digital Tachometer

5. RPS 30 V, 2 Amps

CONNECTION PROCEDURE

1. Connections are given as per the circuit diagram.

2. Switch ON the main supply to the controller unit.

3. In the PWM chopper select FWD/REV direction (duty cycle).

4. Now use Increment/ Decrement keys to increase or decrease the duty cycle

from 0 to 100%.

5. After setting duty cycle press RUN\ STOP key. Now the driver output pulses

are available at outputs H1, L1, H2, and L2.

6. Check the driver outputs for forward and reverse direction with regenerative

braking.

7. Connect DC supply from RPS unit and Connect ½ HP DC motor at load

terminals.

FORWARD

MOTORING:

SNO DUTY CYCLE(α) % SPEED (rpm)

3


REVERSE MOTORING

8. Switch ON the DC supply and driver outputs and observe the output voltage

across the load.

9. Check the outputs for forward and reverse direction and also observe the

speed variation as we vary the duty cycle. Also observe the change of

direction of rotation when we change the direction.

SNO DUTY CYCLE(α) % SPEED (rpm)

4


RESULT:

Thus the operation of Micro

controller based speed control of

Chopper fed DC motor was studied

and necessary graphs were plotted.

5


6


EX.NO:2

Micro controller based speed control of VSI fed

Three phase induction motor.

AIM:

To control the speed of the 3 phase induction motor using IGBT power

module(PEC 16HV2A) and digital inverter controller module (PEC16HV2B).

APPARATUS REQUIRED

SL.NO ITEMS RANGE

1. PEC16HV2A Module

2. PEC16HV2B Module

3. 3 phase induction Motor

4. 9 TO 15 Pin D cable

5. Patch chords

6. CRO

7. Isolation Transformer

8. AC Variac 0-230V

CONNECTION PROCEDURE

1. Connect the IGBT power module and controller module to the supply mains

using power chords.

2. Connect 1Ф AC input source to the power module through a variac and

isolation transformer(AC input terminals are provided in the back panel).

3. Connect DC source across the + ive and – ive terminals provided at the

front panel.

4. Interface PWM output from inverter controller to the power module using the

9-15 pin D cable.

5. Connect motor across 3 phase output terminals of the power module.

7

MODULATION INDEX

ACTUAL

SPEED

Sethu institute of technology, Pulloor, Kariapatti PE 926 Power Electronics & Drives Lab6. Connect sensor cable from the motor to the motor feedback input of the

controller.

MODEL GRAPH

CONTROL VOLTAGE=

SNO PWM Toff

(μs)

Ton (μs)

8


EXPERIMENTAL PROCEDURE

1. Switch ON the power ON\OFF switch of the power module and the

controller module.

2. If OC LED glows press reset switch in power module and then the

controller module, now O.C LED gets Off.

3. Switch on the pulse ON\Off switch of controller module.

4. View the test point waveforms through CRO.

5. From the display select INVERTER MODE.

6. Select MULTIPLE PULSE.

7. Select SINE PWM.

8. Select V\F MODE.

9. Select OPEN LOOP\ CLOSED LOOP

OPEN LOOP CONTROL

1. Select OPEN LOOP control.

2. Switch ON AC supply and by using variac set the voltage at 230V.

3. Then using Increment/ Decrement keys set the frequency as well as the

modulation Index.

4. The motor will run in open loop at speed corresponds the set frequency.

5. The actual speed of the motor will be displayed in the LCD.

CLOSED LOOP CONTROL

1. In order to run the motor in closed loop reduce the speed to zero and reset

the module and follow the procedure.

2. If closed loop is selected in step.9 and the display is Kp= 0.10, Ki= 0.02

then set speed and actual speed of sine PWM will be displayed.

9

Sethu institute of technology, Pulloor, Kariapatti PE 926 Power Electronics & Drives Lab3. Set the speed of the motor Increment/ Decrement keys.

OPEN LOOP SYSTEM:

SNO ACTUAL

SPEED(RPM)

SET

FREQUENCY(Hz)

MODULATION

INDEX

CLOSED LOOP SYSTEM

SNO ACTUAL

SPEED(RPM)

SET

FREQUENCY(Hz)

MODULATION

INDEX

10


11


RESULT:

Thus the sine PWM inverter operation was studied using IGBT power

module (PEC 16HV2A) and digital inverter controller module (PEC16HV2B) and

necessary graphs were plotted.

12


EX.NO:3

Micro controller based speed control of Stepper motor.

AIM:

To interface stepper motor with 8051 microcontroller and control its speed.

APPARATUS REQUIRED

SL.NO ITEMS RANGE

1. MICROCONTROLLER 8051

2. STEPPER MOTOR

ALGORITHM

1. Initialize the data for the motor rotation.

2. Output the data.

3. Initialize the delay for rotation.

4. Decrement the count.

13

Sethu institute of technology, Pulloor, Kariapatti PE 926 Power Electronics & Drives Lab5. Go to the starting address so that the program does not get terminated.

14


PROGRAM

LABE

L

ADDRE

SSMNEMONICS OP CODE COMMENTS

8200MOV DPTR, #0A003H 90 CONTROL WORD REGISTER

8201A0

820203

8203MOV A,#82 74 SET PORT A OUTPUT & PORT-B

INPUT8204

82

8205

MOVX @ DPTR, A F0 MOVE CONTENT OF

ACCUMULATOR TO DPTR

8206MOV DPTR, #0A000H 90 SET PORT-A

8207A0

820800

8209MOV A,#90H 74 MOVE 09H TO ACCUMULATOR

820A09

820B

MOVX @ DPTR, A F0 MOVE ACCUMULATOR CONTENT

TO DPTR

820C ACALL DELAY 51 CALL DELAY

15


820D1F

820EMOV A,#05H 74 MOVE 05H TO ACCUMULATOR

820F05

8210

MOVX @ DPTR, A F0 MOVE CONTENT OF

ACCUMULATOR TO DPTR

8211ACALL DELAY 51 CALL DELAY

82121F

8213MOV A,#06H 74 MOVE 06H TO ACCUMULATOR

821406

8215


TO DPTR

8216ACALL DELAY 51 CALL DELAY

16


82171F

8218MOV A,#0AH 74 MOVE 0AH TO ACCUMULATOR

82190A

821A


TO DPTR

821BACALL DELAY 51 CALL DELAY

821C1F

821DSJMP L1 80 SHORT JUMP TO 8209

821EEA

DELAY821F

MOV R1, #10H 79 MOVE 10H TO R1 REGISTER

822010

L38221

MOV R0, #FFH 78 MOVE FFH TO R0 REGISTER

8222FF

L2 8223 DJNZ R0,L2 D8 DECREMENT AND JUMP ON NO

17

Sethu institute of technology, Pulloor, Kariapatti PE 926 Power Electronics & Drives LabZERO TO L2

8224FE

8225DJNZ R0,L3 D9 DECREMENT AND JUMP ON NO

ZERO TO L38226

FA

8227RET 22 RETURN TO CALLING FUNCTION

FULL STEP SEQUENCE

STEP SW1 SW2 SW3 SW41 OFF ON OFF ON2 OFF ON ON OFF3 ON OFF ON OFF4 ON OFF OFF ON1 OFF ON OFF ON

RESULT

Thus the stepper motor is interfaced with 8051

microcontroller and it is run in full step sequence.

AND GATE (7408) TRUTH TABLE

OR GATE (7432): TRUTH TABLE

NAND (= NOT AND) GATE (7400) TRUTH TABLE

A B OUT0 0 00 1 01 0 01 1 1

A B OUT0 0 00 1 11 0 11 1 1

18


NOR GATE (7402) TRUTH TABLE

XNOR (EXCLUSIVE NOR) TRUTH TABLE

EX.NO: 4

Simulation of logical gates using VHDL and Verilog

Programming

OBJECTIVE:

1.To simulate logical gates using xilinx.

REQUIREMENT

A B OUT0 0 10 1 11 0 11 1 0

A B OUT0 0 10 1 01 0 01 1 0

A B OUT0 0 10 1 01 0 01 1 1

19


1. Verilog HDL and VHDL software with both front-end and backend (Design entry, simulation) and programming.

PROCEDURE

1. Click on the Project navigator icon on the desktop of your PC. Write the verilog HDL code, check syntax, and perform the functional simulation using Xilinx ISE Simulator 2. Create programming file.3. Verify the result.

PROGRAM (VERILOG)module vl2(c,d,e,g,h,a,b);input a,b;output c,d,e,g,h;and a1(c,a,b);or a2(d,a,b);nand a3(e,a,b);nor a4(g,a,b);xnor a5(h,a,b);endmodule

PROGRAM (VHDL)

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

SIMULATION RESULTS:

VHDL:

20


VERILOG:

---- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;

21


entity logu1 isport ( a,b : in STD_LOGIC; c,d,e,g,h : out STD_LOGIC);end logu1;

architecture Behavioral of logu1 is

beginc<= a and b;d<= a or b;e<= a nand b;g<= a nor b;h<= a xnor b;end Behavioral;

RESULT:

Thus the logic gates are simulated using Xilinx and results were verified.

22


4 to 1 line Multiplexer

1 to 4 line De-Multiplexer

A B X0 0 X00 1 X11 0 X21 1 X3

A B OUT0 OUT1 OUT2 OUT30 0 IN 0 0 00 1 0 IN 0 01 0 0 0 IN 01 1 0 0 0 IN

23


EX.NO:5

Simulation of multiplexer and demultiplexer using

Verilog HDL Programming

OBJECTIVE:

1.To simulate 4-1 multiplexer and demultiplexer using xilinx

REQUIREMENT

1. Verilog HDL software with both front-end and backend (Designentry, simulation) and programming.

PROCEDURE


PROGRAM

4-1 MULTIPLEXER

module mux(y,d0,d1,d2,d3,s0,s1);input d0,d1,d2,d3,s0,s1;output y;reg y;always @ (d0 or d1 or d2 or d3 or s0 or s1)beginif( s0==0 && s1==0)y=d0;else if(s0==0 && s1==1)y=d1;else if( s0==1 && s1==0)y=d2;else y=d3;endendmodule

1-4 DEMULTIPLEXER

module demux1(y0,y1,y2,y3,d,s0,s1);input d,s0,s1;

24

Sethu institute of technology, Pulloor, Kariapatti PE 926 Power Electronics & Drives Laboutput y0,y1,y2,y3;

SIMULATION RESULTS:

4-1 MULTIPLEXER

1-4 DEMULTIPLEXER

25


reg y0,y1,y2,y3;always @ (d or s0 or s1 )beginif( s0==0 && s1==0)y0=d;else if (s0==0 && s1==1)y1=d;else if ( s0==1 && s1==0)y2=d;elsey3=d;endendmodule

RESULT:

Thus the multiplexer and demultiplexer are simulated using Xilinx and results were verified.

26


D-FLIP FLOP

Clock InputD

OutputQ

clk X No change

clk 0 0clk 1 1

JK FLIP FLOP:

J

K

Q __ Q

Operation

27


0 0 No Change No Change Hold (no change)

0 1 0 1 Reset

1 0 1 0 Set

1 1 1 Toggle Toggle

EX.NO:6

Simulation of FLIPFLOP using Verilog HDL

Programming

OBJECTIVE:

To simulate J-K,D- FlipFlop using xilinx

REQUIREMENT

1. Verilog HDL software with both front-end and backend (Designentry, simulation) and programming.

PROCEDURE


PROGRAM

JK FLIP FLOP

module dwd(clk,rst,j,k,q,qb); input clk,rst,j,k; output q,qb;reg q,qb;always @ (posedge(clk)or posedge(rst))if(rst==1)beginq=0;qb=1;endelse if(j==0&&k==0)

28


beginq=q; qb=qb;endelse if(j==0&&k==1)beginq=0;

SIMULATION RESULTS:

JK FLIP FLOP

D FLIP FLOP

29


qb=1;endelse if(j==1&&k==0)beginq=1;qb=0;endelsebeginq=qb;qb=q;endendmodule

D FLIP FLOP

module sdgg(clk,rst,din, dout); input clk,rst,din; output dout;reg dout;always @ (posedge(clk)or posedge(rst))if(rst==1)dout=0;elsedout=din;endmodule

RESULT:

Thus the JK Flip Flop and D Flip Flop were simulated using Xilinx and results were verified.

30

12 3

U 1 A

7 4 8 6

45 6

U 1 B

7 4 8 6

1

23

U 2 A

7 4 0 84

56

U 2 B

7 4 0 89

1 08

U 2 C

7 4 0 8

128

9

U 3 A

1 4 0 7 5

Sum

FULL ADDER

Carry

Cin

Y

X


HALF ADDER:

TRUTH TABLE:

X Y SUM CARRY0 0 0 00 1 1 01 0 1 01 1 0 1

X Y CIN SUM COUT

0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1

31


EX.NO:7 Simulation of ADDER using VHDL and Verilog

HDL Programming

OBJECTIVE:

To simulate ADDER using xilinxREQUIREMENT

1. Verilog HDL AND VHDL software with both front-end and backend (Design entry, simulation) and programming.

PROCEDURE


PROGRAM

VERILOG HDL

Full Adder:

module Fulladd(a,b,cin,s,cout); input a,b,cin; output s,cout;wire s1,t1,t2,t3;xorx1(s1,a,b),x2(s,s1,cin);anda1(t3,a,b),a2(t2,b,cin),a3(t1,a,cin);or b1(cout,t1,t2,t3); endmodule

HALF ADDER:

module Halfadd(a,b,s,c); input a,b; output s,c;

32

Sethu institute of technology, Pulloor, Kariapatti PE 926 Power Electronics & Drives Labxor x1(s,a,b);and a1(c,a,b);endmodule

SIMULATION RESULTS:

FULL ADDER:

HALF ADDER:

33


VHDL

FULL ADDER:

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity fff1 isport(a,b,cin: in std_logic; s,cout: out std_logic);end fff1;architecture Behavioral of fff1 isbegins<= a xor b xor cin;cout<= (a and b) or(b and cin) or (cin and a);end Behavioral;

HALF ADDER:

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity hf1 is port( a,b:in std_logic;

s,c:out std_logic);end hf1;architecture Behavioral of hf1 isbegins<= a xor b;c<= a and b;end Behavioral;

RESULT:

Thus the ADDER circuit was simulated using VHDL and Verilog HDL Programming and the results were verified.

34


SIMULATION OF CLOSED LOOP VOLTS/ HZ CONTROL OF 3-PHASE INDUCTION MOTOR

35


EX.NO: 8 Simulation Of Closed loop Volts/ Hz control of 3-

phase Induction Motor

OBJECTIVE:

To simulate closed loop Volts/ Hz control of 3-phase Induction Motor using MATLAB.

KNOWLEDGE REQUIRED

1. Operation of inverter fed Induction motor and its torque speed relationship.

2. MATLAB Software.

36


37


38


RESULT:

Thus the closed loop Volts/ Hz control of 3-phase Induction Motor was simulated using MATLAB and the results were verified.

SIMULATION OF CLOSED LOOP SPEED CONTROL OF

CHOPPER FED DC MOTOR

39


40


EX.NO: 9 Simulation Of Closed loop Speed control Of

Chopper Fed DC Motor

OBJECTIVE:

41


To simulate closed loop speed control of Chopper Fed DC Motor using MATLAB.

KNOWLEDGE REQUIRED

1. Operation of chopper fed DC motor and its torque speed relationship.

2. MATLAB Software.

SIMULATION RESULTS:

SPEED OUTPUT, TORQUE OUTPUT, ARMATURE CURRENT,

42


FIELD CURRENT

43


RESULT:

Thus the closed loop speed control of Chopper Fed DC Motor was simulated using MATLAB and the results were verified.

44


SIMULATION OF CONVERTER FED SPEED CONTROL OF DC

MOTOR

45


EX.NO: 10 Simulation Of Closed loop Speed control of

Converter Fed DC Motor

OBJECTIVE:

To simulate closed loop speed control of Convereter Fed DC Motor using MATLAB.

KNOWLEDGE REQUIRED

1. Operation of converter fed DC motor and its torque speed relationship.

2. MATLAB Software.

46


SIMULATION RESULTS:

47


RESULT:

Thus the closed loop speed control of Converter Fed DC Motor was simulated using MATLAB and the results were verified.

48

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