P.Considine/P.Carbou Nov 2006 1 Switched Capacitor Filters.

P.Considine/P.Carbou Nov 20061

Switched CapacitorFilters


PlanLecture1:• Integration Techniques• Switched capacitor theory• Parasitic effects in switched capacitor integrators

Lecture2:• Switched capacitor noise• Continuous time domain to sampled domain

mapping• Synthesis methods


Pole Requirements for stable systems

S-Plane

jw

jb

a

Z-Plane

For a stable continuous-time systemAll poles, si must be in LHP ( i <= 0)Transfer Function cannot have poles withpositive real parts

For a stable sampled systemAll poles, Zi must obey | Zi | < 1

Laplace Transform: F(s) = f(t) est dt

0

From Inverse Laplace Transform all poles, si = i+ jwi of form 1/(s- i) , 1/((s – i) 2+bi 2),etc contain factor: e iT for i >=0

Z-Transform: F(z) = f(nT) z -n where z = esT

n=0

From Inverse Z-Transform all poles, Zi = ai + jbi of form 1/(Z-aT) , 1/(Z – aT) 2, contain factor: anT = | Zi | n in the transient response for | Zi |>1

Objective: Map a Continuous-Time (C.T.) domain (analog) filter transfer function(T.F.), Ha(Sa) to a Discrete-Time(D.T) domain transfer function, H(z) by replacing Sa by some function Sa = f(z)

Ha(Sa) H(z) with Sa = f(z)Question: What are requirements of f(z) to be a “good” mapping?


Requirements for “good” mapping function f(z)

Ha(Sa) H(z)

with Sa = f(z)

e.g., Continuous Time Integrator Ha(sa) = 1/sRC

Requirements for f(z):1) f(z) is a rational function of z,

i.e.,a division of two polynomial functions 2) For s = jw, |Z|=1 must be true3) For Re(s) < 0, |Z|<1 must be true


Integration Techniques1 (Forward Euler Example)For a C.T.filter with T.F. =Ha(Sa), it’s response can be determined from it’s state equations, a system of 1st order equations which describe it.

NiSGSXS

Nitgdt

tdx

aiaia

ii

,...2,1)()(

LaplaceUsing

,...2,1)()(

T

ZZfS

suggestsaboveEqwiththisComparing

a

1)(

:2.

nT-T nT

Forward Euler

gi(t)

…Eq.1

…Eq.2

)()(1

)()(1

)()()(

:Transform-Ztimediscrete Using

)()()(

)()(

1

1

11

ZGZXT

Z

ZGZXTZ

Z

ZGTZZXZZX

TnTTgTnTxnTx

TnTTgdttg

ii

ii

iii

i

i

nT

TnT

i

Now Eq.1 has been transformed into difference form.

Numerical Integration can be used to evaluate this integral: e.g., for the Forward Euler approximation

dttgTnTxnTx

dttgdtdt

tdx

nT

TnT

i

nT

TnT

i

nT

TnT

i

)()()(

)()(

Now derive the state equations for sampled data systems:

Integrating Eq.1 over the nth sampling period:

Where: xi are the state variables of the filtergi (t) are linear functions of xi (t) and the input signalAnd we assume xi (t) = 0 for t <= 0


Integration Techniques2

nT-T nT

a) Forward Euler

xi(nT) - xi(nT-T) = Xi(z) – z –1 Xi(z)= Solve for f(z)= Gi(z)/Xi(z)

Tgi(nT-T) T.z –1 .Gi(z)

Tgi(nT) T.Gi(z)

(T/2)(gi(nT-T) + gi(nT)) (T/2)(z –1 .Gi(z)+ Gi(z))

(Not used because unstable in Z-domain)

nT nT

gi(t)dt = dxi(t)/dt.dt = xi(nT) - xi(nT-T)nT-T nT-T

f(z). Xi(z) = Gi(z) for some function f(z)

1)( 1 ZZf T

gi(t)

b) Backward Euler

nT-T nT

Z

ZZf T

1)( 1

nT-T nT

c) Trapezoidal/ Bilinear

1

1)( 2

Z

ZZf T

nT-T nT

d) Mid-point

Z

ZZf T

1)(

2

21

In the same way, different numerical Integration techniques will give different approximations of gi(t)dt and each will yield a different function f(Z) for transforming from Continuous-time to Discrete-Time domains.

Integration Technique:


Integration Techniques3

H(j a )

H(ejwT)

H(ejwT)

Continuous-TimeFilter

Sampled-TimeFilter (Forward Euler)

Sampled-TimeFilter (Backward Euler)

Dominant poles (I.e., closest to j axis in s-plane)move towards |Z|=1. (To see this let a0)=> Results in peaking in passband

In Forward Euler Zero’s on jw axis are not mapped onto |Z|=1. So no zero’s in Discrete-Time T.F.=> Deteriorated stopband response

In Backward Euler, dominant poles move away from |Z|=1=> Results in rounding in passband

In Backward Euler, Zero’s on jw axis not mapped to |Z|=1=> Deteriorated stopband response

Check Mapping properties of f(z) vs Requirementse.g., For Forward Euler Mapping:1) F(Z) is a Rational Function of Z? Yes.2) Let sa = ja => ja = (Z-1)/T => z = ja T + 1 But |z| = 1 only at a = 0 |z| ~= 1 at a T << 1, I.e., when fs = 1/T >> a

jb

a

Z-Plane

Image of j axis

1

1)( 1 ZZf T

From how F(Z) functions map poles and zeros from C.T. to D.T. domains we can see:


Switched Capacitor Theory

• Resistor & equivalent switched capacitor.• Interest of switched capacitors in IC.• Basic structures of switched capacitor integrators.• Comparison with continuous time integrator.


Principle(Parallel mode)

RVA VB

C

1 2

VBVA

1

2

Tc

sRC

BAR

TITQR

VVI

)(

)(

s

sEQ

EQ

BA

s

BA

s

TCEQ

BATC

BC

AC

FCC

TRWhere

R

VV

T

CVV

T

QI

CVVQ

VCQ

VCQ

C

C

1:

)()(

)(

)(

)(

)2(

)1(


Principle(Serial mode)

RVA VB

1

2

VBVA

1

2

Tc

sRC

BAR

TITQR

VVI

)(

)(

s

sEQ

EQ

BA

s

BA

s

TCEQ

BATC

BAC

C

FCC

TRWhere

R

VV

T

CVV

T

QI

CVVQ

VVCQ

Q

C

C

1:

)()(

)(

(

0

)(

)(

))2(

)1(C


Interest of switched capacitors• Pole accuracy:

– Tolerance on integrated resistor (σR) 20% to 30%

– Tolerance on integrated capacitor (σC) 10% to 20%

Accuracy on RC poles around 50%

(Or more likely σRC = (σR2+σC

2)0.5 = 0.36 )– Tolerance on integrated capacitor matching 0.1%– Tolerance on clock frequency few ppm

– Accuracy on SC poles better than 1%

• Components size– High resistance value : PREVIOUSLY BIG RESISTOR

SMALL (Switched) CAPACITOR


Continuous Time Integrator

4/Continuous Time Integrator

VIN -

+

CI

VOUT

+-

R

aaain

aoutaa SS

CR

SV

SVSH 021

1

)(

)()(

aIINOUT SCR

VV

1

j

VV INOUT

Transfer function:


Switched Capacitor Integration Techniques

1)( 1 ZZf T

1

1)( 2

Z

ZZf T

Correspondance Table Summary

Parallel Switched-Capacitor Integrator Forward Euler Mapping

Serial Switched-Capacitor Integrator Backward Euler Mapping

Serial/Parallel Switched-Capacitor Integrator Bilinear Mapping

Z

ZZf T

1)( 1

We will establish on the following pages:


Switched Capacitor Integrator1/ Parallel Integrator

-

+CU

1 2

CI

VOUT

VIN

+

+

-

-

1

2

1Z2/1

Z 0Z

E l e m e n t I n i t i a l C h a r g e F i n a l C h a r g e P o l a r i t y D e l t a C h a r g e

UC 2/1 ZVC INU0 + )0( 2/1 ZVC INU

IC 1 ZVC OUTI OUTI VC - ))1(( 1 ZVC OUTI

C h a r g e r e d i s t r i b u t i o n e q u a t i o n s 0)1( 12/1 ZVCZVC OUTIINU

T r a n s f e r f u m c t i o n1

2/1

1

Z

Z

C

CVV

I

UINOUT

A s s u m i n g INV c o n s t a n t d u r i n g o n e

C l o c k p e r i o d 12/1 ZVZV ININ1

1

1

Z

Z

C

CVV

I

UINOUT

VIN

Sampling Instant

s

IEQI

U

sI

U

INOUT

s

sI

UINOUT

s

s

I

UINOUT

T

Zsand

CRCCTsTC

CWhere

sVV

Z

T

TC

CVV

T

T

ZC

CVV

1

11

1

1

1

0

0

a) Calculate Transfer Function: b) Relate S.D. T.F. to Integration model:

This is equivalent to Forward Euler integration

X

Final-InitialFor (Q)=0 at node X At +Node of

Capacitors


Switched Capacitor Integrator2/ Serial Integrator

-

+

1

2

CI

VOUT

VIN+

+

-

-1

2

1Z2/1

Z 0Z

Elem ent Initial C harge Final C harge Polarity D elta C harge

UC 0 INU VC - )0( INU VC


C harge redistribution equations 0)1( 1 ZVCVC OUTIINU

Transfer fum ction11

1

ZC

CVV

I

UINOUT

CU

VIN

Sampling Instant

lerBackwardEuT

ZsAnd

TC

CWhere

sVV

Z

T

TC

CVV

T

T

ZC

CVV

s

sI

U

INOUT

s

sI

UINOUT

s

s

I

UINOUT

1

0

0

1

1

1

1

1

1

a) Calculate Transfer Function:b) Relate C.T. T.F. to Integration model:

Equivalent to Backward Euler Integration


Capacitors

X


Switched Capacitor Integrator3/ Parallel/Serial Integrator

VIN

E le m e n t In i t ia l C h a r g e F in a l C h a r g e P o la r i t y D e l ta C h a r g e

1UC 0 INU VC 1 - )0( 1 INU VC

2UC 12

ZVC INU 0 + )0( 12

ZVC INU


C h a rg e r e d is t r ib u t io n e q u a t io n s 0)1( 11

21 ZVCZVCVC OUTIINUINU

T r a n s f e r f u m c t io n A s s u m in g UUU CCC 21 1

1

1

1

Z

Z

C

CVV

I

UINOUT

-

+

1

2

CI

VOUT

+

+

-

-CU1

CU2 -

+

1

2

1Z2/1

Z 0Z

VIN

Sampling Instant

1

12

1

2

12

21

1

1

1

0

0

1

1

Z

Z

TsAnd

RCC

CTTC

C

wheres

VV

T

Z

Z

TC

CVV

T

T

Z

Z

C

CVV

s

II

U

ssI

U

INOUT

s

sI

UINOUT

s

s

I

UINOUT

Equivalent to Bilinear Integration

a) Calculate Transfer Function:

b) Relate C.T. T.F. to Integration model:


Capacitors

X

2 +-

Notice: For same RC pole Cu1=Cu2=Cu/2 of previous serial or parallel integrators


Comparison of parallel and C.T. Integrators

j

Tsj

INOUT

jj

Tsj

INOUT

sI

U

jj

Tsj

TsjTswjI

UINOUT

TsjI

UINOUT

Tsj

I

UIN

I

UINOUT

eR

eTs

Sin

Ts

VV

jjSinCoseandjj

ceej

But

eTs

Sin

Ts

jVV

TC

CLet

eee

C

CVV

eC

CVV

eZLet

ZC

CV

Z

Z

C

CVV

.

.)

2*

(

2*

**

)2

()2

(1

sin1

*)

2*

(

2*

**

*

1**

1

1**

1

1**

1**

22

*

0

22

2

*0

*2**2

2

*

2

*

2

**

**

**

1

1

-15

-10

-5

0

5

10

15

20

25

30

35

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

Gai

n(dB

)

RC integrator Parallel SC integrator

-100

-95

-90

-85

-80

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

Phas

e(de

g)

FrequencySample Domain Frequency,w (normalised to w0)


j

Tsj

IN

Tsj

INOUT

sI

U

jj

Tsj

TsjTswj

Tswj

I

UINOUT

Tsj

Tsj

I

UINOUT

Tsj

I

UIN

I

UINOUT

eR

eTs

Sin

Ts

V

eTs

Sin

Ts

jVV

TC

CLet

eee

e

C

CVV

e

e

C

CVV

eZLet

Z

Z

C

CV

ZC

CVV

.

*)

2*

(

2*

**

*)

2*

(

2*

**

*

)(

**

1**

1**

1

1**

22

*

0

2

*0

*2**2

2

*

2

*

2

**

**

**

**

**

1

-15

-10

-5

0

5

10

15

20

25

30

35

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

Gai

n(dB

)

RC integrator Serial SC integrator

-100

-95

-90

-85

-80

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

Phas

e(de

g)

Frequency

Comparison of serial and C.T. Integrators


Comparison with parallel/serial integrator

)(**2

1

1**2*

1

1**2

*

2

2111

2

2

1

1*

*

**

1

1**

1

1**

**

**

**

1

1

ss

Tsj

Tsj

s

Tsj

s

INOUT

I

Us

s

IN

s

s

sI

sUINOUT

I

UIN

I

UINOUT

F

FTanF

e

eFj

eZLet

Z

ZFjs

sVV

C

CF

FZZ

V

F

F

Z

Z

FC

FCVV

Z

Z

C

CV

Z

Z

C

CVV

-15

-10

-5

0

5

10

15

20

25

30

35

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

Gai

n(dB

)

RC integrator Parallel/Serial SC integrator

-100

-95

-90

-85

-80

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

Phas

e(de

g)

Frequency

i.e.,BILINEAR

TRANSFORM1

121

12

2

:

Z

Z

T

Z

ZFs

C

CF

Where

s

s

I

Us


Parasitic effects in SC integrators

• Clock overlap• Parasitic capacitors• Switch resistance• Clock feed through• Charge injection• Mismatch


Need of non overlapping clocks

VOUT

VIN -

+CU

2

CI

+

+

-

-1

CI

CI

VOUT

VOUT

-

+CU

1

+

+

-

-2

VIN

-

+CU

+

+

-

-21

VIN1

2

1Z2/1

Z 0Z

VIN

Sampling Instant


Non overlapping clocks generator

D1

D2

D1

D2

D2

D1

CKCK1N

CK1P

CK2N

CK2P

CK1P

CK1N

CK2N

CK2P

CK


Parasitic Capacitors (Parallel Integrator)


UC 2/1 ZVC INU 0 + )0( 2/1 ZVC INU


C p 1 2/11

ZVC INP 0 + )0( 2/11

ZVC INP

C p 2 0 0 + 0

C h a r g e r e d i s t r i b u t i o n e q u a t i o n s 0)1()( 12/11 ZVCZVCC OUTIINPU

T r a n s f e r f u m c t i o n

1

2/11

1

)(

Z

Z

C

CCVV

I

PUINOUT

A s s u m i n g INV c o n s t a n t d u r i n g o n e

C l o c k p e r i o d 12/1 ZVZV ININ 1

11

1

)(

Z

Z

C

CCVV

I

PUINOUT

1

2

1Z2/1

Z 0Z

VIN

Sampling Instant

-

+CU

1 2

CI

VOUT

VIN

+

+

-

-

Cp2Cp1

THIS TYPE OF INTEGRATOR IS SENSITIVE TO PARASITIC CAPACITORS ( INTERCONNECT, JUNCTIONS)

POLE ACCURACY IS NO LONGER TRUE

X


Structure insensitive to parasitic capacitor (Equivalent Parallel Integrator)


UC 1* ZVC INU 0 - )*0( 1 ZVC INU


C p 1 1

1 * ZVC INP 0 + tionredistribuNo

C p 2 0 0 + 0

C h a r g e r e d i s t r i b u t i o n e q u a t i o n s 0)1(* 11 ZVCZVC OUTIINU

T r a n s f e r f u m c t i o n 1

1

1

Z

Z

C

CVV

I

UINOUT

1

2

1Z2/1

Z 0Z

VIN

Sampling Instant

VOUT

VIN

NON-INVERTING INTEGRATOR

SAME TRANSFER FUNCTION AS PARALLEL INTEGRATOR

EXCEPT THE SIGN

POLE ACCURACY IS RECOVERED

-

+

1 2

CI

+-

Cp2Cp1

Cu

12

++

+ X


Structure insensitive to parasitic capacitor (Equivalent Serial Integrator)


UC 0 INU VC - )0( INU VC


C p 1 0 INP VC 1 + tionredistribuNo

C p 2 0 0 + 0

C h a r g e r e d i s t r i b u t i o n e q u a t i o n s 0)1( 1 ZVCVC OUTIINU

T r a n s f e r f u m c t i o n 11

1

ZC

CVV

I

UINOUT

1

2

1Z2/1

Z 0Z

VIN

Sampling Instant

VOUT

VIN

INVERTING INTEGRATOR

SAME TRANSFER FUNCTION AS SERIAL INTEGRATOR

POLE ACCURACY IS RECOVERED

-

+

2 2

CI

+-

Cp2Cp1

Cu

11

++

+ X


Switch resistance

CRON

)C*Ln(

T

R

LnCR

T

LnCR

T

ehaveMust

eVV

S

ON

ON

S

ON

S

CRON

Ts

CRON

Ts

INC

maxerr2

maxerr)(*2

maxerr)(*2

allowablemaxerr:

)1(*

*2

*2

VIN

1

2

1Z2/1

Z 0Z

Ts

SPS

P

S

ONP

ONS

FFF

F

FerrLn

CRF

CRFerrLn

29.6 1000

1maxerr IF

2

2)(max

2

1

12)(max

After charging C for one (non-overlap) clock phase:

i.e., RON.C pole frequency must be more than twice the sampling frequency for capacitor charging error of <0.1%:


Clock Feed-Through

VIN

C

CgsCgd

VG

VC

SWITCH ON

ONG

INC

VV

VV

VG

ICgs

TRANSITION ON ->OFF

)(*

*)(*

**

0

***

*)()(

**

GS

GSGC

GGSGS

C

CGGS

C

LOADGCGSC

COUTINC

CGGS

OUTOFFINONGSGSCGS

CC

CVV

dT

VCCC

dT

VdT

VVC

dT

VC

IIifIIButdT

VC

dT

VVC

dT

dVCI

dT

VVC

dT

VVVVC

dT

dVCI

SWITCH OFF

OFFG

OUTC

VV

VV

CLOCK FEED-THROUGH INDUCES DC OFFSET BUT NO NON-LINEARITY

because no dependency on VIN

)()( OUTINOFFON

CGGS

OUTINC

OFFONG

VVVV

VVV

VVV

VVV


Clock Feed-Throughcompensation methods (1)

VG1

ICgs1

VIN

C

Cgs1Cgd1

VG1

VC

Cgs2Cgd2

VG2

W W/2

VG2

ICgd2

ICgs2 SINGLE TYPE OF

SWITCH

NMOS OR PMOS

DUMMY SWITCH

dt

dV

dt

dV GG 21 TRUE IF AND 221 GDGSGS CCC


Clock Feed-Throughcompensation methods (2)

VGn

VIN

C

VC

CgsnCgdn

VGn

CgspCgdp

VGp

VGp

ICgsn

ICgsp

COMPLEMENTARY SWITCHES

NMOS AND PMOS

dt

dV

dt

dV GpGn TRUE IF AND GSPGSN CC


Charge Injection

-- --- - - -C

-

-

-

--

---

C

SWITCH ON

SWITCH OFF

Pwell

N+ N+

Vg=+V

Vg=0

• When Vg=+V is applied, P-type acceptor Holes are repelled from surface• Negative acceptor atom space charge left in depletion layer• As Vg increases, an inversion layer of electrons forms at surface This negative charge is redistributed when Vg0

Pwell

N+


Charge Injection

VIN

C

VG

VC

SWITCH ON

)f(VC IND

IND

INC

VV

VV

TRANSITION ON ->OFF

IND

IN

COUT

IND

IN

INDIN

CDCC

INC

INININDCD

VC

CV

C

QVBut

VC

CVC

VCCV

QQQOFFSwitch

VCQONSwitch

VfVVCQ

*

)*(

*

:

*:

)(*

'

'

SWITCH OFF

0

D

OUTC

C

VV

CHARGE INJECTION INDUCES NON-LINEARITY because charge injection has a dependency on VIN

D

1-

DEPENDS ON THE IMPEDANCES SEEN

AT VIN AND VC TERMINALS


Charge Injectioncompensation method

2Cu

2D

1D

1

2Cu

2D

1D

1

2Cu

2D

1D

1

2Cu

2D

1D

1

Cu

1

1D

2D

2 Cu

1

1D

2D

2

SAMPLING

CHARGE INJECTIONHIZ AT Cu

SIDECLOCK NON-

OVERLAP

RE-DISTRIBUTIONCHARGE INJECTION SAMPLING

Towards low-impedance

input

Don’t care


Mismatch

5

5

5

5

5

5

25

25

C1

C2

C1

C2

%3

82.259.4*9.4

9.24*9.24

1

2

1.0

255*5

25*25

1

2

ErrorC

C

C

C

%0

259.4*9.4

9.4*9.4*25

1

2

1.0

255*5

25*25

1

2

ErrorC

C

C

C


Noise in SC integrators

• Low pass filtering• Sampling• Aliasing• Holding


SAMPLING & HOLD LOW-PASS FILTERED WHITE NOISE

PSD WHITE NOISE

PSD AFTER HOLD

PSD AFTER

LPF

LPF SAMPLE HOLD

WHITE NOISE fc

PSD AFTER SAMPLING

CRON

-20

-15

-10

-5

0

5

10

-4 -2 0 2 4

Ga

in(d

B)

Frequency

-20

-15

-10

-5

0

5

10

-4 -2 0 2 4

Ga

in(d

B)

Frequency

10*log10(s(x)*sinc(x)**2)

-20

-15

-10

-5

0

5

10

-4 -2 0 2 4

Ga

in(d

B)

Frequency

-3dB frequency Fp=2

-20

-15

-10

-5

0

5

10

-4 -2 0 2 4

Ga

in(d

B)

Frequency

Sampling frequency Fs=1

PSD = Power Spectral Density


LOW-PASS FILTERED WHITE NOISE

CRON

)2

bandwidth, equivalent with 4(Or

2

1

24

24

sin)],0()([4

/

)/(1

14H(f)4 ,

,/1

1

21

1 |H(f)|

21

1)( :function transfer RC

),bandwidthinpowerNoiseRMS(

4 :density spectralpower noise sided)-(singleResistor

2

2

1

01

1112

02

2

0

2

21

22

1

1

2

2

fp BkTRC

kTV

CRkTRfkTRV

CxTandxceTanTanfkTRV

dxfdfffxLet

dffpf

kTRdfkTRVPowerNoiseTotal

fwhereffCfR

CfRjRfH

fRvf

kTRR

EQONN

ONONpONN

xpONN

pp

ONONN

CRp

pON

ONjwCON

jwC

PSD

ONPSD

ON

4kTRdf RON

C

Switch model:Resistor in series with Johnson Noise source

Total noise power is independent of RON


SAMPLING LOW-PASS FILTERED WHITE NOISE

2by increased is samplingafter PSD

PSD AFTER

LPF

PSD AFTER SAMPLING

SAMPLING

)2()2(

)2(

][1

1

ssp

spsp

p

sSAMPLED TfCosTfCosh

TfSinhTf

f

fnfPSD

Under-sampling

factorOndulation

function1when .fp.Ts>>1

22

error)gain 10001(for 2 IF

fs

fsTsfp

fsfp

-6

-5

-4

-3

-2

-1

0

-3 -2 -1 0 1 2 3

Ga

in(d

B)

Frequency

10*log(g(f)**2)

-6

-5

-4

-3

-2

-1

0

-3 -2 -1 0 1 2 3

Ga

in(d

B)

Frequency

-14

-12

-10

-8

-6

-4

-2

0

-3 -2 -1 0 1 2 3

Ga

in(d

B)

Frequency

CRp ONf 2

1 As RON decreases, PSDSAMPLED increases


EFFECT OF UNDERSAMPLINGALIASING

-20

-15

-10

-5

0

5

10

-5 -4.5 -4 -3.5 -3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

Gai

n(dB

)

Frequency

gd(x)gd_1(x)gd_2(x)gd_3(x)gd_4(x)gd_5(x)

gd1(x)gd2(x)gd3(x)gd4(x)gd5(x)

10*log10(usf(x))

-20

-15

-10

-5

0

5

10

-5 -4.5 -4 -3.5 -3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

Gai

n(dB

)

Frequency



10*log10(usf(x))

-20

-15

-10

-5

0

5

10

-5 -4.5 -4 -3.5 -3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

Gai

n(dB

)

Frequency



10*log10(usf(x))

-20

-15

-10

-5

0

5

10

-5 -4.5 -4 -3.5 -3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

Gai

n(dB

)

Frequency



10*log10(usf(x))

Fp=2

Fs=10

Fp=2

Fs=5

Fp=2

Fs=2

Fp=2

Fs=1

2

0


HOLDING SAMPLED LOW-PASS FILTERED WHITE NOISE

PSD AFTER SAMPLING

Under-sampling

factor

Double sidedPSD

PSD AFTER HOLD

Hold function

ONSSHOLD RTkTfpTfSINCPSD 2)(2

22

1 )(

0

2 fs

TdfTfSINCB

SSEQ

C

TkfsRTkTfpBPSDPSD ONSEQSAMPLEDHOLD

2222

-15

-10

-5

0

5

10

-3 -2 -1 0 1 2 3

Ga

in(d

B)

Frequency

10*log10(usf(x))

-20

-15

-10

-5

0

5

10

-3 -2 -1 0 1 2 3

Ga

in(d

B)

Frequency

-20

-15

-10

-5

0

5

10

-3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5 3

Ga

in(d

B)

Frequency

EQUIVALENT BANDWIDTH

…calculated in Mathematica


Switching Noise Conclusions

The total noise in the baseband (-fc/2 < f < fc /2 ) due to replicas is kT/C Aliasing due to sampling concentrates the full noise- power of RON into the baseband It is futile to reduce RON below Tsettling requirements since, while direct thermal-noise PSD decreases, aliasing increases, and the two effects cancel Increasing C and fc reduces both direct and aliased thermal-noise PSD’s

C since reduces total noise power kT/C fc since baseband is wider while total noise kT/C is constant


Idea: Pre-Distortion

• Each of these integration techniques distorts the frequency axis, w, in the sampled-domain

• Pre-distortion of the continuous-time function frequency variable, wa to wap with a suitable pre-distortion function, and then mapping the resulting pre-distorted filter function Ha(Sap) to the Z-domain will avoid distortion of the original poles and zeros in the Z-domain filter.

This will be illustrated in the next example


VIN

1 2

CI

-

+

Cu

12

VOUT1

-

+

1 2

CI

Cu

12

VOUT2

1

1

2

21

1

1

12

1

1

2

2121

1

1

11

11

11

Z

Z

C

C

Z

Z

C

CVV

Z

Z

C

CVV

Z

Z

C

CVV

I

U

I

UINOUT

I

UOUTOUT

I

UINOUT

Overall phase error = Tc

Predistortion of single-type (Forward Euler) integrator


)*(**

)1)*(*(*

*

)1)*()*(((*

)1(**

)1(*

)1(*

1*

**

**

1*

1**

**

1*

*

*

*

)**(

*

1

1

sT

s

sT

s

ssT

s

jTs

sT

sU

I

sI

sUINOUTINOUT

I

UINOUTINOUT

TSineF

TCoseF

js

TjSinTCoseFS

eFjS

eZ

ZFsSs

*FC

CR*C

ZFC

FCVV

sCRVV

Z

Z

C

CVV

sCRVV

s

s

s

s

s

DOMAIN SAMPLED DOMAIN TIME CONTINOUS



Poles pre-distortion

0)*0(**00002

0(0

0)1)*0(*(*00002

(0

)*0(**00

)1)*0(*(*00

0*

222

0*222

0*

0*

000

spT

s

SS

S

spT

sS

SSS

sT

s

sT

s

TpSineFFF

FsArcCosFp

TpCoseFF

FFLnFp

TSineF

TCoseF

jp

s

s

s

s

)

POLE SAMPLED POLE DISTORTED-PRE


FILTER THE OF POLE ACONSIDER

CONTINOUS TIME FILTER HAS TO BE SYNTHESIZED USING POLE PRE-DISTORTION METHOD TO OBTAIN THE DESIRED FREQUENCY RESPONSE

WITH SAMPLED FILTER



Method1: Poles pre-distortion

-0.2

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

-1.2 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6

A0(t), O0(t)A0p(t), O0p(t)A0f(t), O0f(t)

Distorted Pole

Pre-Distorted Pole

Desired Pole {-1,1}

0.01<Fs<10



)2

*()

2

*(*2*

)2

*()

2

*(*2*

)(**

)1(***

)1(*

)1(**

**

**

1*

1**

**

1*

2

)(

2

)(

2

)()**(

*

2/1

2/1

1

2/1

sss

sss

jTsjTs

s

jTsjT

s

sT

sU

I

sI

sUINOUTINOUT

I

UINOUTINOUT

TCosh

TSinF

TSinh

TCosF

eeFjS

eeFjSjs

eZ

ZZFsSs

*FC

CR*C

ZF

Z

C

FCVV

sCRVV

Z

Z

C

CVV

sCRVV

s

s


Predistortion of single-type (Backward Euler) integrator


POLE DISTORTED-PRE


FILTER THE OF POLE ACONSIDER

222222

222222

000

))2

0()

2

0(1()

2

0(4)

2

0()

2

0(1

22

0

sin20

2

))2

0()

2

0(1()

2

0(4)

2

0()

2

0(1

20

)2

0()

2

*0(*200

)2

0()

2

*0(*200

TsTsTsTsTs

T

Arc*Fs p

TsTsTsTsTs

ArcCoshFsp

TCosh

TSinF

TSinh

TCosF

jp

S

Sss

Sss

Predistortion of single-type (Backward Euler) integrator


VIN

1 2

CI

-

+

Cu

12

VOUT1

-

+

1 1

CI

Cu

22

VOUT2

1

2/1

2

21

2/1

1

12

12

21

1

1

12

12

2121

1

1

11

11

1

1

1

1

1

1

Z

Z

C

C

Z

Z

C

CVV

ZC

C

Z

Z

C

CVV

ZC

CVV

Z

Z

C

CVV

I

U

I

UINOUT

I

U

I

UINOUT

I

UOUTOUT

I

UINOUT

Overall phase error =0

Predistortion of both-type (Bilinear) integrator


22

22

ssQ

ssQ

VkV

P

PP

Z

ZZ

INOUT

ZsT

sTs

f F

fAF

Fs

fTanF

Z

ZFs

S

SS

S

S

)

)

DOMAIN SAMPLED DOMAIN TIME CONTINUOUS

2

2

tan(

(2

1

12



Ha(Sa) H(z) with Sa = f(z)

aa

aa

TjTj

TjTj

Tj

Tj

Tj

Tj

a

Tj

a

wTw

TanT

w

wTTan

TwwTTan

Tw

wTCos

wTSin

j

Tee

ee

e

e

Te

e

Tjw

ez

jwsZ

Z

Tzfs

2

2

222

2

2

22

222

1

12

1

12)(

1

22

22

2

2

Instead pre-warp (or “pre-distort”) wa wap and use wap instead in f(z)

i.e., w does not map onto wa and so w-axis in z- domain is warped (i.e., bent or compressed)

a

aap

aap

TTTan

TTan

T

TTan

T

TTan

T

22

22

2

2

2

2

11

i.e., Pre-warping now maps w wa

So poles, zero’s will now be mapped correctly

Example: Bilinear Transform

Notation: wa = continuous-time frequency variablewap= pre-distorted continuous-time frequency variablew = discrete-time domain frequency variable



SC Filters synthesis methods

• Synthesis from LC ladder network– Mapping method1– Mapping Method2

• Ladder Filter Design Example

• Synthesis from active RC filters– Bi-quadratic switched capacitor example

• Use of bilinear transform

• Exact transfer function


Synthesis from RLC ladder(1)

C1

R1

C3 C5 R2

L2 L4

V0

V1 V3 V5 V6

V2 V4

I0 I2 I4

I1 I3 I5 I6

OUT

IN

VVVR

VI

sC

IVIII

VVVsL

VI

sC

IVIII

VVVsL

VI

sC

IVIII

VVVR

VI

56 2

66

*5

55 645

534 *4

44

*3

33 423

312 *2

22

*1

11 201

10 1

00Get nodal equations using Kirchoff’s Laws:

1) I=0 at node x2) V=0 around loop yand solve…



OUTIN VVVsC

IVVVV

sC

IVVVV

sC

IVVVV

R

VIIII

sL

VIIII

sL

VIIII

R

VI

56 *5

55 534

*3

33 312

*1

11 10

2

66 645

*4

44 423

*2

22 201

1

00

I2

1

1

1

R

1 1

sC 1

1

1

sL 2

1

1

1

sC 3

1

1

1

1

sL 4

1

1

1

sC 3

1

1

1

2

1

R

1V0 V1 V2 V3 V4 V5 V6 VOUTVIN

I0 I1 I3 I4 I5 I6

1

1R

R

1 1

sCR 1

1

1

sL

R

2

1

1

sCR 3

1

1

1

1

sL

R

4

1

1

sCR 3

1

1

1

2R

R


Vp0

=I0.R

Vp1

=I1.R

Vp2

=I2.R

Vp3

=I3.R

Vp4

=I4.R

Vp5

=I5.R

Vp6

=I6.R



1

1R

R

1 1

sCR 1

1

1

sL

R

2

1

1

sCR 3

1

1

1

1

sL

R

4

1

1

sCR 3

1

1

1

2R

R


Vp0

=I0.R

Vp1

=I1.R

Vp2

=I2.R

Vp3

=I3.R

Vp4

=I4.R

Vp5

=I5.R

Vp6

=I6.R

sCRR

RVV

VsL

VVRV

sCR

VVV

sL

VVRV

sCR

VVVR

R

V PPP

P

PIN

52

4

)(

3

2

)(

1

)(1 54

553

442

331

2

21

1


Ladder Filter Design Example (1)

L

s

in

R

VI

sCV

VVsL

I

IR

VV

sCV

32

33

312

2

21

11

1

1

1

V1 V3L2Rs

C1 C3 RL

Vin Vout

I2

Starting point: LCR prototype “Ladder” filter configuration

Get nodal equations using Kirchoff’s Laws: 1) I=0 at node x2) V=0 around loop ySubsequent equations alternate from V to I


Ladder Filter Design Example (2)Arrange equations schematically.Each -1/s gain stage will become an integrator


Ladder Filter Design Example (3)Replace each -1/s gain stage by it’s continuous time equivalent circuit


Ladder Filter Design Example (4)Replace R’s by switched capacitors


SC Building Blocks

Φ2 Φ1

Φ1Φ2

VIN

C

Φ1 Φ1

Φ2Φ2

VIN

C

VIN

C

Non-Inverting S/C (*)

Inverting S/C

Unswitched C

ΔQ

Φ2

Φ1

VIN

VOUT

Φ2

Φ1

VIN

VNVN-1

VNVN-1

VNVN-1

VN-1VN-2

CVIN ΔQ

-CZ-1VIN ΔQ

C(1-Z-1)VIN ΔQ

(-1/C)/(1-Z-1)VINΔQ

Requiv = T/C = 1/(f.C)For positive R’s

|Requiv| = T/C = 1/(f.C) For negative R’s

Z-domain Transfer Function

VOUT

-

+

CI

+-

Φ1 Φ1

Φ2Φ2

VIN

C(*) Note:

Is an inverting integrator

VOUT


Cascade Filter Design: Biquad Example (1)Second-order S/C Biquad:

out

sT

sT

sT

VwVinw

K

sVWhere

VwVoutQ

wVinsKK

sVout

arrange

wsQw

s

KsKsKeH

sVin

sVoutsH

dsdsd

cscsceHzH

sTez

zbzb

azazazH

00

01

100

21

20

02

012

2

012

2

012

2

12

2

012

2

1:

1

Re

)()(

)()(

)()(

1

1)(

01:

1

021

).(.

:

xnearxeSince

sTe

fff

fj

fjwTs

Note

x

sT

ccc

Lnx

ex

y=x

22ppps

2

12

1

2

p

p

p

ps

Where: (definition) 0 = pole frequency of pole sp = p+ p

Q = Quality factor of H(s)

jw

jwp

p

sp As Q increases, sp becomes closer to the jw-axis=> Get peaking of H(jw) near wo


Biquad Design Example (2) Create a simple block diagram of gain elements and integratorsfrom the rearranged transfer function equation

Create an active-RC realization from above block diagram by:- Assuming each integrator has a current input (or a sum of current inputs), a voltage output, and a feedback capacitor, C Then it’s transfer function is: Vout/Iin=-1/sC=-1/s if C=1

- Replace constant gains with resistors with equivalent current, e.g., for w0 in block diagram above Iint1(in)=Vout*w0 , becomes R=1/ w0

- Replace complex gains with equivalent C or R,C circuit, e.g., K1+K2s is equivalent to a resistor 1/K1 in parallel with a capacitor K2: I = Vin.(K1+K2s)=Vin.(Y1+Y2) Y1=1/Z1=K1, Y2=1/Z2=K2s


Biquad Design Example (3)Use switch-cap building blocks to replace resistors:- Non-inverting for R>0, C=T/R- Inverting for R<0, C=T/|R|- Remove all redundant switches

C1=T.K0/w0 C2=C3= T.w0 C4= T.w0 /QC1’=T.K1C2’= K2


Note that in the Biquad example above we assumed |wT|<< 1

It is fairly easy to get the exact transfer function (T.F.) of the final circuit above by replacing each integrator and branch by it’s z-domain T.F.

• Refer to Z-domain equivalents on Building Blocks slide• Then compare required H(Z) polynomial with calculated T.F. and choose suitable values for components. This will result in a more accurate filter realization. See the following 4 slides

• Limitation: For filters with High-Q poles, I.e., close to jw-axis (or to unit circle in Z-domain) response becomes sensitive to process variations. May become impractical, non-economical

Biquad Realisation Footnote


-

+

-

+

1 G

2

1

2

2

1

H

D

E

B

C

2 A

1

1

2

2

1

1

2

I

2

1

J

F

- +

- +

- + - +

+ -

+ -

+ -

+ -

+ -

+

-

Getting exact transfer function of synthesized Biquad Switched Capacitor Equivalent


Synthesis from RC active filters (3)

E l e m e n t I n i t i a l c h a r g e F i n a l c h a r g e P o l a r i t y D e l t a c h a r g eA 1* ZVA 0 - )*( 1 ZVA

B 1 ZVB VB - ))1(( 1 ZVB

C 0 VC - )( VC

D 1 ZVD VD - ))1(( 1 ZVD

E 1 ZVE VE - ))1(( 1 ZVE

F 0 VF - )( VF

G 0 INVG - )( INVG

H 1 ZVH IN 0 - )( 1 ZVH IN

I 0 INVI - )( INVI

J 1 ZVJ IN 0 - )( 1 ZVJ IN

CHARGE RE-DISTRIBUTION TABLE



Use of bilinear transform

)(4

)(4

)(

4)(

4

)(

2

2

)(

1)2()1(

)()()(

1)2()1(

)()(

22

22

21

21

12

12

12

12

QRP

QRP

TQRP

RP

Tss

NOM

NOM

TNOM

OM

Tss

sT

sT

sTZ

ZRZQP

ZOZNMZT

B

F

B

F

BD

AE

BD

ACZ

BD

AEZ

D

G

BD

FG

BD

IE

BD

IC

BD

IE

BD

JE

BD

JC

B

G

B

H

BD

FHZ

D

H

BD

EJZ

VV

B

F

B

F

BD

AE

BD

ACZ

BD

AEZ

B

I

B

J

B

I

BD

AGZ

BD

AH

B

JZ

VV

SS

SS

S

S

IN

IN

DOMAIN s IN FUNCTIONTRANSFER TRANSFORMBILINEAR INVERSE

DOMAIN Z IN FUNCTIONTRANSFER



Use of bilinear transform

)(2

2

)(2

2

)(4

)(4

)(

4)(

4

)(

22

22

RP

QRPQRPQ

QRP

QRP

T

OM

NOMNOMQ

NOM

NOM

T

QRP

QRP

TQRP

RP

Tss

NOM

NOM

TNOM

OM

Tss

sT

PS

P

ZS

Z

SS

SS

POLES

ZEROS



Use of bilinear transformpre-distortion

szcontinuouzfs

fpTanFsz

spcontinuoupfs

fpTanFsp

z

P

filter Sampled filter time continuous distorted-Pre filter time Continuous

)(2

)(2



Use of bilinear transformCoefficients identification

2

2

2222

)(4

))()22(2(2

)2(2tan

)(4

)()()()(2222

)()(2

)(tan

BD

AE

B

FBD

AC

BD

AE

B

F

BD

AC

qp

BD

AC

BD

AE

B

FD

C

B

A

afs

fP

BD

AH

B

J

B

ID

G

B

A

D

H

B

A

BDB

JAH

BDB

IAH

BDB

AGJ

BDB

AGI

qz

D

H

D

G

B

A

B

J

B

ID

H

D

G

B

A

afs

fz



References

• “Analog MOS Integrated Circuits for Signal Processing”

by Roubik.Gregorian, Gabor C.Temes

• “CMOS Analog Circuit Design”

by Phillip E.Allen, Douglas R.Holberg

• “Analysis and Design of Analog Integrated Circuits”

by Paul R.Gray, Robert G.Meyer

P.Considine Oct, 2001

P.Considine/P.Carbou Nov 2006 1 Switched Capacitor Filters.

Documents

Transcript of P.Considine/P.Carbou Nov 2006 1 Switched Capacitor Filters.