Part I - SoC...

1

Luca Benini ARTIST2 / UNU IIST 2007

Part I - SoC Technology

Silicon technology trends and challengesApplication driversArchitecture evolution

Luca Benini – DEIS Università di [email protected]


1%

99%

Embedded Systems

General purpose systems Embedded systems

Microprocessor market shares

2


Embedded Hardware: Moore’s law

Formulated in 1965 by Intel co-founder G.MooreIC transistor capacity has doubled roughly every

18 months for the past several decades

10,000

1,000

100

10

1

0.1

0.01

0.001

Logic transistors per chip

(in millions)

1981

1 98 3

1 98 5

1 98 7

1 98 9

1 99 1

1 99 3

1 99 5

1 99 7

1 99 9

2 00 1

2 00 3

2 00 5

2 00 7

2 00 9

Note: logarithmic scale


Graphical illustration of Moore’s law

1981 1984 1987 1990 1993 1996 1999 2002

Leading edgechip in 1981

10,000transistors

Leading edgechip in 2002

150,000,000transistors

Something that doubles frequently grows more quickly than most people realize!

A 2002 chip can hold about 15,000 1981 chips inside itself

3


STMicroelectronics Roadmap

Margarshack03

65nm1400Kgates/mm2

45nm2600Kgates/mm2


Technology Progress Overview

Processor speed improvement: 2x per year (since 85). 100x in last decade.DRAM Memory Capacity: 2x in 2 years (since 96). 64x in last decade.DISK capacity: 2x per year (since 97). 250x in last decade.

4


ARM – Embedded Processor Roadmap


Technology bottlenecks

5


Relative delay is growing even for optimized interconnects

Interconnect Bottleneck


Power Bottleneck

1990 1995 2000 2005 2010 2015 2020

100

10-2

10-4

10-6

1

300

200

150

100

250

50

0

Gate-Oxide Leakage

Sub-Threshold Leakage

Dynamic Power

Possible trajectory for high-k dielectrics

Pow

er C

onsu

mpt

ion

Phys

ical

Gat

e Le

ngth

[nm

]

Power trend

0255075

100125150

Power Density (Watts/cm2)

250nm 180nm 130nm 90nm 65nm

Leakage Power

Dynamic Power

Power density trend

[STM ASIC]

6


Variability Bottleneck

0

5 0

10 0

1 50

200

25 0H

eat F

lux

(W/c

m2)

Heat Flux (W/cm2)—Vcc variation

40

50

60

70

80

90

100

110

Tem

pera

ture

(C)

Temp Variation & Hot spots

10

100

1000

10000

1000 500 250 130 65 32

Technology Node (nm)

Mea

n N

umbe

r of

Dop

ant

Ato

ms

Random Dopant Fluctuations

0.01

0.1

1

1980 1990 2000 2010 2020

micron

10

100

1000

nm193nm248nm365nm Lithography

Wavelength

65nm90nm

130nm

Generation

Gap

45nm32nm

13nm EUV

180nm

Source: Mark Bohr, Intel

Sub-wavelength Lithography

[Borkar05]


Impact of Static Variations

30%

5X

FrequencyFrequency~30%~30%

LeakageLeakagePowerPower~5~5--10X10X

0.90.9

1.01.0

1.11.1

1.21.2

1.31.3

1.41.4

11 22 33 44 55Normalized Leakage (Normalized Leakage (IsbIsb))

Nor

mal

ized

Fre

quen

cyN

orm

aliz

ed F

requ

ency

Today…

[Borkar05]

7


Technology Outlook

Medium High Very HighVariability

Energy scaling will slow down>0.5>0.5>0.35

Energy/Logic Op scaling

0.5 to 1 layer per generation8-97-86-7Metal Layers

11111111RC Delay

Reduce slowly towards 2-2.5<3~3ILD (K)

Low Probability High ProbabilityAlternate, 3G etc

128

11

2016

High Probability Low ProbabilityBulk Planar CMOS

Delay scaling will slow down>0.7~0.70.7Delay = CV/I scaling

256643216842Integration Capacity (BT)

8162232456590Technology Node (nm)

2018201420122010200820062004High Volume Manufacturing

Extreme variations are expected!


Reliability Bottleneck

Soft Error FIT/Chip (Logic & Mem)

0

50

100

150

180

130 90 65 45 32 22 16

Rel

ativ

e

~8% degradation/bit/generation

Time dependent device degradation

0

1

1 2 3 4 5 6 7 8 9 10Time

Ion

Rel

ativ

e

Extreme device variations

0

50

100

100 120 140 160 180 200Vt(mV)

Rel

ativ

e

Wider

8


Circuit Design Tradeoffs

00.5

11.5

2

Low-Vt usagelow high

Higher probability of target frequency with:1. Larger transistor sizes 2. Higher Low-Vt usage

But with power penalty

00.5

11.5

2

Transistor sizesmall large

powertarget frequency probability


0

0.5

1

1.5

Logic depthsmalllarge

frequencytarget frequency probability # uArch critical paths

0

0.5

1

1.5

less more

μArchitecture Tradeoffs

Higher target frequency with:1. Shallow logic depth2. Larger number of critical paths

But with lower probability

9


Designer Productivity GapLogic Transistors/ChipTransistor/Staff Month

58%/Yr. compoundComplexity growth rate

21%/Yr. compoundProductivity growth rate

Source: SEMATECH19

81

1983

1985

1987

1989

1991

1 993

199 5

199 7

1999

200 3

2001

2005

2007

2009

1K

10K

100K

1M

10M

100M

1B

10B

10

100

1K

10K

100K

1M

10M

100MC

ompl

exity

Log

icT

rans

isto

rs p

er C

hip

(K)

Prod

uctiv

ityT

rans

isto

rs/S

taff

Mon

th

SoC designs today are complex, characterized by more and more IPs being integrated on a single chip, and a shrinking time-to-market


Application drivers

10


Example Area: Automotive Electronics

What is “automotive electronics”?

Vehicle functions implemented with electronics

Body electronicsSystem electronics: chassis, engineInformation/entertainment


Automotive Electronics Market Size

8.9Market ($billions) 10.5 13.1 14.1 15.8 17.4 19.3 21.0

0200

400600

8001000

12001400

1998 1999 2000 2001 2002 2003 2004 2005

Cost of Electronics / Car ($)

90% of future innovations in vehicles:based on electronic embedded systems

2006: 25% of the total cost of a car will be electronics

11


Automotive Electronics Platform Example

Source: Expanding automotive electronic systems, IEEE Computer, Jan. 2002


Digital Convergence – Mobile Example

Broadcasting

TelematicsImaging

Computing

CommunicationEntertainment

One device, multiple functionsCenter of ubiquitous media networkSmart mobile device: next drive for semicon. Industry

12


4th Gen and Next-Gen Networks

Includes: 802.20, WiMAX (802.16), HSDPA, TDD UMTS, UMTS and future versions of UMTS


Mobile graphics/games

Millions of unitsJon Peddie Research

Handheld Multimedia Devices report

0

100

200

300

400

500

600

700

800

900

2001 2002 2003 2004 2005 2006 2007 2008 2009 2010

MM phonesNon 3D MM phonesNative API based phones

Resolution today ~176x208 –320x240In Japan, QVGA (320x240) is the normNokia series 90 is 640x320Nokia N93 is 320x200Sony Ericsson S700i, M600i, K800i: 240x320

To 1024x768 in the future, VGA (640x400) first

13


Automotive applications trends

[ARM06]


Mobile applications trends

[ARM06]

14


Consumer/Home applications trends

[ARM06]


Media Portability ProblemMedia infrastructure portability is a multi-level industry problem

Media infrastructure is time-consuming and expensive to develop, integrate and program

Software component & silicon vendors need to a reliable way to

accelerate diverse codecs on diverse silicon

System integrators need cross-vendor standard for media component integration with

sophisticated data routing and robust synchronization

Application programmers need a cross-platform

portable API for controlling high-level media operations

Media ComponentsInputs, video codecs, image and

sound libraries, outputs etc.

Media GraphsMedia components connected to

process media in real-time

Media ApplicationsUse media networks to deliver a

compelling user experience

Media Infrastructure StackHardware and software to deliver rich

media processing solutions

Media applications are not portable as proprietary hardware-

centric libraries are needed to access media acceleration

Difficult to flexibly integrate diverse, multi-vendor media

components into complete media processing solutions

Software components are not portable across processors -

exacerbated by proliferation of media standards and increasing

silicon complexity

15


3DSmall footprint 3D for embedded systems

Complete Khronos Media Stack

Vector 2DLow-level vectoracceleration API

Media Engines – CPUs, DSP, Hardware Accelerators etc.

Platform MediaFrameworks

IL

SOUNDLow-level

gaming audio acceleration

API Image Libraries, Video Codecs,Sound Libraries

Accelerated media primitives for codec

developmentDL

Component interfaces for codec integration

AL

Playback and recording interfaces

Khronos defines low-level, FOUNDATION-level APIs.“Close to the hardware” abstraction provides portability AND flexibility

The Khronos API family provides a complete ROYALTY-FREE, cross-platform media acceleration platform

Applications or middleware libraries (JSR 184 engines, Flash players, media players etc.)

EGLAbstracted Access to

OS ResourcesFast mixed mode 2D/3D

rendering


Mid-2005OpenVG 1.0 Spec release

Adoption of Khronos APIs

Time

Silicon Designs in progress

Rapid adoption when silicon ships

Widespread, cross-platform availability

Market adoption in media-accelerated handsets

Mid-2004OpenGL ES 1.1

Spec release

Beginning-2006OpenMax IL 1.0

Spec release

End-2006OpenSL ES 1.0

Spec release

We Are Here - OpenGL ES is widespread

- OpenVG is in rapid adoption- OpenMAX is being implemented

- OpenSL ES is being designed

100%

16


The Ambient Intelligence Dream

Secure, trustworthy computing and communicationembedded in every-thing and every-one.

A pervasive, context aware ambient, sensitive and responsive to the presence of people


AmI = Complex Interplay of 4 Technologies driven by Societal Challenges

Embedded (distributed) computing

Ubiquitous adaptive wireless communication

Transducer networks i/f to physical world

Multi-mode, natural interfaces to the user

©ISTAG

©Philips

17


Application pull

Year of Introduction2005 2007 2009 2011 2013 2015

5 GOPS/W

100GOPS/W

Signrecognition

A/Vstreaming

Adaptiveroute

Collisionavoidance

Autonomousdriving

3D projecteddisplay

HMI by motionGesture detection

Ubiquitousnavigation

Si Xray

Gbit radio

UWB

802.11n

Structured encoding

Structured decoding

3D TV 3D gaming

H264encoding

H264decoding

Imagerecognition

Fully recognition(security)

Autopersonalization

dictation

3D ambientinteraction

LanguageEmotionrecognition

Gesturerecognition

Expressionrecognition

MobileBase-band

1TOPS/W

[IMEC]


• Must be dependable,• Reliability R(t) = probability of system working

correctly provided that is was working at t=0• Maintainability M(d) = probability of system working

correctly d time units after error occurred.• Availability: probability of system working at time t• Safety: no harm to be caused• Security: confidential and authentic communication• Even perfectly designed systems can fail if the

assumptions about the workload and possible errors turn out to be wrong.

• Making the system dependable must not be an after-thought, it must be considered from the very beginning

Characteristics of AMI systems

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Characteristics of AMI Systems (2)Must be efficient

Energy efficientCode-size efficient (especially for systems on a chip)Run-time efficientWeight efficientCost efficient

Dedicated towards a certain applicationKnowledge about behavior can at design time can be used to minimize resources and to maximize robustnessDedicated user interface(no mouse, keyboard and screen)


Characteristics of AMI Systems (3)

Many ES must meet real-time constraintsA real-time system must react to stimuli from the controlled object (or the operator) within the time interval dictated by the environment.For real-time systems, right answers arriving too late are wrong.„A real-time constraint is called hard, if not meeting that constraint could result in a catastrophe“ [Kopetz, 1997].All other time-constraints are called soft.A guaranteed system response has to be explained without statistical arguments

19


Characteristics of AMI Systems 4

Frequently connected to physical environmentthrough sensors and actors,Hybrid systems(analog + digital parts).

Typically, ES are reactive systems:„A reactive system is one which is in continual interaction with is environment and executes at a pace determined by that environment“ [Bergé, 1995]Behavior depends on input and current state.

automata model appropriate,model of computable functions inappropriate.


Architecture Evolution

20


The AMI processing Bestiary

The work-horsePowers the fixed base network machines

Power W Performance GB/s

The hummingbirdPowers the wireless base network interfaces

Power mW Performance MB/s

The butterflyThe sensor network hardware

Power µW Performance KB/s


L3 CACHE (1.5/3 MB)

Released at 733MHz and 800MHz, now 1GHzThree level caching system25 million transistors in the CPU and 300 million in the cache (0.18µm)421mm2 die size

Itanium® 2 Processor

The CPU running at full load draws ~130 WattsThe clock signals and logic total to approx 84% of the total power usage. Leakage power: approx. 2%.Power delivery: Vdd=1.5V, P=130W, P=VddI (!!)

21


Handset architecture

C540

ARM7

TI’s TMS320vc5471


Berkeley’s Daft Dust Device

63 mm3

Circuits: 0.25 µm CMOSdigital circuits underneath ground padmetal shields to prevent photogenerated carriers

CCR: Cronos MUMPSOptical wireless connection (line of sight)

360µm

300µ

m

PhotodiodePad toCCR

VddPadGND Pad/ LFSR

Power-on ResetCha

rge

Pum

p

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Device Classes for AmIStationary Nomadic Transducer

Am

bient Body

Home

OfficeCar

“UPA”

TCRF

TCRF

TCRF

UMTSWLANWPANWBANDA/VB

PDADSCDVCMP3GPSHC…

Hear, See, Feel, Show…

“More Moore” “More-than-Moore”

MIMO

Internet IPv6

100Gop/s 10 Gop/s

1Watt 100mW

‘Milliwatt’ (battery, f.c.)

10 Watt

‘Watt’ (mains)

1Top/s 10Mop/s

Gb/s

0.1Gb/s

kb/s

100μW

energy

energy

energy

(ambient)‘Microwatt’


‘More Moore’ vs. ‘More than Moore’

‘More Moore’ ‘More than Moore’

ComputingStorage

Interaction with user andambient

MasteringGiga-Complexity

Low Power Digital SoC

Embedded Software

Ultra-CreativityUltra-low power

Multi-TechOn-Top-of-CMOS

CMOS Memory RF Passives Sensors FluidicsDisplaysMems

Baseline CMOS On-top-of-CMOS

Source: Medea+

Power Sources

<1cm3SiP

90nm

16nm

23


SoC: Enabler for Digital Convergence

Today

> 100XPerformanceLow PowerComplexity

Storage

4G/5G, DMB, WiBro, etc.

SoCSoCSoC

Future


SoC INTEGRATION

Number of integrated technologies limited by costconsiderations

Potential side-by-side integration of Si, GaAs, MEMs

24


Chip composition

Strong unbalance between logic and memory areaoccupancy


System / ServiceApplication S/W

Mobile TerminalMiddleware

ModuleRTOS

ChipHAL

ProcessS/W IP

Target System Application

Requires design of Hardware AND software

SoC Solution-on-a-Chip

+

SOCSOC

System e-SW

Chip

25


Power-Flexibility ConflictSource: T.Claasen (ISSCC99 p1.2)

32 bit IPE

GP microprocessor

2 1 0.5 0.25 0.13 0.07feature size(μm)

1000

100

10

1

0.1

0.01

0.001

Power efficiency PE (GOPS/Watt)

Reconfigurable // computingMuxed data paths

IS Computing mpuasip-dsp

cgfg

AmI


The Architectural Gap

Create SL methods, tools and skills for designing flexible, yet power-efficient platforms

= 1 B uncertain devices + >10M lines of code

for mapping real-time MULTIPLE S/W applications on them at lowest NRE cost

Greatest Challenge:Overcome Power-Flexibility ConflictWhile coping with CMOS (r)evolution

“Managing Giga-Complexity ”

26


Competing imperatives

Technology push:high-volume products;feasible design.

Marketing push:fast turnaround;differentiated products.

IBM PowerPC 750

Nokia 9210


ROI Goal: One Design, Many Design-ins

$10M design cost, $15 manf. cost, 5% premium for programmability

Low-endstill camera

High-endstill camera

Video camcorder

one chip

many systemdesigns

0

20

40

60

80

100

120

1 2 3 4 5 6 7

100,000

1,000,000

System designs per chip design

Tota

l per

uni

t cos

t

SOC Flexibility = Cost Reduction (Model: 100K and 1M system volumes)

27


Flexibility is the Key to ROI

=↑↓↑↑

=−

==*

costt developmen chip)costunit chipASP (chip*volume

InvestmentReturnROI

Flexibility means more systems per design

Programmability more “hot features” available Little impact

on chip cost –pennies per processor

Reduce design time, team size and re-spin risk


What is a (HW) platform?

A partial design:for a particular type of system;includes embedded processor(s);may include embedded software;customizable to requirements:

software;component changes.

IBM CoreConnect

28


The “hourglass” model

A rchitectural Space

A pplication Space

A pplication Instance

P latform Instance

S ystemPlatform

PlatformD esign SpaceE xploration

P latformSpecification

A Hardware Platform is a family of architectures that satisfy a set of architectural constraintsimposed to allow the re-use of hardware and software components.


Why platforms?

Any given space has a limited number of good solutions to its basic problems.A platform captures the good solutions to the important design challenges in that space.A platform reuses architectures.

29


Standards and platforms

Many high-volume markets are standards-driven:

wireless;multimedia;networking.

Standard defines the basicI/O requirements.

bluetooth.com

MPEG Tamperemeeting


Standards and platforms 2

Systems house chooses implementation of standards functions:

improved quality, lower power, etc.Product may be differentiated by added features:

cell phone user interface.Standards encourage platform-based design.

30


Platform vs. full-custom

Platform has many fewer degrees of freedom:

harder to differentiate;can analyze design characteristics.

Full-custom:extremely long design cycles;may use less aggressive design styles if you can’t reuse some pieces.


Platforms and embedded computing

Platforms rely on embedded processors:

can be customized through software;can put considerable design effort into the CPU.

Many platforms are complex heterogeneous multiprocessors.

Agere StarPro

31


Platforms and IP-based design

Platforms use IP:CPUs;memories;I/O devices.

Platforms are IP at the next level of abstraction.


Advantages of platform-based design

Fast time-to-market.Reuse system design---hardware, software.Allows chip to be customized to add value.

32


Costs of platform-based design

Masks.NRE: design of the platform + customization.Design verification.


Two phases of platform-based design

Design the platform.Use the platform.

requirements past designs

platform

userneeds

product

33


Division of labor

Platform design:choose, characterize hardware units;create the system architecture;optimize for performance, power.

Platform-based product design:modify hardware architecture;optimize programs.


Semiconductor vs. systems house

Semiconductor house designs the platform.Systems house customizes the platform for its system:

customization may be done in-house or by contractor.

34


Platform design challenges

Does it satisfy the application’s basic requirements?Is it sufficiently customizable? And in the right ways?Is it cost-effective?How long does it take to turn a platform into a product?


Platform design methodology

Size the problem.How much horsepower? How much power?

Develop an initial architecture.Evaluate for performance, power, etc.Evaluate customizability.Improve platform after each use.

35


Platform use challenges

How do I understand the platform’s design?How do I modify it to suit my needs?How do I optimize for performance, power, etc.?


Platform use methodology

Start with reference design, evaluate differences required for your features.Evaluate hardware changes.Implement hardware and software changes in parallel.Integrate and test.

36


Design refinement

Bad news:hard to learn the platform in order to change it.

Good news:an existing design can be measured, analyzed, and refined.

Worldwide shipping by UPS ...

roughly US$ 50 for CD and US$ 100 for paper copy

(1500 pages, heavy!)Bluetooth.com


Hardware Platforms Not Enough!

Hardware platform has to be abstractedInterface to the application software is the “API”Software layer performs abstraction:

Programmable cores and memory subsystem “hidden” by RTOS and compilersI/O subsystem with Device DriversNetwork with Network Communication Software

37


Software Platforms

Output DevicesInput devices

Hardware Platform

I O

Hardware

Software

network

Software Platform

Application Software Platform API

Software Platform

RT

OS

BIOS

Device DriversN

etw

ork

Com

mun

icat

ion


Hw ASIC Sw SoC Platform

1

10

100

1000

104

105

106

107

108

1980 1985 1990 1995 2000 2005Year

IP

Chip

Logicff,oa

RTopr

dac,adc,uartbus

Coproc.Mpeg2,jpeg,

coders

ASIC1 application

NRE cost> 50M€DSP

ASIPRAMBUS

Platform Hw&Sw

NO

CR

F-SDR

Multi-C

ore

n applications

+ EmbeddedSoftware

Middleware

38


Software and hardware reuse

Want to reuse as many hardware components as possible:

known performance, power.

Want to use software libraries where possible.RTOS simplifies design of multi-tasking systems.



Hardware Platform

I O

Hardware

network

DUAL-CORE

RTO

S

BIOS

Device Drivers

Net

wor

k C

omm

unic

atio

n

DUAL-CORE

Architectural Space (Performance)

Application Space (Features)

HW-SW Platforms: Exploration and Reuse

Platform Instance

Application Instances

System Platform(no ISA)

Platform Design Space Exploration

PlatformSpecification

Platform API

Software Platform


Hardware Platform

I O

Hardware

network

Alternate

RTO

S

BIOS

Device Drivers

Net

wor

k C

omm

unic

atio

n

Alternate

RTO

S

BIOS

Device Drivers

Net

wor

k C

omm

unic

atio

n


Hardware Platform

I O

Hardware

network

Core

RTO

S

BIOS

Device Drivers

Net

wor

k C

omm

unic

atio

n

Core

Application Software

Application Software

39


Platform Eco-System: e.g. TI OMAP

SystemHouses

Device & Equipment ManufacturersNokia, Ericsson, Sony, TI for Handspring, Acer Communications & Multimedia Inc, High Tech Computer Corporation, LG, Compal,

GVC, Quanta Computer, ZTE, Sendo, Arima, ASUSTeK, Compal, DBTel, Quanta, Inventec, Tecom, Chi Mei, Ares, Inventec, TelePaq, FIC, Mitac-Synnex, Universal Scientific

Industrial.

Virtual Component(SW IP) Providers

Application & Middleware ProvidersMicrosoft, Real Networks,

PacketVideo, GeoVector, TI Security Lib., Atelier Phone SW, GPRS SW, AM ROAD Electronics, Ultima Electronics,

ProSense, Chanceux

Consumer

Development CentersBSQUARE, Productivity Systems, Inc. (PSI), PacketVideo Partners

Texas Instruments PartnersNokia, Ericsson, Sony,TI for Handspring, Acer

SemiconductorHouses

TI OMAP

Virtual Component(HW IP) Providers

SW IP:Symbian

SDK & OS (EPOC), MS WinCE, DSP BIOS, OSE

HW IP ARM

Source: IEEE Computer


Pros and cons

Plentiful hardware options.Simple programming semantics.Good software development environments.Performance-limited.

40


Summary

Technology evolutionBottlenecks

ApplicationsApplication trendsAmbient intelligence

Platforms

Part I - SoC...

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