OVERCOMING KEY CHALLENGES OF TODAY'S COMPLEX SOC: PERFORMANCE OPTIMIZATION AND VERIFICATION QUALITY

OVERCOMING KEY CHALLENGES OF TODAY'S COMPLEX SOC: PERFORMANCE OPTIMIZATION AND VERIFICATION QUALITY

PANKAJ SINGH, ASHISH JAIN, NARENDRA KAMAT

2| The 12th International System-on-Chip Conference, Nov. 22-23, 2014 | OCTOBER 31, 2014 |

OUTLINE

POWER MANAGEMENT FOR IMPROVED ENERGY EFFICIENCY AND

VERIFICATION CHALLENGES

SKIN TEMPERATURE AWARE POWER MANAGEMENT

BATTERY BOOST

PERFORMANCE ANALYSIS ENVIRONMENT

REUSE VERIFICATION ENVIRONMENT

SOC VERIFICATION

UVM METHODOLOGY & WHAT NEXT.

CHALLENGES/GAPS: HW-SW DEBUG, VIRTUAL PROTOTYPE MODEL.

EMULATION CONFIGURATION OPTIONS.

Power Mgmt forEnergy Efficiency &Verification Challenges

Performance Analysis Verification Environment

SoC VerificationChallenges

POWER MANAGEMENT FOR IMPROVED ENERGY EFFICIENCY ANDVERIFICATION CHALLENGES

Power Mgmt. forEnergy Efficiency &VerificationChallenges


SoC VerificationChallenges: UVM,HW-SW Debug, VP,Emulation

| The 12th International System-on-Chip Conference, Nov. 22-23, 2014 | OCTOBER 31, 2014 |

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POWER MANAGEMENT UNIT

* Physical monitors on the chip/platform, or digital estimators based on activity, other parameters

Power Monitors

Current Monitors

Temperature Monitors

Monitors*

Filters & Comparators

> < =

Platform Constraints

CPU

Graphics

NorthBridge/ Memory Interface

Multimedia

APU Power Controllers

Operating points for different

APUEntities

APU activity,power, thermal inputs

PLATFORM INFRASTRUCTURE CONSTRAINTSPlatform Component Constraint

Cooling solution/Heat sink Heat dissipation ability to maintain die & system temperature

AC Brick Power/Current carrying capability

Battery pack Power/Current carrying capability

Voltage Regulators/FETs on the board Current carrying capability, thermals


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MUCH MORE CONFIGURABILITY AND FLEXIBILITY

APU Power/ Thermal Profile


Platform Power

and Thermal Profile

Old Paradigm: Adjust platform design to fit the APU’s power/thermal profile


Platform Power

and Thermal Profile

Platform Power

and Thermal Profile

New Reality/Challenge: Configure APU to fit the platform’s power/thermal profile


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DYNAMIC CONFIGURABILITY

2-in-1 Convertibles:

Clamshell versus tablet/slate mode

Docked

versus

Undocked Modes

System BIOS

Platform Events

Docked/Undocked, Tablet/Clamshell Mode

Changes

Power Management

Unit

Frequency/ Power Limits

To match the Config Requirements

Parameters Config 1 (Docked) Config 2 (Undocked) Config 3 (…)

TDP Limit 18W 12W 15W

Surface Temp Limit 50C 42C 45C

… … … …


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SKIN TEMPERATURE AWARE POWER MANAGEMENT

Without STAPM

With STAPM

Without STAPM

With STAPM


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BATTERY BOOST

= Increased efficiency

Energy use drops While Performance

increases

Based on 3DMark11 (Performance preset) on 15W quad-code Kabini (KB 15w4c) and 15W quad-code Beema (BM 15w4c) . Pre-production engineering samples of APUs used with 2x8GB DDR3 1866 RAM, 1280x720 display panel, Windows 8.0 and unreleased reference driver


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Complex interaction among various hardware components and software components require a multi-level verification approach

Software readiness as important and critical for time-to-market as a robust and verified hardware design

Verification environment not only needs to model SOC components but System/Platform components as well

IP level verification of basic blocks like the activity monitors

SOC level verification of the accumulator and controller logic

APU

FIRMWARE

BIOS

DRIVER

Software validationusing a behavioral level model of the hardware

HW-SW cosim and/or Emulation for verification of interfaces between hardware components and software modules


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Typically software readiness and hardware schedules are mis-aligned

‒ Software development delayed with respect to hardware development to bank on the time between design tapeout and silicon arrival

‒ Puts any software-hardware co-verification at great risk

‒ Alignment of software and hardware schedules a ‘must-have’ requirement for successful execution of current generation power management architecture

IP Level Verification

SOC Verification

HW/SW Co-verification/Emulation

Software (BIOS, Driver, Firmware) Verification

PERFORMANCE ANALYSISENVIRONMENT

Power Mgmt. forEnergy Efficiency &Verification Challenges




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SOC PERFORMANCE

Trends:

‒ Chip industry: Lot more disparate client IPs on one chip…

‒ Platform/software use cases: Big Data, HPC, more displays, higher resolution…

Memory is the bottleneck

‒ Interconnect performance is critical to maximize potential of engine IPs

Each client has different general characteristics

‒ CPU: Latency sensitive for single-threaded performance; latency-under-load

‒ GFX: Massively parallel workloads; huge appetite for memory bandwidth

‒ Display and Real-time clients: Burst traffic, with demanding QoS requirements

Visual Computing

HPC

Big Data

Evolutionary design

System-on-Chip

Reuse

New Class of Applications: Large Data Sets, Massively Parallel

New Class ofConstraints: IP Reuse, Large Complex SOCs

Memory Subsystem

(Interconnect) Performance

Applications demand high-performance memory access

Larger no# clients demand high performance memory access


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PERFORMANCE VALIDATION FOR INTERCONNECT IP

Ensure that performance metrics of interest meet the product goals

Metrics:

‒ Peak bandwidth

‒ DRAM utilization efficiency

‒ Unloaded latency for different clients

‒ Loaded latency curve

Use RTL simulation

Related approach is to use an abstract performance model.


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BANDWIDTH MEASUREMENT AT INTERFACE

Inbound Data

• Record number of bytes moved

Outbound Data

• Record number of bytes moved

LATENCY MEASUREMENT AT INTERFACE

Inbound Request

• Save tag/timestamp

Outbound Response

• Match tag

• Delta with saved timestamp

• Record latency


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INTERCONNECT IP

Interconnect

CPU1CPU0

GPUIO

DRAM Chn 1

DRAM Chn 0

Interface points for primary

performance measurements

- Need low development/maintenance cost

- Interfaces not necessarily identical

Keychallenges

- Reuse existing functional verification code

- Leverage industry-standard UVM framework

- Software engineering approachApproach

DESIGN PARAMETERS


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TRACKER CLASS

Simple/minimal codeTwo types:

Bandwidth[B.W] & Latency

Data structures to track the selected

metric[B.W and latency]

One tracker per metric per interface

Scoreboard instantiates tracker objects, and

invokes track method when transactions are

observed


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PERFORMANCE SCOREBOARDS AT EACH INTERFACE

Interconnect

CPU1CPU0

GPUIO

DRAM Chn 1

DRAM Chn 0

SB SB

SBSB

SCOREBOARD FUNCTIONS

Callbacks registered with verification monitors for all

data transactions (UVM: analysis ports)

Master (instantiate) tracker objects

When callback received, invoke track method on all

trackers.


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END OF SIMULATION

Top-level performance environment module queries each scoreboard for metrics

Each scoreboard queries each instantiated tracker for metrics

Bottom-up rollup of data, formatted and printed in a file for analysis.

Env

CPU0 Scoreboard

BW TrackerLatency Tracker

CPU1 Scoreboard


GPU Scoreboard


IO Scoreboard



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ADVANTAGES

Minimal new code (low development/maintenance costs)

Leverages existing verification testbench infrastructure

Exploits recurring measurement patterns

Code portable from IP-level to SOC-level

UVM (standard) compliant

SOC VERIFICATION CHALLENGES

Power Mgmt. forEnergy Efficiency &Verification Challenges




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VERIFICATION CHALLENGE : INCREASED COMPLEXITY, INCREASE IN CORES AND REDUCED TIME TO MARKET

Baseline Design

Design Complexity

Power Management

Firmware

Software

Baseline Design

Design Complexity

Power Management

Firmware

Software

Co

mp

lexi

ty

TimeReduced Design Cycle

Incr

ease

d C

om

ple

xity

Design Cycle

0

5

10

15

20

25

0

20

40

60

80

100

120

140

2006 2011 2014

IPs (left axis)

Average IP and Processor Core trendsin advanced SoCs

Source: Caspi, HVC 2013

IP C

ore

s

Emb

edd

ed P

roce

sso

r C

ore

s

Ref: [3]


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UVM 1.2UVM

Testbench

UVM Methodology – A big leap in Verification. What Next?

reusable

Source : uvm cookbook


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HW-SW DEBUG

SoC verification involves lot of embedded software

The number of heterogeneous cores are growing‒ Need for the debug process capability of simultaneously

viewing multiple cores both from a HW perspective as well as from programmers point of view

SoC debug need a simultaneous view of both hardware and software‒ RTL and gate level, including HDL source code,

waveform, schematic, assertion, testbench, transaction and power-aware debug

‒ Programmer's view of both C/C++ and assembly code as well as memory, register and breakpoint windows

‒ No standard tool or accepted methodology exist. The debug tool released this year by EDA company’s could evolve and fill the HW-SW gap.


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VIRTUAL PROTOTYPE MODEL - GAPS

RTL and VP are developed in two parallel streams

VP model used for Architecture exploration, SW development, Reference model for verification. However gaps exist in developing good quality of VP model

‒ Largely the firmware code is applied to verify the VP – may not cover entire VP . No randomization used.

‒ Coverage still largely eludes the VP verification. Tools available in market do not address the coverage topic in a straight forward way especially toggle coverage

Therefore, determining “Are we Done? “ for VP verification poses big gaps


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EMULATION: WHEN TO USE WHICH CONFIGURATION?

CharacteristicsIn-circuit

EmulationEmbedded Target

EmulationHybrid

Virtual/Emulation

Why

• Connecting real hardware to your design

• Real peripheral device testing• Real-world traffic

• Enables Save/Restore• Easily re-locatable• Additional debug monitoring

• Enables Save/Restore• Easily re-locatable• Capacity savings• Highest performance• Improved software debug

When to use

• When testing in real environment with real devices is important

• When CPU validation is a higher priority

• When highest model accuracy is required

• When getting deep into workloads is important

• When CPU validation is a higher priority

• When capacity is available

• Need to run large software workloads

• When CPU validation is a lower priority

• Fast initial bring-up of OS

Who

• Platform engineering teams• Design teams• Product engineering teams

• Platform engineering teams• Design teams

• Software teams• GFX driver developers• Platform engineering teams• Design teams

Reference: [3] cdnlive ’14 . Alex Starr, Brian Fisk


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SUMMARY

EFFICIENT POWER MANAGEMENT TECHNIQUES SUCH AS STAPM AND BATTERY BOOST FOR IMPROVED ENERGY EFFICIENCY [PERFORMANCE/WATT]

DEVELOPING PERFORMANCE ANALYSIS ENVIRONMENT BY REUSING EXISTING VERIFICATION ENVIRONMENT

HOLISTIC VIEW OF SOC VERIFICATION :

EVOLUTION OF UVM METHDOLOGY, UVM 1.2 AND CHALLENGES WITH MULTI LANGUAGE SUPPORT/AMS SUPPORT.

EDA INDUSTRY/TOOL CHALLENGES WITH HW-SW DEBUG, VP MODEL VERIFICATION.

H/W ASSISTED SIMULATION ACCELERATION, CHOOSING EMULATION CONFIGURATION FOR YOUR DESIGN.

Power Mgmt forEnergy Efficiency &Verification Challenges


SoC VerificationChallenges


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THANKYOU


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REFERENCES

1. Applying AMD's "Kaveri" APU for Heterogeneous Computing. Hot Chips 26 -Palo Alto, CA. Bouvier Dan, Sander Ben

2. UVM CookBook

3. Complementing In-circuit Emulation with Virtualization for Improved Efficiency, Debug Productivity, and Performance. CDNLIVE SI VALLEY 2014. Alex Starr, Brian Fisk

4. Harry Foster, Mentor Graphics. DAC’14


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DISCLAIMER & ATTRIBUTION

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AMD MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE CONTENTS HEREOF AND ASSUMES NO RESPONSIBILITY FOR ANY INACCURACIES, ERRORS OR OMISSIONS THAT MAY APPEAR IN THIS INFORMATION.

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ATTRIBUTION

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OVERCOMING KEY CHALLENGES OF TODAY'S COMPLEX SOC: PERFORMANCE OPTIMIZATION AND VERIFICATION QUALITY

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