Os Hardware Ch 3
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Transcript of Os Hardware Ch 3
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Operating Systems Hardware
Components
CIS 320, Fall, 2011
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Objectives
2
Explain operating system hardware components
and their key characteristics
Describe the basic features and system
architecture of popular PC processors Understand how hardware components interact
with operating systems
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Understanding CPUs
The system architecture of the computer is builtaround the CPU System architecture includes the number and type of CPUs in
the hardware, and the communications routes (buses) between
CPUs and other hardware components CPUchip that performs the actual computational
and logic work
Coresection of the processor that actually does
the reading and execution of instructions Processors originally only had one core
Multicore processor has two or more cores
Multiprocessor computershave multiple physicalCPU chips
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Understanding CPUs
CPU hardware elements:
Design typeData bus
Cache Address bus
Speed Control bus
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Design Type
Two general CPU designs: CISC (Complex Instruction Set Computer)
pronounced sisk
RISC (Reduced Instruction Set Computer)
pronounced risk
Main difference number of different instructions the chip can process
Instruction set
the list of commands the CPU can understand and carry out
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CISC Characteristics
How a CISC CPU operates When the CPU gets a command it assigns specific instructions to
different parts of the chip
When a command is finished and the next command is received, the
CPU uses the same parts of the chip it used before
Advantages of CISC: Only needs general-purpose hardware to carry out commands versus
hardware designed for a specific purpose
Chip is driven mainly by software, which is cheaper to produce
Disadvantages of CISC: Complexity of on-chip software needed to make the hardware do the
right thing
The need to continually reprogram the on-chip hardware
CISC chips can be a little slower than RISC chips
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CISC Characteristics (Continued)
CISC CPU Because general hardware is used, functions will not be
executed in the most efficient way
Hardware modules can be added that are optimized to perform
certain functions
ExampleA math coprocessor can be added in order to help
perform all computational functions
CPU performance is increased
Increases price
Math co-processors originally a separate chip now often part of the
CPU chip
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RISC Characteristics
Advantages Has smaller instruction set, and uses these small instructions to put
together more complex operations
Hardware only needs to support the smaller instruction set, in theory
should cost less With small instructions, the system can pipeline
pipelining - allows the processor to operate on one instruction at
the same time it is fetching one or more subsequent instructions
Disadvantages
May require more instructions to complete a given high level request
Intel / CISC owns the market share
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Design Type
CISC versus RISC processing
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Does Pipelining help here?
1.
C := A + B;
F := D + E;
I := G + H;
L := I + J;2.
A := B + C;
A += D;A += E;
A += F
A + = GOS Related Harware Components 10
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CISC vs RISC
Waters are becoming more muddied
CISC based CPUs (intel) adopting many features
of RISC and RISC based chips expanding their
instruction sets. E.g. with a math co-processor a CISC CPU can pipelinemathematical computations
Some use of pipelining in CISC CPUs, but less effective due to
longer instructions & more varied instruction lengths
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Simultaneous Multithreading
A superscalar processor
executes more than one
instruction during a clock cycle by
simultaneously dispatching
multiple instructions to redundant
functional units on the processor.Each functional unit is not a
separate CPU core but an
execution resource within a single
CPU such as an arithmetic logic
unit, a bit shifter, etc.
12
(IF = Instruction Fetch,
ID = Instruction Decode,
EX = Execute,MEM = Memory access,
WB = Register write back,
i= Instruction number,
t= Clock cycle [i.e., time])
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RISC EPIC
The RISC processor design has evolved into a concept
called Explicitly Parallel Instruction Computing
(EPIC)
Created as joint project by Intel and Hewlett-Packard (HP)
Enables the processor to handle massive numbers of
operations simultaneously by implementing large storage areas
and executing parallel instruction sets
Chip can predict and speculate which operations are likely
Can support up to 256 64-bit registers Reduces or eliminates bottlenecks at the processor
Intels Itanium chip
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RISC-based EPIC processors
(continued)
Can build three instructions into one word
A wordis like a single communication with the
processor
CISC and traditional RISC use one instruction perword
EPIC instructions can be combined into instruction
groups, consisting of multiple words It attempts to execute all of the instructions in one group at the
same time
Thus, making the RISC-based EPIC processor
much faster than CISC and traditional RISC chips
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Speed
Internal clock speedis the most obvious indicator
clock provides this to make sure that all the chips know what toexpect at what time
tells you how many clock pulses, or ticks, are available per second
Externalclock speed CPUs also must be able to communicate with the other chips in the
computer
lower clock speed to communicate with the rest of the computer
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Cache
Since the internal clock of a CPU is faster than the
external clock the CPU would have to wait on
information to arrive from other parts of the
computer Most modern CPUs have cache memory built into
the chip This memory is extremely fast and typically runs at the same
speed as the processor Cache memory is referred to as level 1 (L1) cache
Some CPUs have two or more levels of cache memory, called
level 2 (L2) cache
Normally runs at the same speed as the external CPU clock
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Cache
In many cases, up to 90% of data the CPU needs to
transfer to and from memory is present in the L1, L2/L3
cache
Cache controllerpredicts what data will be neededand makes the data available in cache before it is
needed
Intelligent, fast cache controllers and large amounts of
L1, L2, and L3 help increase the speed of a CPU
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Main memory is 5-10 times slower than CPU, so as CPU
accesses memory, delays occur
Solution: Add faster (more expensive) memory
onto CPU (L1, small amount, fast and expensive)
between CPU and Main Memory (L2, larger amount)
Leads to cache replacement algorithms, read ahead algorithms
performed by the cache controller
L2 Cache
14 MB
Main
Memory
Direct Access
StorageCPU
L1 Cache
128 KB
CPUMain
MemoryDirect Access
Storage
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Address Bus
Address Businternal communications pathway
that specifies the source and target addresses for
memory reads and writes
Typically runs at the external clock speed of the CPU Width of the address is the number of bits that can be used to
address memory
Wider bus means the computer can address more memory and
store more data
Older PCs use a 32-bit address bus Allows them to address 4 billion (4 GB) memory addresses
Many newer processors use a 64-bit address bus
Allows them to address 16 terabytes (TB) of memory
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Data Bus
The data bus allows computer components, such
as CPU, display adapter, and main memory, to
share information
The number of bits in the data bus indicates howmany bits of data can be transferred from memory
to the CPU in one clock tick A CPU with an external clock speed of 1 GHz and a 64-bit data
bus could transfer as much 8 GB per second
A CPU with a 64-bit data bus typically can perform
operations on 64 bits of data at a time
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Control Bus
Information is transported on the control bus to
keep the CPU informed about the status of
resources and devices connected to the computer
Memory read and write status is transported on this
bus, as well as interrupt requests Interrupt request (IRQ)a request to the processor to
interrupt whatever it is doing to take care of a process, which
in turn might be interrupted by another process
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Popular CISC PC Processors
Intel16 /32 / 64 bit CISC, began with 8088 in
original PC and most popular today, even in Apple
and SUN
AMDdirectly compete with Intel CISC
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Popular PC Processors
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Popular PC Processors
Multicore Intel CPUs
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What are the Trends in PC Processors?
Bus sizes? Address bus, Data bus, Control bus
Internal & external Clock speeds? Differences in speeds?
Cache Levels, size, location
# of Cores?
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Popular RISC based Processors
Motorola 68000 seriesobsolete 32 bit CISC inolder MACs, others
SPARCScalable Processor Architecture A RISC processor designed by Sun Microsystems (now Oracle)
SPARC T3 is the current version of the SPARC processor
A 64-bit chip with 64-bit address and data buses
Alpha64 bit RISC chip developed by DEC
PowerPC32 & 64 bit RISC chips, developed
jointly by IBM, Motorola, and Apple Computer
Intel Itanium
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Intel Itanium
The Intel Itanium processor is a significantdeparture from previous Intel processors in two
aspects:
built on the RISC-based EPIC architecture and it is a 64-bit
chip
intended for very large-scale operations that match powerful
mainframes
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Itanium Sales Forecasts
Never really tookoff as projected
Windows/red Hat
discontinuing
support for
itanium
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CPU Market Shares
CISC based Intel & AMD dominate in # of units
RISCbased and EPIC much smaller share, but
tend to be more prevalent in mid-range servers
RISC based ARM (Advanced RISC Machine)
processors dominate the embedded device/cell
phone market
And are used in the Raspberry Pi
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Chapter Summary
Hardware and operating systems are interrelated because in manyways they grew up together. Processor hardware improvements
have marched steadily from the early 8088 chip to the modern 64-
bit multicore processors. Operating systems paralleled these
changes to take advantage of the capabilities at each stage of
development. The early computer operating systems were well suited to the early
processors. As processors became faster and more advanced, so
did operating systems.
Today, 64-bit processors provide a foundation for contemporary
Windows, Mac OS X and Unix/Linux operating systems to takeadvantage of their high-speed networking and multimedia
capabilities. Multicore processors bring greater capabilities and
functionality to server operating systems.
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