On behalf of IPHC-Strasbourg group (CNRS & Universit© de Strasbourg)

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14th ICATPP Conference, 23-27 September 2013. Development of CMOS Pixel sensors (CPS) for vertex detectors in present and future collider experiments. Auguste Besson. On behalf of IPHC-Strasbourg group (CNRS & Université de Strasbourg). CMOS pixels sensors - PowerPoint PPT Presentation

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  • Development of CMOS Pixel sensors (CPS) for vertex detectors in present and future collider experimentsOn behalf of IPHC-Strasbourg group (CNRS & Universit de Strasbourg)Auguste Besson14th ICATPP Conference, 23-27 September 2013 CMOS pixels sensors Main features and state of the art STAR PXL detector ILD VTX detector Toward new applications 0.18 m technology ALICE ITS upgrade Lab & beam test results Summary

    Auguste Besson

  • CMOS pixel sensor (CPS) for charged particle detectionMain featuresMonolithic, p-type SiSignal created in low doped thin epitaxial layer ~10-20 m~ 80 e- /m total signal ~ O(1000 e-)Thermal diffusion of e-Limited depleted regionInterface highly P-doped region: reflection on boundaries Charge collection: N-Well diodesCharge sharing resolutionContinuous charge collectionNo dead timeMain AvantagesGranularityPixel pitch down to 10 x 10 m2 spatial resolution down to ~ 1 m)Material budgetSensing part ~ 10-20 m whole sensor routinely thinned down to 50 mSignal processing integrated in the sensorCompacity, flexibility, data fluxFlexible running conditionsFrom 0C up to 30-40C if necessaryLow power dissipation (~ 150-250 mW/cm2) material budgetRadiation tolerance: >~100s kRad and O(1012 neq) f(T,pitch)Industrial mass productionAdvantages on costs, yields, fast evolution of the technology, Possible frequent submissionsMain limitationIndustry adresses applications far from HEP experiments concernsDifferent optimisations on the parameters on the technologiesRecently: new accessible processes:Smaller feature size, adapted epitaxial layerOpen the door for new applications

    Auguste Besson

  • State of the art (1)IPHC-Strasbourg and collab.CPS developped since ~ 1999Typical performances in AMS 0.35 m technologyDetection efficiency 99.9% with fake rate ~ 10-5Typical spatial resolution (20 m pitch) : ~1.5 m (analog output)~3.5 m (digital output)

    Read-out architecture with digital outputIn pixel preamplification and CDSColumn parallel rolling shutter read-outContinuous read-outIntegration time = #rows x row r.o. time (100ns)End-of-columns discriminatorsData sparsification (0-suppression)enhances r.o. speed with preserving material budget, granularity and power comsumption

    Analog outputDigital output

    Auguste Besson

  • State of the art (2): current applicationsEUDET pixel telescopeBeam telescope (FP6 project)6 x Mimosa-26 planes (// r.o. and dig output)Successfully operating since 2008STAR PXL detectorFirst vertex detector equipped with CPS2 layers = 40 ladders x 10 sensorsFirst sectors (3/10) installed May 2013Commissioning completedEnd of construction under wayPrototype: Mimosa-28 (Ultimate)AMS 0.35 m techno with high resisitivity epitaxial layer960 x 928 pixels, 20.7 m pitch 3.8 cm2In pixel CDS & ampli, collumn parallel read-outEnd of column discri. and binary charge encodingOn chip zero suppression

    Auguste Besson

  • Mimosa-28 (=Ultimate) performancesOperating conditionsJTAG + 160 MHzTemperature35CRead-out time = 200 sSuited to 106 part/cm2/sPower comsumption150 mW/cm2

    PerformancesNoise ~ 15 e- ENC @ 35CEff vs fake rateSpatial resolution charge sharingsp ~ 3.5 mRadiation tolerance3.1012neq/cm2 + 150 kRad @ 35 C

    reached performances meets specifications

    Auguste Besson

  • CPS and vertex detector optimisation: squaring the circleVertex detector design and specificationsPhysics performancesSpatial resolutionMaterial budget multiple scatteringExperimental environment constraintsRadiation hardness (ionising and non ion. rad.)Occupancy Read-out speedPower dissipation cooling ?Other parametersCosts, fabrication reliability and flexibilityMechanical integrationGeometryAlignment issuesInterdependance of these parameterse.g. lower radius of inner layerBetter i.p. but larger occupancy, higher rad.Needs higher read-out speed and/or granularity power dissipation

    CPS presents an attractive trade off with respect to all these parameters

    Auguste Besson

  • An example of vertex detector optimisation: ILD @ ILCBaseline: (cf. ILC - Detector Baseline Document)Spatial resolution/material budget

    Occupancy 1st layer: ~ 5 part/cm2/BX few % occupancy maxRadiations: O(100 krad) et O(1x1011 neq (1MeV)) / yearPower dissipation: 600W/12W (Power cycling, ~3% duty cycle)Proposed geometry:3 x double sidded laddersOptimize material budget / alignment.2 designs:Double sidded inner ladders :Priority to r.o. speed & spatial resolution2 faces: resolution / speed (elongated pixels)Pitch 16x16m2/ 16x64m2 + binary charge encodingtread-out ~ 50s/10s ; res ~ 3 m/6m2012: Mimosa-30 prototype (AMS 0.35 m) with 2 sided read-outOuter ladders: power dissipationMinimize Pdiss while keeping good spatial resoutionPitch ~ 35x35 m2 + ADC 3-4 bitstread-out ~ 100 s2012: Mimosa-31 prototype (AMS 0.35 m) with 4-bit ADC

    Auguste Besson

  • Toward new applications

    Auguste Besson

  • Upgrade for more demanding applicationsCPS are also considered by forthcoming projectsCBM @ FAIR (>2016): baselineILD @ ILC@ 500 GeV: TDR optionALICE @ LHC: baseline for ITS upgrade

    ILC motivationsRobustness with respect to predicted beam background occupancyCapabilities to stand the increased occupancy @ 1 TeV (x3-5)Stand alone tracking capabilities (low momentum tracks)How to improve read-out speed ?Elongated pixels (+staggered pixels)Less row per columnAllow in pixel discriminator r.o 2 x fasterMore parrallelisation2 or 4 rows read out simutaneously r.o 2-4 x fasterSub arrays read out in // r.o 2-4 x fasterOnly possible in smaller feature size process (0.18 m) see next slide higher particles rates

    Auguste Besson

  • Evolving to an optimal process: Tower-Jazz 0.18 mCMOS 0.35m process does not allow to fully exploit the potential of CPSMain limitations of 0.35m:Feature size in pixel circuitry, r.o. speed, power comsumption, radiation hardnessNumber of metal layers in pixel circuitry, r.o. speed, insensitive areaClock frequency data outputEpitaxial layer flexibility: (thickness and resistivity) Charge collection/sharingTower-Jazz 0.18 mSmaller feature size process Stitching multi chips slabs (yield ?)6 metal layers in pixel discri.Deep P-well small pitch in pixel discri.higher epitaxial resistivity (1-6 k.cm), epi thickness 18-40 mEnhances signal Higher read-out speed, higher radiation tolerance Faster and smarter pixels

    Auguste Besson

  • Validation of the 0.18m technology roadmapGoal: ALICE ITS upgrade (cf. TDR draft) scheduled for 2017-18 LHC shutdownAddionnal L0(22mm) + replacement of inner layersscheduled for 2017-18 LHC long shutdown(See talks by Beol and Bufalino) 0.25-1 MRad + 0.3-1x1013neq/cm2Chip sensitive area 1x3 cm2STEP 1 (2012): First prototypes Validation of MIP detection performancesSTEP 2 (2013):

    STEP 3 (2014-15): 2 strategies

    Read-out architecturePixels architectureSparsificationCharge encodingEngineering run Tower 0.18 mMimosa-22THRA1/A2 (1l)Mimosa-22THRB (2l)SUZE-02Noise: Mimosa-32N1/N2Optimisation Mimosa-32FEEPixels/diodes dim.: Mimosa-34AROM-0 (1bit)MIMADC (3bits)ASTRALMISTRAL Inner layers 0.3% X0 Spatial resolution ~ 4 m Read-out speed ~ 10-30 s Col. // read-out with in pixel ampli. Simultaneaous 2 rows encoding (x2 faster) Read-out speed ~ 30 s In pixel discri & 2/4-row encoding 2-4 x faster than M22THR r.o. speed ~ 10-20 s Pdiss ~< 150-200 mW / cm2

    Auguste Besson

  • Validation of the 0.18m technology roadmapGoal: ALICE ITS upgrade (cf. TDR draft) scheduled for 2017-18 LHC shutdownAddionnal L0(22mm) + replacement of inner layersscheduled for 2017-18 LHC long shutdown(See talks by Beol and Bufalino) 0.25-1 MRad + 0.3-1x1013neq/cm2Chip sensitive area 1x3 cm2STEP 1 (2012): First prototypes Validation of MIP detection performancesSTEP 2 (2013):

    STEP 3 (2014-15): 2 strategies

    Read-out architecturePixels architectureSparsificationCharge encodingEngineering run Tower 0.18 mMimosa-22THRA1/A2 (1l)Mimosa-22THRB (2l)SUZE-02Noise: Mimosa-32N1/N2Optimisation Mimosa-32FEEPixels/diodes dim.: Mimosa-34AROM-0 (1bit)MIMADC (3bits)(next slides)(next slides)ASTRALMISTRAL Inner layers 0.3% X0 Spatial resolution ~ 4 m Read-out speed ~ 10-30 s(next slides) Col. // read-out with in pixel ampli. Simultaneaous 2 rows encoding (x2 faster) Read-out speed ~ 10-30 s In pixel discri & 2/4-row encoding 2-4 x faster than M22THR Pdiss ~< 150-200 mW / cm2

    Auguste Besson

  • STEP 1: Tower-Jazz 0.18 m2012: First prototypes (M32 & M32ter)Validation of MIP detection performances (120 GeV/c Pions @ CERN)Charge collection properties, pitch, in pixel amplification, CDS, etc.Beam test: SNR & det.eff. 20 m pitch (1MRad, 1013 neq/cm2 @ 30 C)

    Remaining room for improvementSuspected RTS noise

    Auguste Besson

  • STEP 1: Resolution with digital outputResolution obtained from analog data + simulated binary charge encodingSpatial resolution vs discriminator threshold scan AMS 0.35 (Mi 28) 20.7x20.7 m2 pitchTHR 0.18 (Mi 32) 20x20 m2 pitchTHR 0.18 (Mi 32) 20x40 m2 pitch

    Auguste Besson

  • STEP2: Read-out architecture M22 THRA1 resultsMIMOSA-22THRA1 design (adapted from M28-STAR)128 col. x 320 rows (22x22/33 m2) + end of col. discri8 col. with analog output for testsRolling shutter (single row) read-out tr.o. ~ 50 sRTS noise optimisation: enlarged preamp T gate4 different submatricesStudy RTSDifferent epitaxial layers 18m(HR18), 20m(HR20), etc.

    Beam Test (5GeV e- @ DESY)Det.Eff. ~ 99.5 % with fake 10-5 (lab test)Few 10-3 inefficiency may come from track-hit mismatch (under investigation)

    Auguste Besson

  • M22 THRA1 results : digital part

    Fixing the Noise tailEnlarge pre-amp transistor gate dimensionRight: L/W = 0.18/1 m TailLeft: L/W = 0.36/1 mTN ~ 17 e-

    Efficiency