NVL-02.14GSps Four-Bit Noninterleaved Data Converter Pair in 90 Nm CMOS With Built-In Eye Diagram...
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A 65 nm Low-Power Ada ptive-Coupling Redundant Flip-Flop AIM: The main aim of the project is to design “ A 65 nm Low-Power Adaptive- Coupling Redundant Flip-Flop”. (A!"RAC"# A low-power redundant flip-flop to be operated with high reliability over 1 GHz cl oc fr e!ue nc y ba se d on th e low- powe r "A#$$% an d th e hi gh ly -r el ia bl e "&#'()% fl ip -f lo ps * +ts power dissi pation is almos t e! uivalen t to the tr ansmission-gat e $$ at 1, da ta acti vi ty wh il e pa yi ng . area pe na lties* /0pe ri me nt s by -par ti cl e and neut ron ir radi at ion reve al it s hi ghly-r el ia bl e perations with no error at 1*2 3 and 1 GHz* 4e measured five different process corner chips by irradiation* 5oft error rates are almost e!uivalent in these corner chips* Propo$ed Ar%&ite%ture: Advantage: 67-nm chip including the low-power redundant $$ called &#'()-A#$$ by using low- power A#$$ and the hi ghly-reliable &#'() $$ * The A'8 pr oduc t of &#'()-A#$$ is smaller than that of the original &#'() when data activity is below 9,* At , data activity: the A'8 product of &#'()-A#$$ is 2 larger than that of the TG$$* . BLOCK DIAGRAM:
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Transcript of NVL-02.14GSps Four-Bit Noninterleaved Data Converter Pair in 90 Nm CMOS With Built-In Eye Diagram...
A 65 nm Low-Power Adaptive-Coupling Redundant Flip-Flop
A 65 nm Low-Power Adaptive-Coupling Redundant Flip-Flop
AIM:
The main aim of the project is to design A 65 nm Low-Power Adaptive-Coupling Redundant Flip-Flop.
(ABSTRACT)
A low-power redundant flip-flop to be operated with high reliability over 1 GHz clock frequency based on the low-power (ACFF) and the highly-reliable (BCDMR) flip-flops. Its power dissipation is almost equivalent to the transmission-gate FF at 10% data activity while paying 3 area penalties. Experiments by -particle and neutron irradiation reveal its highly-reliable Operations with no error at 1.2 V and 1 GHz. We measured five different process corner chips by irradiation. Soft error rates are almost equivalent in these corner chips.
Proposed Architecture:
Advantage:
65-nm chip including the low-power redundant FF called BCDMR-ACFF by using low-power ACFF and the highly-reliable BCDMR FF. The ADP product of BCDMR-ACFF is smaller than that of the original BCDMR when data activity is below 40%. At 0% data activity, the ADP product of BCDMR-ACFF is 2 larger than that of the TGFF.
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BLOCK DIAGRAM:
Schematic diagram of BCDMR-ACFF
Schematic diagram of ACFF.TOOLS: hspice_vA-2008.03, t-spice
REFERENCE:
[1] D. Krueger, E. Francom, and J. Langsdorf, Circuit design for voltage scaling and ser immunity on a quad-core itanium processor, in Proc.ISSCC, Feb. 2008, pp. 9495.
[2] M. Zhang, S. Mitra, T. M. Mak, N. Seifert, N. J. Wang, Q. Shi, K. S. Kim, N. R. Shanbhag, and S. J. Patel, Sequential element design with built-in soft error resilience, IEEE Trans. VLSI Sys., vol. 14, no. 12, pp. 13681378, Dec. 2006.
[3] B. I. Matush, T. J. Mozdzen, L. T. Clark, and J. E. Knudsen, Areaefficient
temporally hardened by design flip-flop circuits, IEEE Trans. Nucl. Sci., vol. 57, no. 6, pp. 35883595, Dec. 2010.[4] N. Seifert, P. Slankard, M. Kirsch, B. Narasimham, V. Zia, C. Brookreson, A. Vo, S. Mitra, B. Gill, and J. Maiz, Radiation-induced soft error rates of advanced CMOS bulk devices, in Proc. IRPS, Mar. 2006, pp. 217225.
[5] J. Furuta, C. Hamanaka, K. Kobayashi, and H. Onodera, A 65 nm bitable cross-coupled dual modular redundancy flip-flop capable of protecting soft errors on the c-element, in Proc. VLSI Circuits Symp., Jun. 2010, pp. 123124.
