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NVL-02.14GSps Four-Bit Noninterleaved Data Converter Pair in 90 Nm CMOS With Built-In Eye Diagram Testability

NVL-03.Power Efficient Class AB Op-Amps With High And

NVL-04.an Optimized Modified Booth Recoder for Efficient Design of the Add-Multiply Operator

NVL-06.Carbon Nanotubes Blowing New Life Into NP Dynamic

NVL-07.Thwarting Scan-Based Attacks on Secure-ICs

NVL-08.Novel Class of Energy-Efficient Very High-Speed

NVL 09.Low Power Pulse Triggered Flip Flop Design

NVL-11.Analysis and Design of a Low-Voltage Low-Power

NVL-12.Constant Delay Logic Style

NVL-14.Minimizing Energy of Integer Unit by Higher Voltage

NVL-13.Low-Power Dual Dynamic Node Pulsed Hybrid Flip-Flop Featuring Efficient Embedded Logic

NVL-26.Design of Sequential Elements for Low Power

Nvl-24.Four Bit Cmos Full Adder in Submicron Technology With Low Leakage and Ground Bounce Noise Reduction

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