NSERC CREATE Si-EPIC Program...Final GDS Students submit: Final report Chip Layout – 2009-10 (23...

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Si-EPIC 1 NSERC CREATE Si-EPIC Program http://www.SiEPIC.ubc.ca September 11, 2012 Lukas Chrostowski Si-EPIC Image: Wei Shi

Transcript of NSERC CREATE Si-EPIC Program...Final GDS Students submit: Final report Chip Layout – 2009-10 (23...

Page 1: NSERC CREATE Si-EPIC Program...Final GDS Students submit: Final report Chip Layout – 2009-10 (23 designs, MPW) 5 12 mm 7 mm One student design 2008-2009 Course – Chips Received

Si-EPIC 1

NSERC CREATESi-EPIC Programhttp://www.SiEPIC.ubc.ca

September 11, 2012Lukas Chrostowski

Si-EPIC

Image: Wei Shi

Page 2: NSERC CREATE Si-EPIC Program...Final GDS Students submit: Final report Chip Layout – 2009-10 (23 designs, MPW) 5 12 mm 7 mm One student design 2008-2009 Course – Chips Received

Si-EPIC

Outline – Si-EPIC Training Program� History: CMC-UBC Silicon Photonics workshops, 2008+� NSERC CREATE grant

� Researchers, industry

� Si-EPIC training workshops� Passive Silicon Nanophotonics� Active Silicon Photonics� CMOS, Silicon for Photonics� Systems, Packaging, & Integration

� Design tools, Si-EPIC component Library� Foundry fabrication� Experimental facilities� Research� Si-EPIC Annual Research Review meeting

� June 2012 @ McGill

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Page 3: NSERC CREATE Si-EPIC Program...Final GDS Students submit: Final report Chip Layout – 2009-10 (23 designs, MPW) 5 12 mm 7 mm One student design 2008-2009 Course – Chips Received

� CMC-UBC Silicon Nanophotonics Workshop & Course � Started in 2008 – 5th offering in June 2012� 90+ students from across Canada trained to-date from 18+ universities,

industry (e.g., TeraXion), government lab� An exciting opportunity for students to design, have fabricated, and test

silicon photonic devices; complete cycle < 1 year. � Based on IMEC passive silicon photonics. Possible to fabricate photonic

crystals, waveguides, fiber coupling, ring resonators, filters, etc.

Silicon Photonics Workshops

3

2009

2010

2011

2012

Page 4: NSERC CREATE Si-EPIC Program...Final GDS Students submit: Final report Chip Layout – 2009-10 (23 designs, MPW) 5 12 mm 7 mm One student design 2008-2009 Course – Chips Received

UBC EECE 484 – 2011

Workshop schedule – Design cycle

4

Design & Modelling

Mask Layout

Fabrication(Foundry)

Test

Workshop~1 week, June-July

500 nm5 μm

400 nm 500 nm290 nm

Input

Drop

1476.85 1476.95 1477.05 1477.15−20

−18

−16

−14

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−10

−8

−6

−4

−2

0

Wavelength (nm)

Tra

nsm

issi

on (

dB)

~15 pm

Q: ~100,000

Students submit:� Proposal� Design doc

Students submit:� Draft GDS� Final GDS

Students submit:� Final report

Page 5: NSERC CREATE Si-EPIC Program...Final GDS Students submit: Final report Chip Layout – 2009-10 (23 designs, MPW) 5 12 mm 7 mm One student design 2008-2009 Course – Chips Received

Chip Layout – 2009-10 (23 designs, MPW)

5

12 mm

7 mm

One student design

Page 6: NSERC CREATE Si-EPIC Program...Final GDS Students submit: Final report Chip Layout – 2009-10 (23 designs, MPW) 5 12 mm 7 mm One student design 2008-2009 Course – Chips Received

2008-2009 Course – Chips

� Received wafer with 186 die

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Page 7: NSERC CREATE Si-EPIC Program...Final GDS Students submit: Final report Chip Layout – 2009-10 (23 designs, MPW) 5 12 mm 7 mm One student design 2008-2009 Course – Chips Received

Example student projectsStudent publications / conference proceedings:

• A. D. Simard, Y. Painchaud, S. LaRochelle, “Integrated Bragg Gratings in Curved Waveguides,” IEEE Photonics Society Annual Meeting, paper ThU3, Denver, USA, November 2010.• Nicolas Rouger, Lukas Chrostowski, Raha Vafaei, "Temperature Effects On Silicon-On-Insulator (SOI) Racetrack Resonators: a Coupled Analytic and 2D Finite Difference

Approach", Journal of Lightwave Technology, vol. 28, issue 9, pp. 1380--1391, 05/2010• Nicolas Rouger, Lukas Chrostowski, "Simulation of coupling between parallel SOI nanowaveguides and its dependence on temperature", 2009 IEEE/LEOS International Conference

on Optical MEMS and Nanophotonics, pp. 103--104 , 16/08/2009• Robi Boeck, Nicolas A. F. Jaeger, Lukas Chrostowski, "Experimental Demonstration of the Vernier Effect using Series-Coupled Racetrack Resonators", 2010 International

Conference on Optical MEMS & Nanophotonics, 09/08/2010 (accepted)• Wei Shi, Raha Vafaei, Miguel Angel Guillen Torres, Nicolas A. F. Jaeger, Lukas Chrostowski, "Ring-Resonator Reflector with a Waveguide Crossing", 2010 International Conference

on Optical MEMS & Nanophotonics, 09/08/2010• Xu Wang, Wei Shi, Raha Vafaei, Nicolas A. F. Jaeger, Lukas Chrostowski, "Silicon-on-Insulator Bragg Gratings Fabricated by Deep UV Lithography", IEEE Asia Communications &

Photonics Conference, 8/12/2010• Jonas Flueckiger, Samantha M. Grist, Gurpal Bisra, Lukas Chrostowski, Karen C. Cheung, "Cascaded silicon-on-insulator microring resonators for the detection of biomolecules in

PDMS microfluidic channels", SPIE Microfluidics, BioMEMS, and Medical Microsystems IX, 01/2011• Robi Boeck, Nicolas A. F. Jaeger, Nicolas Rouger, Lukas Chrostowski, "Series-Coupled Silicon Racetrack Resonators and the Vernier Effect: Theory and Measurement", Optics

Express, vol. 18, issue 24, pp. 7, 11/2010.• Wei Shi, Raha Vafaei, Miguel Angel Guillen Torres, Nicolas A. F. Jaeger, Lukas Chrostowski, "Design and Characterization of Microring Reflectors with a Waveguide Crossing",

Optics Letters, vol. 35, issue 17, pp. 2901-2903, 09/2010• Xu Wang, Wei Shi, Raha Vafaei, Nicolas A. F. Jaeger, Lukas Chrostowski, "Uniform and Sampled Bragg Gratings in SOI Strip Waveguides with Sidewall Corrugations", IEEE

Photonics Technology Letters (2011)• Han Yun, Wei Shi, Xu Wang, Lukas Chrostowski, Nicolas A. F. Jaeger, "Design of a Microring Reflector with a Dumbbell Structure", The 15th Canadian Semiconductor Science and

Technology Conference , 15/08/2011.• Xu Wang, Wei Shi, Samantha Grist, Han Yun, Nicolas A. F. Jaeger, Lukas Chrostowski, "Narrow-Band Transmission Filter using Phase-Shifted Bragg Gratings in SOI", IEEE Photonics

Conference, pp. ThZ1, 10/2011.• Wei Shi, Xu Wang, Wen Zhang, Lukas Chrostowski, Nicolas A. F. Jaeger, "Contradiretional couplers in silicon-on-insulator rib waveguides", Optics Letters, (In Press) 2011.• Guillén-Torres, Miguel A., Chrostowski, Lukas, Cretu, Edmond, Jaeger, Nicolas A. F., "Ring Resonator Gyroscope: System Level Analysis and Parameter Optimization", Canadian

Semiconductor Science and Technology Conference, Vancouver, B.C., Canada., pp. MPA1, 15/08/2011.• C. Lin, L. Chrostowski, N.A.F. Jaeger, "Embedded Ring Resonator", Canadian Semiconductor Science and Technology Conference, 08/15/2011.• Gad, M., Ackert, J., Yevick, D., Chrostowski, L., Jessop, P., , "Ring Resonator Wavelength Division Multiplexing Interleaver", IEEE Journal of Lightwave Technology, vol. 29, issue 14,

pp. 2102–9, 07/2011.• Ackert, J. J., Doylend, J. K., Logan, D. F., Jessop, P. E., Vafaei, R., Chrostowski, L., Knights, A. P., "Defect-mediated resonance shift of silicon-on-insulator racetrack resonators", Opt.

Express, vol. 19, no. 13: OSA, pp. 11969--11976, 06/2011.• Jonas Flueckiger, Samantha M. Grist, Eric Ouellet, Lukas Chrostowski, Karen C. Cheung, "Label-Free Biosensing Using Cascaded Silicon-on-Insulator Micro-Racetrack Resonators

Integrated With PDMS Microfluidic Channels", The 15th International Conference on Miniaturized Systems for Chemistry and Life Sciences, Seattle, Washington, USA, 10/2011. • Yonathan Dattner, O. Yadid-Pecht, Analysis of the Effective Refractive Index of Silicon Waveguides Through the Constructive and Destructive Interference in a Mach–Zehnder

Interferometer, IEEE Photonics Journal, Vol 3, Issue 6, pp. 1123-1132, Dec. 2011• Lukas Chrostowski, Samantha Grist, Jonas Flueckiger, Wei Shi, Xu Wang, Eric Ouellet, Han Yun, Mitch Webb, Ben Nie, Zhen Liang, Karen C. Cheung, Shon A. Schmidt, Daniel M.

Ratner, Nicolas A. F. Jaeger,"Silicon photonic resonator sensors and devices", Proceedings of SPIE Volume 8236; Laser Resonators, Microresonators, and Beam Control XIV, 01/2012.

• Wei Shi, Xu Wang, Wen Zhang, Han Yun, Charlie Lin, Lukas Chrostowski, Nicolas A. F. Jaeger, "Grating-coupled silicon microring resonators", Applied Physics Letters, 03/2012.• Wei Shi, Xu Wang, Han Yun, Wen Zhang, Nicolas Jaeger, Lukas Chrostowski, "Integrated silicon contradirectional couplers: modeling and experiment", SPIE Photonics Europe,

Brussels, Belgium, pp. 8424-82, 04/2012. • Wei Shi, Xu Wang, Han Yun, Wen Zhang, Lukas Chrostowski, Nicolas Jaeger, "Add-drop filters in silicon grating-assisted asymmetric couplers ", OFC/NFOEC, Los Angeles, US, pp.

OTh3D.3 , 04/03/2012.• Wei Shi, Xu Wang, Wen Zhang, Han Yun, Nicolas A. F. Jaeger, Lukas Chrostowski, "Integrated microring add-drop filters with contradirectional couplers ", CLEO (Conference on

Lasers and Electro-Optics) 2012, San Jose, US, pp. JW4A.91 , 05/2012. • Wei Shi, Han Yun, Ting Kai Chang, Wen Zhang, Charlie Lin, Nicolas A. F. Jaeger, Lukas Chrostowski, "Differential measurement of transmission losses of integrated optical

components using waveguide ring resonators", Photonics North, Montreal, Canada, 06/06/2012.

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Vernier Effect – Robi Boeck (2009-10)

� Two coupled rings with different radii – provide a much larger “free spectral range”

� Experimental demonstration� Robert Boeck, Nicolas A. F. Jaeger, Lukas Chrostowski, "Experimental Demonstration of the Vernier Effect using Series-Coupled Racetrack

Resonators", 2010 International Conference on Optical MEMS & Nanophotonics, 09/08/2010.

8

1500 1510 1520 1530 1540 1550

�65

�60

�55

�50

�45

�40

�35

�30

�25

Wavelength (nm)

Opt

ical

Pow

er (

dBm

)

10 um

1 um

Lc

R1

50 nm

50 nm

R2

k1 k3k2

35 nm

Page 9: NSERC CREATE Si-EPIC Program...Final GDS Students submit: Final report Chip Layout – 2009-10 (23 designs, MPW) 5 12 mm 7 mm One student design 2008-2009 Course – Chips Received

Microfluidics – Rings + PDMS

� Cascaded silicon-on-insulator microring resonators for the detection of biomolecules in PDMS microfluidic channels

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Jonas Flueckiger (2009), Samantha Grist (2010)

Page 10: NSERC CREATE Si-EPIC Program...Final GDS Students submit: Final report Chip Layout – 2009-10 (23 designs, MPW) 5 12 mm 7 mm One student design 2008-2009 Course – Chips Received

Waveguide Bragg Gratings – Xu Wang (2009-)

� Bragg gratings – strip, rib waveguides

� Phase shifted gratings

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1470 1475 1480 14850

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

Wavelength (nm)T

rans

mis

sion

~10 nm

1460 1480 1500 1520 1540 1560 1580−40

−35

−30

−25

−20

−15

Wavelength (nm)

Tra

nsm

issi

on (

dB)

Single-modeBW: 0.5 – 35 nmHighest ER: 30 dB

Page 11: NSERC CREATE Si-EPIC Program...Final GDS Students submit: Final report Chip Layout – 2009-10 (23 designs, MPW) 5 12 mm 7 mm One student design 2008-2009 Course – Chips Received

Contra-directional Grating-Assisted Couplers – Wei Shi (2010-)

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1520 1540 1560 1580 1600 1620−30

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−5

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Wavelength (nm)

Dri

p−po

rt r

espo

nse,

dB

20 nm 13 nm

Input Win

Drop 1 W1

W2Drop 2

Drop 3

Drop 4

W3

W4

Through

1460 1490 1520 1550 1580 1610 1640−25

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−15

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−5

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Wavelength, nm

Nor

mal

ized

Tra

n sm

issi

on, d

B

λD

6.5 nm

Λ/2

DropInput

W. Shi, Group IV Photonics, WA7, 2012

Page 12: NSERC CREATE Si-EPIC Program...Final GDS Students submit: Final report Chip Layout – 2009-10 (23 designs, MPW) 5 12 mm 7 mm One student design 2008-2009 Course – Chips Received

Si-EPIC

Outline – Si-EPIC Training Program� History: CMC-UBC Silicon Photonics workshops, 2008+� NSERC CREATE grant

� Researchers, industry

� Si-EPIC training workshops� Passive Silicon Nanophotonics� Active Silicon Photonics� CMOS, Silicon for Photonics� Systems, Packaging, & Integration

� Design tools, Si-EPIC component Library� Foundry fabrication� Experimental facilities� Research� Si-EPIC Annual Research Review meeting

� June 2012 @ McGill

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Page 13: NSERC CREATE Si-EPIC Program...Final GDS Students submit: Final report Chip Layout – 2009-10 (23 designs, MPW) 5 12 mm 7 mm One student design 2008-2009 Course – Chips Received

Si-EPIC

Si-EPIC Program� NSERC CREATE $1.65M grant

� Matching funding & in-kind from industry & universities

� 6 year training program in silicon photonics� Training from 11+ professors, CMC, and industry seminars� workshops open to all (industry and academia)

� Canada-wide – 5 core universities� Collaborators/contributors welcome

� The key objective of the Si-EPIC CREATE program is to train students to be innovative designers and to enhance their capacity to engage in innovation and commercialization with industry partners. The program has been meticulously designed to provide students a wide range of experience through� Research projects, workshops, industrial internships, professional

development� Research collaboration among trainees and researchers

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Page 14: NSERC CREATE Si-EPIC Program...Final GDS Students submit: Final report Chip Layout – 2009-10 (23 designs, MPW) 5 12 mm 7 mm One student design 2008-2009 Course – Chips Received

Si-EPIC

Si-EPIC Professors –UBC, McGill, McMaster, Ottawa, Sherbrooke

Lukas ChrostowskiProgram Director – Si-EPIC ProgramAssociate Professor, Electrical and Computer EngineeringUniversity of British Columbiahttp://www.ece.ubc.ca/faculty/lukas-chrostowski

Vincent AimezProfessor, Electrical and Computer Engineering University of Sherbrookehttp://www.usherbrooke.ca/gelecinfo/fr/pers/profs/aimv-fr/

Andrew P. Knights Associate Professor, Engineering PhysicsMcMaster Universityhttp://engphys.mcmaster.ca/faculty_staff/faculty/knights/

Wei-Ping HuangProfessor, Electrical and Computer Engineering McMaster Universityhttp://photonsrvr.ece.mcmaster.ca/huang/Home.htm

Jeff F. YoungProfessor, Physics and AstronomyUniversity of British Columbiahttps://www.phas.ubc.ca/users/jeff-young

Nicolas A. F. JaegerProfessor, Electrical and Computer EngineeringUniversity of British Columbiahttp://www.ece.ubc.ca/~nickj/

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Shahriar MirabbasiAssociate Professor, Electrical and Computer EngineerinUniversity of British Columbiahttp://www.ece.ubc.ca/~shahriar/

Odile Liboiron-Ladouceur Assistant Professor, Electrical and Computer EngineeringMcGill Universityhttp://www.photonics.ece.mcgill.ca/Liboiron-Ladouceur/LLadouceur.html

David V. PlantProfessor, Electrical and Computer EngineeringMcGill Universityhttp://www.photonics.ece.mcgill.ca/Plant/Plant.html

Jianping YaoProfessor and University Research Chair in Microwave PUniversity of Ottawahttp://www.site.uottawa.ca/~jpyao/

Robert W. BoydProfessor and Canada Excellence Research Chair, QuanPhysicsUniversity of Ottawahttp://www.quantumphotonics.uottawa.ca/robert-boyd-en

Page 15: NSERC CREATE Si-EPIC Program...Final GDS Students submit: Final report Chip Layout – 2009-10 (23 designs, MPW) 5 12 mm 7 mm One student design 2008-2009 Course – Chips Received

Si-EPIC

Industry, Collaborators� Agencies

� CMC Microsystems: development of design kits, instruction at the workshops, technical support, organizes the workshop-MPW foundry submission, fabrication cost subsidy

� C2MI (Centre de Collaboration MiQro Innovation / MiQro Innovation Collaborative Centre), Bromont, QC: pre-commercialization R&D on packaging the Si-EPIC chips

� National Research Council, Institute for Microstructural Sciences� OpSIS (Optoelectronic Systems Integration in Silicon), University of Delaware

� Industry – internships for SiEPIC scholars� TeraXion Inc.� OneChip Photonics� Apollo Photonics Inc.,� Lumerical Solutions Inc.� Crosslight Software, Inc.� Optelian, Versawave Inc.� PMC Sierra, Inc.� Reflex Photonics Inc� Telus

� Collaborators� Joyce Poon, University of Toronto� Sophie Larochelle, Universite Laval

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Page 16: NSERC CREATE Si-EPIC Program...Final GDS Students submit: Final report Chip Layout – 2009-10 (23 designs, MPW) 5 12 mm 7 mm One student design 2008-2009 Course – Chips Received

Si-EPIC

Students – 2012 SiEPIC Scholars� Kyle Murray

� McMaster University

� David Patel� McGill University

� Meer Nazmus Sakib� McGill University

� Guillaume Beaudin� University of Sherbrooke

� Md Shafiqul Hai� McGill University

� Monireh Moayedi� McGill University

� Quihang Zhong� McGill University

� Haibo Liang� McMaster University

� Jiamin Zheng� McMaster University

� Ahmadreza Farsaei� UBC

� Ellen Schelew� UBC

� Jonas Flueckiger� UBC

� Samantha Grist� UBC

� Valentina Donzella� UBC

� Xu Wang � UBC

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Page 17: NSERC CREATE Si-EPIC Program...Final GDS Students submit: Final report Chip Layout – 2009-10 (23 designs, MPW) 5 12 mm 7 mm One student design 2008-2009 Course – Chips Received

Si-EPIC

Outline – Si-EPIC Training Program� History: CMC-UBC Silicon Photonics workshops, 2008+� NSERC CREATE grant

� Researchers, industry

� Si-EPIC training workshops� Passive Silicon Nanophotonics� Active Silicon Photonics� CMOS, Silicon for Photonics� Systems, Packaging, & Integration

� Design tools, Si-EPIC component Library� Foundry fabrication� Experimental facilities� Research� Si-EPIC Annual Research Review meeting

� June 2012 @ McGill

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Page 18: NSERC CREATE Si-EPIC Program...Final GDS Students submit: Final report Chip Layout – 2009-10 (23 designs, MPW) 5 12 mm 7 mm One student design 2008-2009 Course – Chips Received

Si-EPIC

SiEPIC Workshops

� Si-EPIC program – 4 annual workshops in:� Passive Photonics – July 2012, onwards

� Fibre grating couplers, resonators (rings, disks, waveguide Bragg gratings, photonic crystals), splitters (ybranches, directional couplers), optical filters

� Active Photonics (modulators and detectors) – Fall 2012, onwards� pn, pin junction modulators, detectors

� CMOS Electronics for silicon photonics – Summer 2013, onwards� amplifiers (detector TIA, modulator drivers)

� Systems, Integration, Packaging – Summer 2014, onwards� CMOS+photonic integration (bonding), system-level design and modelling,

packaging?

� Workshops open to all� Industry and academia (18 universities so far!)

� Chrostowski – also involved in OpSIS Workshops� August 2011 – IME process, 8 days� June / July 2012 – IME process, 5 days

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Page 19: NSERC CREATE Si-EPIC Program...Final GDS Students submit: Final report Chip Layout – 2009-10 (23 designs, MPW) 5 12 mm 7 mm One student design 2008-2009 Course – Chips Received

Si-EPIC

2012 Passive Silicon Photonics workshop

� June 26th – July 5th at McGill University� Site visit to C2MI / IBM, Bromont, QC

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Page 20: NSERC CREATE Si-EPIC Program...Final GDS Students submit: Final report Chip Layout – 2009-10 (23 designs, MPW) 5 12 mm 7 mm One student design 2008-2009 Course – Chips Received

Si-EPIC

Schedule

� 6 Year grant: 2012 – 2018� 4 workshops annually (typically in the summer)

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Tasks

Workshops: Silicon Photonics - Passive Silicon Photonics - Active Silicon for Photonics (CMOS electronics) Systems, Integration and Packaging

A M J J A S O N D J F M A M J J A S O N D J F M A M J J A S O N D J F M A M J J A S O N D J F M A M J J A S O N D J F M A M J J A S O N D J F M

Workshop instruction Foundry fabricationStudent design Student experiments

Year 4 - 2015-16 Year 5 - 2016-17 Year 6 - 2017-18Year 1 - 2012-13 Year 2 - 2013-14 Year 3 - 2014-15

Page 21: NSERC CREATE Si-EPIC Program...Final GDS Students submit: Final report Chip Layout – 2009-10 (23 designs, MPW) 5 12 mm 7 mm One student design 2008-2009 Course – Chips Received

Si-EPIC

Outline – Si-EPIC Training Program� History: CMC-UBC Silicon Photonics workshops, 2008+� NSERC CREATE grant

� Researchers, industry

� Si-EPIC training workshops� Passive Silicon Nanophotonics� Active Silicon Photonics� CMOS, Silicon for Photonics� Systems, Packaging, & Integration

� Design tools, Si-EPIC component Library� Foundry fabrication� Experimental facilities� Research� Si-EPIC Annual Research Review meeting

� June 2012 @ McGill

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Page 22: NSERC CREATE Si-EPIC Program...Final GDS Students submit: Final report Chip Layout – 2009-10 (23 designs, MPW) 5 12 mm 7 mm One student design 2008-2009 Course – Chips Received

Si-EPIC

Design tools

� Mentor Graphics – leverage CMOS tools� Schematic Driven Layout� Netlist export for system simulations� Layout using placement from schematic� Interactive / Automated routing� Scripted layout for cell parameterization� Error checking (DRC) – broken waveguides, mismatched waveguides, PDK...� Tiling� Future: Layout Versus Schematic, Integration with system/device modelling

� Lumerical Solutions� Passive & active device simulations� System simulations

� Si-EPIC Component Library – promote design reuse� optical models, device layout, test data

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Page 23: NSERC CREATE Si-EPIC Program...Final GDS Students submit: Final report Chip Layout – 2009-10 (23 designs, MPW) 5 12 mm 7 mm One student design 2008-2009 Course – Chips Received

Si-EPIC

Optical design & modelling

� Silicon photonic � passive components (MODE, FDTD)� active components – modulator, detectors (DEVICE, MODE)� systems (INTERCONNECT)

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Page 24: NSERC CREATE Si-EPIC Program...Final GDS Students submit: Final report Chip Layout – 2009-10 (23 designs, MPW) 5 12 mm 7 mm One student design 2008-2009 Course – Chips Received

Mentor Graphics – Schematic Driven Layout� Side-by-side view of Layout & Schematic

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Page 25: NSERC CREATE Si-EPIC Program...Final GDS Students submit: Final report Chip Layout – 2009-10 (23 designs, MPW) 5 12 mm 7 mm One student design 2008-2009 Course – Chips Received

Mentor Graphics – Interactive Routing� Make netlists, define waveguide paths� Convert paths to polygons with chosen 90º bends (adiabatic)

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Page 26: NSERC CREATE Si-EPIC Program...Final GDS Students submit: Final report Chip Layout – 2009-10 (23 designs, MPW) 5 12 mm 7 mm One student design 2008-2009 Course – Chips Received

Si-EPIC

Outline – Si-EPIC Training Program� History: CMC-UBC Silicon Photonics workshops, 2008+� NSERC CREATE grant

� Researchers, industry

� Si-EPIC training workshops� Passive Silicon Nanophotonics� Active Silicon Photonics� CMOS, Silicon for Photonics� Systems, Packaging, & Integration

� Design tools, Si-EPIC component Library� Foundry fabrication� Experimental facilities� Research� Si-EPIC Annual Research Review meeting

� June 2012 @ McGill

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Page 27: NSERC CREATE Si-EPIC Program...Final GDS Students submit: Final report Chip Layout – 2009-10 (23 designs, MPW) 5 12 mm 7 mm One student design 2008-2009 Course – Chips Received

ePIXfab imec• Passives, grating couplers

OpSIS-IME• Passives• Modulators• Detectors• Edge /

gratingcoupling

OpSIS-BAEOpSIS-Luxtera /Freescale• Photonics+CMOS

100 keV E-Beam Lithography Univ. Washington MFF

Si-EPIC

Foundries

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Λ/2

DropInput

TE

adiabatic taper

Page 28: NSERC CREATE Si-EPIC Program...Final GDS Students submit: Final report Chip Layout – 2009-10 (23 designs, MPW) 5 12 mm 7 mm One student design 2008-2009 Course – Chips Received

Si-EPIC

Active silicon photonics – Phase-shifted contra-directional couplers

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� Gratings: both side-wall and rib� CMOS-photonic technology by BAE systems through OpSIS� 248 nm lithography� PIN junction for electrical tuning� Good agreement with simulation

Wa WbG

p+ p++n+n++

n Contact p Contact

∆Wa

∆Wb

Grating

C1400 nm600 nm 200 nm

110 nm 100 nm

W. Shi, et al, GFP, San Diego: WP2, 2012

Page 29: NSERC CREATE Si-EPIC Program...Final GDS Students submit: Final report Chip Layout – 2009-10 (23 designs, MPW) 5 12 mm 7 mm One student design 2008-2009 Course – Chips Received

Si-EPIC

Active silicon photonics – Phase-shifted contra-directional couplers

28

� Gratings: both side-wall and rib� CMOS-photonic technology by BAE systems through OpSIS� 248 nm lithography� PIN junction for electrical tuning� Good agreement with simulation

Wa WbG

p+ p++n+n++

n Contact p Contact

∆Wa

∆Wb

Grating

C1400 nm600 nm 200 nm

110 nm 100 nm

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Through, Fit

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4λ phase-shift

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W. Shi, et al, GFP, San Diego: WP2, 2012

Page 30: NSERC CREATE Si-EPIC Program...Final GDS Students submit: Final report Chip Layout – 2009-10 (23 designs, MPW) 5 12 mm 7 mm One student design 2008-2009 Course – Chips Received

Si-EPIC

Active silicon photonics – Phase-shifted contra-directional couplers

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108

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Frequency, Hz

Res

pons

e, d

B

RF: −19 dBm, DC: 0.3 mA, 1519.65 nmRF: −19 dBm, DC: 1.0 mA, 1519.25 nm−20 dB/decadeNoise floor

S21

W. Shi, et al, GFP, San Diego: WP2, 2012

1518.4 1518.6 1518.8 1519 1519.2 1519.4 1519.6 1519.8 1520

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Nor

mal

ized

Res

pons

e, d

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0.0mA, 0.0V0.08mA, 0.827V0.15mA, 0.852V0.3mA, 0.883V0.4mA, 0.898V0.6mA, 0.920V0.8mA, 0.938V1.0mA, 0.957V1.5mA, 0.990V

Critical coupling

� Voltage < 1V, efficiency: -0.73 nm/mA� Critical coupling obtained� Small-signal response

� 3 dB bandwidth 90 MHz� Limited by carrier life time

� Improvement� Carrier are uniformly injected into the waveguides; the tuning efficiency may be enhanced by optimizing the overlap of the current density with the longitudinal optical intensity distribution� Reverse-bias

� No carrier life-time limitation� High-speed optical modulator

Page 31: NSERC CREATE Si-EPIC Program...Final GDS Students submit: Final report Chip Layout – 2009-10 (23 designs, MPW) 5 12 mm 7 mm One student design 2008-2009 Course – Chips Received

Si-EPIC

Outline – Si-EPIC Training Program� History: CMC-UBC Silicon Photonics workshops, 2008+� NSERC CREATE grant

� Researchers, industry

� Si-EPIC training workshops� Passive Silicon Nanophotonics� Active Silicon Photonics� CMOS, Silicon for Photonics� Systems, Packaging, & Integration

� Design tools, Si-EPIC component Library� Foundry fabrication� Experimental facilities� Research� Si-EPIC Annual Research Review meeting

� June 2012 @ McGill

30

Page 32: NSERC CREATE Si-EPIC Program...Final GDS Students submit: Final report Chip Layout – 2009-10 (23 designs, MPW) 5 12 mm 7 mm One student design 2008-2009 Course – Chips Received

Si-EPIC Chip Measurements

� Fibre Grating Coupler:1. Manual single-fibre stations2. Semi-automated single-fibre station3. Automated fibre-array station for die-level testing

� Edge Coupling:1. Semi-automated edge-coupling station

� Experimental facilities distributed throughout Canada� e.g., High-speed BERT, 100 Gb/s at McGill

31

Page 33: NSERC CREATE Si-EPIC Program...Final GDS Students submit: Final report Chip Layout – 2009-10 (23 designs, MPW) 5 12 mm 7 mm One student design 2008-2009 Course – Chips Received

Semi-automated single-fibre measurement station� Auto-alignment, computer

controlled� < 1 minute per device test

� 2 independent fibres� stepper + piezo controlled

� Wafer/die stage� stepper motors

� Coordinates loaded from spreadsheet

� Optical spectrum� Tunable laser 1460-1640 nm

� Temperature control

32

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Page 34: NSERC CREATE Si-EPIC Program...Final GDS Students submit: Final report Chip Layout – 2009-10 (23 designs, MPW) 5 12 mm 7 mm One student design 2008-2009 Course – Chips Received

Automated Probe Station – Fibre-Array

� Auto-alignment, in-house automated software� Coordinates loaded from

spreadsheet

� Fibre array� Z stepper stage, manual theta

� Sample XY stages � Die-level test� 10 cm travel stepper � 50 nm repeatability

� Optical spectrum� Tunable laser 1460-1640 nm

� Electrical probes� 67 GHz VNA

33

Fibre Array:- 4 to 64 fibres- 127 µm pitch- TE / TM- PM fibre

Page 35: NSERC CREATE Si-EPIC Program...Final GDS Students submit: Final report Chip Layout – 2009-10 (23 designs, MPW) 5 12 mm 7 mm One student design 2008-2009 Course – Chips Received

Si-EPIC

Outline – Si-EPIC Training Program� History: CMC-UBC Silicon Photonics workshops, 2008+� NSERC CREATE grant

� Researchers, industry

� Si-EPIC training workshops� Passive Silicon Nanophotonics� Active Silicon Photonics� CMOS, Silicon for Photonics� Systems, Packaging, & Integration

� Design tools, Si-EPIC component Library� Foundry fabrication� Experimental facilities� Research� Si-EPIC Annual Research Review meeting

� June 2012 @ McGill

34

Page 36: NSERC CREATE Si-EPIC Program...Final GDS Students submit: Final report Chip Layout – 2009-10 (23 designs, MPW) 5 12 mm 7 mm One student design 2008-2009 Course – Chips Received

Si-EPIC

Research – Si-EPIC Professors

Lukas ChrostowskiProgram Director – Si-EPIC ProgramAssociate Professor, Electrical and Computer EngineeringUniversity of British Columbiahttp://www.ece.ubc.ca/faculty/lukas-chrostowski

Vincent AimezProfessor, Electrical and Computer Engineering University of Sherbrookehttp://www.usherbrooke.ca/gelecinfo/fr/pers/profs/aimv-fr/

Andrew P. Knights Associate Professor, Engineering PhysicsMcMaster Universityhttp://engphys.mcmaster.ca/faculty_staff/faculty/knights/

Wei-Ping HuangProfessor, Electrical and Computer Engineering McMaster Universityhttp://photonsrvr.ece.mcmaster.ca/huang/Home.htm

Jeff F. YoungProfessor, Physics and AstronomyUniversity of British Columbiahttps://www.phas.ubc.ca/users/jeff-young

Nicolas A. F. JaegerProfessor, Electrical and Computer EngineeringUniversity of British Columbiahttp://www.ece.ubc.ca/~nickj/

35

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Shahriar MirabbasiAssociate Professor, Electrical and Computer EngineerinUniversity of British Columbiahttp://www.ece.ubc.ca/~shahriar/

Odile Liboiron-Ladouceur Assistant Professor, Electrical and Computer EngineeringMcGill Universityhttp://www.photonics.ece.mcgill.ca/Liboiron-Ladouceur/LLadouceur.html

David V. PlantProfessor, Electrical and Computer EngineeringMcGill Universityhttp://www.photonics.ece.mcgill.ca/Plant/Plant.html

Jianping YaoProfessor and University Research Chair in Microwave PUniversity of Ottawahttp://www.site.uottawa.ca/~jpyao/

Robert W. BoydProfessor and Canada Excellence Research Chair, QuanPhysicsUniversity of Ottawahttp://www.quantumphotonics.uottawa.ca/robert-boyd-en

Page 37: NSERC CREATE Si-EPIC Program...Final GDS Students submit: Final report Chip Layout – 2009-10 (23 designs, MPW) 5 12 mm 7 mm One student design 2008-2009 Course – Chips Received

Si-EPIC 36

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See also the group of Shahriar on fast-light and interferometry

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Robert W. BoydProfessor and Canada Excellence Research Chair, Quantum PhysicsUniversity of Ottawa

Page 38: NSERC CREATE Si-EPIC Program...Final GDS Students submit: Final report Chip Layout – 2009-10 (23 designs, MPW) 5 12 mm 7 mm One student design 2008-2009 Course – Chips Received

Si-EPIC 37

Development of a Chip-Scale Slow-Light Spectrometer

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Flat-band photonic crystal structure

One design uses an arrayed waveguide gratingWe will use slow-light based on the propertiesof a photonic crystal structure

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Design goal: 0.1 nm (12 GHz) resolution over a 10 nm working range

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Page 39: NSERC CREATE Si-EPIC Program...Final GDS Students submit: Final report Chip Layout – 2009-10 (23 designs, MPW) 5 12 mm 7 mm One student design 2008-2009 Course – Chips Received

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Page 40: NSERC CREATE Si-EPIC Program...Final GDS Students submit: Final report Chip Layout – 2009-10 (23 designs, MPW) 5 12 mm 7 mm One student design 2008-2009 Course – Chips Received

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Page 41: NSERC CREATE Si-EPIC Program...Final GDS Students submit: Final report Chip Layout – 2009-10 (23 designs, MPW) 5 12 mm 7 mm One student design 2008-2009 Course – Chips Received

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Page 42: NSERC CREATE Si-EPIC Program...Final GDS Students submit: Final report Chip Layout – 2009-10 (23 designs, MPW) 5 12 mm 7 mm One student design 2008-2009 Course – Chips Received

1

Jianping YaoMicrowave Photonics Research LaboratoryOttawa University� Published over 150 journals papers since 2004 in microwave photonics� Equipment

– Optical tables, optical fibres, optical vector analyzer, optical spectrum analyzers, FBG system, tunable laser sources, AWG (10 G sample per second), microwave source, BERT, VNA, 32-GHz Oscilloscope, 53 GHz optical / 63 GHz Electrical sampling Oscilloscope, microwave source analyzer

� Silicon Photonics for Microwave Photonics - Arbitrary radio-frequency waveform generation - Tunable microwave phase shifter - Analog all-optical signal processor - Photonic microwave delay-line filter

Page 43: NSERC CREATE Si-EPIC Program...Final GDS Students submit: Final report Chip Layout – 2009-10 (23 designs, MPW) 5 12 mm 7 mm One student design 2008-2009 Course – Chips Received

1

Equipment in the MWPLab at u Ottawa

Page 44: NSERC CREATE Si-EPIC Program...Final GDS Students submit: Final report Chip Layout – 2009-10 (23 designs, MPW) 5 12 mm 7 mm One student design 2008-2009 Course – Chips Received

1

Arbitrary radio-frequency waveform generationIn our previous work, a photonic RF arbitrary waveform generator based on spectral shaping and wavelength-to-time mapping was demonstrated. The pulse shaper is not integrated with large size.

Now we use silicon-chip-based spectral shaper, which brings three advantages:1) small footprint; 2) low propagation loss, high Q; 3) tunable by the thermal-optic effect.

C. Wang, F. Zeng, and J. P. Yao, "All-Fiber UWB pulse generation based on spectral shaping and dispersion-induced frequency-to-time conversion," IEEE Photon. Technol. Lett. , vol.19, no. 3, pp. 137-139, Feb. 2007.

Wavelength

Optical Spectrum

Wavelength

Filter Response

Optical Line Electrical Line

Pulsed Laser Source

Optical Spectral Filter

Dispersive Device Photodetector

Wavelength

Filtered Spectrum

Time

Output Waveform

Page 45: NSERC CREATE Si-EPIC Program...Final GDS Students submit: Final report Chip Layout – 2009-10 (23 designs, MPW) 5 12 mm 7 mm One student design 2008-2009 Course – Chips Received

Si-EPIC

Prof. Shahriar Mirabbasi

� CMOS Electronics for Photonics research:� Integration of electronics (as much as possible) with photonics blocks � Performance optimization of the electronics blocks� Co-design electrical and optical components to optimize overall performance� Take advantage of advances in CMOS (and its volume manufacturing) to

reduce the cost in optical links

� 90 nm CMOS TSMC design submitted� High-speed driver for a travelling-wave Mach-Zehnder Interferometer modulator� Detector Trans-impedance amplifier (TIA)� Integration approach: flip-chip bonding CMOS onto photonics die

� Expertise in RF CMOS design, e.g.� Zargaran-Yazd, et al “A 10 Gb/s low-power SERDES receiver based on a

hybrid speculative/SAR digitization technique”, ISCAS, 2011 (65 nm CMOS)� N Nouri, S Mirabbasi, “A 67-GHz low-phase-noise oscillator and its

application in a polar transmitter”, Analog Integrated Circuits and Signal Processing, 2011

44

Page 46: NSERC CREATE Si-EPIC Program...Final GDS Students submit: Final report Chip Layout – 2009-10 (23 designs, MPW) 5 12 mm 7 mm One student design 2008-2009 Course – Chips Received

Si-EPIC

Outline – Si-EPIC Training Program� History: CMC-UBC Silicon Photonics workshops, 2008+� NSERC CREATE grant

� Researchers, industry

� Si-EPIC training workshops� Passive Silicon Nanophotonics� Active Silicon Photonics� CMOS, Silicon for Photonics� Systems, Packaging, & Integration

� Design tools, Si-EPIC component Library� Foundry fabrication� Experimental facilities� Research� Si-EPIC Annual Research Review meeting

� June 2012 @ McGill

45

Page 47: NSERC CREATE Si-EPIC Program...Final GDS Students submit: Final report Chip Layout – 2009-10 (23 designs, MPW) 5 12 mm 7 mm One student design 2008-2009 Course – Chips Received

Si-EPIC

Si-EPIC Annual Research Review meeting

� Annual Silicon Photonics meeting in Canada � ~ June 2012� Location: McGill University� co-located with a SiEPIC workshop� Conference open to all� Day 1:

� Invited academic & industry speakers� Keynote� Poster session

� Day 2:� Si-EPIC academic talks� Industry – student meetings� Design competition awards

46

http://www.SiEPIC.ubc.ca

Page 48: NSERC CREATE Si-EPIC Program...Final GDS Students submit: Final report Chip Layout – 2009-10 (23 designs, MPW) 5 12 mm 7 mm One student design 2008-2009 Course – Chips Received

Si-EPIC

Path for success in Si-EPIC program

� student internships in Canadian industry� workshops

� continue with successful approach� increased industry participation -- attendees, presenters

� coordinated research efforts across Canada� Research collaborations enabled by SiEPIC CREATE

� Si-EPIC Library� numerous components� used for sub-systems / systems R&D, both academics and industry

� an ecosystem in Canada� companies, students graduating, translation of university research, training via

workshops� similar to CMOS community: modelling, design, device designers, system

designers, test, applications, products

47

Page 49: NSERC CREATE Si-EPIC Program...Final GDS Students submit: Final report Chip Layout – 2009-10 (23 designs, MPW) 5 12 mm 7 mm One student design 2008-2009 Course – Chips Received

Thank you to workshop participants!

48

2009

2010

2011

2012