Note:

For Q1 : Refer to 1st year lectures

For Q9 (Mechatronics): Refer to your lectures as it has been solved in the class

Subject : Dig. Techniques and Microprocessors Lecturer: Dr Laith Jasim Saud Exam. Date: Mon. 13-2-2012 (Final term exam.)

University of Technology Control & Systems Engineering Dept. Academic year 2011-2012 M.Sc. courses (Computers Eng.)

** Time : 3 hrs ** - االجابة على ورقة االسئلة - يمنع استخدام الحاسبات المبرمجة او التي تحوي مجموعة الحروف أالبجدية

- يمنع تواجد الهواتف النقالة Note: Depend on the data and information given to you in the question. Make any necessary assumptions in case you think they are inevitable to solve the question.

Q1- Complete the truth table given below (( 6 marks)):

S-R F-F implemented using NOR gates

The F-F symbol

Inputs Outputs comments

S R QR1 QR2 0 0 0 0 0 0

0 0

0 1 1 0 1 1

The F-F Truth Table Q2- To implement an n-variable function (with k minterms) we have the following options available with us : (( 7 marks)) • n to 2P

nP decoder + k input OR gate.

• 2P

nP : 1 multiplexer

• 2P

n-1 P: 1 multiplexer + 1 inverter with ( n-1 ) select lines

• 2P

nP × 1 ROM

• n × p × 1 ((p ≤ k)) PLA

Q3- Complete: (( 7 marks)) - A 4-bit carry look- ahead adder has a delay of 4 Gates. - A 12-bit carry look- ahead adder has a delay of 8 Gates. - A 16-bit carry look- ahead adder has a delay of 10 Gates. - For a 4-bit adder: There are 4 gates in the longest path of a carry look- ahead adder versus 9 gates for a

ripple carry adder. - For a 16-bit adder: There are 10 gates in the longest path of a carry look- ahead adder versus 33 gates for a

ripple carry adder.

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Q4- Give a general block diagram for a synchronous sequential circuit, and a general block diagram for an asynchronous sequential circuit (( 8 marks))

Q5- It is required to design a circuit with two inputs X1 X2

which detects the sequence 11,01,11 on these inputs and gives an output Z=1 whenever this sequence occurs. Overlapping is allowed. Just give the state diagram for this cct. (( 14 marks))

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Q6- Reduce the following state table (( 12 marks))

Q7 - For the cct shown below, give the state table as a k-map. (( 7 marks))

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Q8- Give a block diagram for a serial adder which adds two n-bits numbers and gives the final sum and carry. (( 11 marks))

Q9- Consider the state table shown below: (( 22 marks))

a- Create merger diagram and use it to merge the compatible states and write the new state table after merging . b- Considering the state table you found in A above, Give a critical-race-free state assignment.

a-

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b-

Note: Fill in outputs corresponding to unstable states to avoid momentary false outputs during transitions.

Q10- Define static hazard. Use a 2×4 K-map to show a static hazard case and how to avoid it (( 6 marks)) When one input variable changes, the output changes momentarily when it shouldn't. Or : The change of a single variable causes a momentary change in other variables which should not occur.

Q11- It required to design a cct which has 2 inputs (A and B) and one output (Z), so that: Z = A when B=1, and Z keeps its last value when B=0. Give the state table for this cct. (( 6 marks))

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Q12- Design a synchronous circuit with a single input X which can detect the pattern 0101 in the input sequence and gives an output z=1 whenever this pattern occurs. Overlapping is possible. Use D-FFs in implementing your design. (( 25 marks))

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Q13- Design an arithmetic-logic –shift unit which accomplishes the functions given in the table below on two n-bit numbers A and B. Give just one stage of this unit. ((18marks))

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Q14- Design a bus system for 3 registers using MUXs. Each register has 3 bits. (( 9 marks))

Q15- (( 10 marks)) a- define critical race: A race condition exists in an asynchronous circuit when two or more binary state variables change value in response to a change in an input variable. And if the final state depends on the order in which variables change, then the race is said to be critical. b- Races may be avoided by :

- Directing through intermediate unstable states. - Proper states assignment.

c- Show if there is a critical race in the state table of figure below.

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Q16- Complete the followings regarding the 8086 microprocessor (( 12 marks)) a- It is a 16 - bit microprocessor. It’s ALU, internal registers works with 16 bit binary word. b- It has a 20 bit address bus can access up to 1M memory locations. c- It has a 16 bit data bus. It can read or write data to a memory/port either 8 bits or 16 bit at a time. d- It can support up to 64k I/O ports. e- It provides 14 registers each of which is composed of 16 bit. f- It can pre-fetch up to 6 instruction bytes from memory and queues them in order to speed up instruction execution. g- It requires 5 V power supply. h- It has A 40 pin Dual Inline package. i- It is designed to operate in two modes, MIN mode and MAX mode.

j- It is composed of Two main units EU and BIU The first unit is composed of : ALU, Registers, Flags, Control and Timing, Decoding cct And the second is composed of: Instructions queue, Summing unit, Registers Q17- (( 9+14+6+6+9 marks)) a- Name 6 groups in the instruction set of the 8086 µp and give a sample instruction for each group Data transfer: MOV AL,15 Arithmetic: ADD AL,-3 Logic: AND AL,00H Shift and rotate: ROR AL,1 Transfer: JMP ** Subroutine and Interrupt: RET ……… b- Name the 8086 µp registers and state the role of each one

1- AX - the accumulator register (AH / AL): Used for : Arithmetic, logic and data transfer …. 2- BX - the base address register (BH / BL): usually contains a data pointer used for based, based indexed

or register indirect addressing. 3- CX - the count register (CH / CL): Used for Iterative code segments using the LOOP instruction …… 4- DX - the data register (DH / DL): Specifying ports in some IN and OUT operations …… 5- SI - source index register: Can be used for pointer addressing of data……… 6- DI - destination index register: Can be used for pointer addressing of data…….. 7- BP - base pointer: Primarily used to access parameters passed via the stack… 8- SP - stack pointer: Always points to top item on the stack…. 9- CS - points at the segment containing the current program. 10- DS - generally points at segment where variables are defined. 11- ES - extra segment register, it's up to a coder to define its usage. 12- SS - points at the segment containing the stack. 13- IP - the instruction pointer: Always points to next instruction to be executed ….. 14- Flags Register: indicates some conditions produced by the execution of an instruction or controls certain

operations of the EU….

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……………………………………………………………………………………………………………….. ……………………………………………………………………………………………………………….. ……………………………………………………………………………………………………………….. ……………………………………………………………………………………………………………….. ………………………………………………………………………………………………………………..

c- Give the default assignment of registers to each of the segment registers.

CS: IP DS: BX, DI, SI ES: DI SS: SP, BP

d- Name 6 flag bits in the 8086 µp and state the role of each.

1- Carry Flag (CF) - this flag is set to 1 when there is an unsigned overflow. 2- Parity Flag (PF) - this flag is set to 1 when there is even number of one bits in result. 3- Auxiliary Flag (AF) - set to 1 when there is an unsigned overflow for low nibble. 4- Zero Flag (ZF) - set to 1 when result is zero. 5- Sign Flag (SF) - set to 1 when result is negative. 6- Overflow Flag (OF) - set to 1 when there is a signed overflow.

…………….. e-

Name the signals groups in the 8086 µp min mode, and explain the role of the following signals Interrupt, DMA, Mode, Address/Data, M/IO

INTR, It is a maskable hardware interrupt used by external units to interrupt the microprocessor so as to do a pre-specified routine. The processor uses the INTA signal to acknowledge the INTR request. There are specified detailed rules regarding the way to deal with such interrupt signal. HOLD, It is a signal used by some other master unit to indicate to the microprocessor that this master unit is requesting a local bus “hold”, so that the other master can use the bus. The processor receiving the ``hold'' request uses the HLDA signal to acknowledge the HOLD request. There are specified detailed rules regarding the way to deal with such interrupt signal.

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Q18- (( 6+7+6+8+6 marks)) a- Name the addressing modes of the 8086 µp

Immediate, Register, Direct, Indirect : Base (B), Index (I), B + I, B + Displacement (D), I + D , B + I + D b- For the 8086 µp, if DS=3300H, SI=0300H, BX=0400H, then what will be the physical address in the following cases MOV AL, [BX+8]

33408 MOV [BX+SI] , BP

33700

MOV [BX] , CL 33400

MOV [2222H] , AX

35222 MOV AH, 33H

Immediate c- Write a program to output the value 55H to a port with address F000H. Mov AL, 55H Mov DX, F000H Out DX,AL d- Explain how the push pop works PUSH: 1- SP=SP-2 2- Move data to memory [SS:SP] POP: 1- Bring data from memory 2- SP=SP+2 [SS:SP]

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e- Show how the execution time of a given 8086µp program is calculated? - The execution time for each instruction is calculated depending on: the number of cycles for each

instruction, the number of clocks for each cycle, and the frequency. - The program time is given by the sum of the instructions time. - Loops must be taken into consideration as some instructions will be repeated. - Dependent cases must be, as well, taken into consideration.

Q19- Show how the following programs affect (step by step) the values in AL and AH, and the flags in the end. (( 12 marks))

Program 1: MOV AL, 23 AL=17H AAM AH=02 AL=03 RET Flags C: Z: S: O: P: A: x 0 0 x 1 x Program2: STC CF=1 MOV AL, 8 AL=08H ADC AL, 1 AL=0AH RET Flags C: Z: S: O: P: A:

0 0 0 0 1 0

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**NOTE: 1- 8086 Signal to be considered in any of the interfacing questions and as necessary are: Data signals, address signals, RD,WR, M/IO , BHE, DEN, D T/R, MN/MX, ALE,READY 2- Use the 8086 in the minimum mode. Q20 - Interface the signals ADD A, ADD B, ADD C, ALE in the ADC0808 to the 8086 µp. (( 8 marks))

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Q21- Interface the ADC0808 to the 8086 µp indirectly through the 8255 PPI (( 18 marks))

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Q22- Design a circuit for buffering the data bus of the 8086 µp. (( 7 marks))

Q23- Give the read cycle timing diagram for the 8086 µp in the minimum mode. (( 12 marks))

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Q24- Interface two 4K×8 ROMS and two 4K×8 RAMS chips with the 8086µp. The ROMS should start at address FE000H, and the RAMs at address FA000H. The 4 chips should compose a 8K× 16 memory size with the possibility of accessing 8 bit data in the odd as well as the even addresses. ((19marks))

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Q25- Interface the 16 bit tri state buffer shown below to input 16 bit data to the 8086 µp. (( 8 marks))

Q26- Complete the followings regarding the 80386DX µp ((22 marks))

a- It is a 32 - bit microprocessor. b- The memory management techniques used in it are segmentation , paging c- It has a 32 bit address bus d- The no of segments it can support is 16k and the size of the virtual memory it can handle is 4GB × 16k = 64 T B e- The very main units of it are CPU, MMU, BIU f- It is can operate in one of the following modes: Real, Virtual, Protected g- It can (can, cannot) run programs written for the 8086µp. h- One of the addressing modes which is in it and not in the 8086µp is: scaled. i- A register group or type in it and do not exist in the 8086µp is : Control. j- One new instruction in it which do not exist in the 8086µp is CWDE k- The main signals in it necessary for interfacing a memory and an I/O port to it are

l- Which is more efficient; the 8086 or the 80386? Say why in very short notice points. (give 6 points). The 80386: - Faster. - More instructions. - New added instructions. - Larger memory. - Larger accumulator. - Larger registers. - Larger data bus. - …….

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Q27- Complete the design of the circuit shown below to form a 4× 1GB memory for the 80386DX. The 80386Dx signals to be used in your design are: ((16marks))

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