Non-Pilot Protection of the HVDC Grid...ii Abstract Non-Pilot Protection of the HVDC Grid Firouz...

Non-Pilot Protection of the HVDC Grid

by

Firouz Badrkhani Ajaei

A thesis submitted in conformity with the requirements for the degree of Doctor of Philosophy

Department of Electrical and Computer Engineering University of Toronto

© Copyright 2016 by Firouz Badrkhani Ajaei

ii

Abstract

Non-Pilot Protection of the HVDC Grid

Firouz Badrkhani Ajaei

Doctor of Philosophy

Department of Electrical and Computer Engineering University of Toronto

2016

This thesis develops a non-pilot protection system for the next generation power transmission

system, the High-Voltage Direct Current (HVDC) grid. The HVDC grid protection system is

required to be (i) adequately fast to prevent damages and/or converter blocking and (ii) reliable

to minimize the impacts of faults. This study is mainly focused on the Modular Multilevel

Converter (MMC) -based HVDC grid since the MMC is considered as the building block of the

future HVDC systems.

The studies reported in this thesis include (i) developing an enhanced equivalent model of the

MMC to enable accurate representation of its DC-side fault response, (ii) developing a realistic

HVDC-AC test system that includes a five-terminal MMC-based HVDC grid embedded in a

large interconnected AC network, (iii) investigating the transient response of the developed test

system to AC-side and DC-side disturbances in order to determine the HVDC grid protection

requirements, (iv) investigating the fault surge propagation in the HVDC grid to determine the

impacts of the DC-side fault location on the measured signals at each relay location, (v)

designing a protection algorithm that detects and locates DC-side faults reliably and sufficiently

fast to prevent relay malfunction and unnecessary blocking of the converters, and (vi) performing

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hardware-in-the-loop tests on the designed relay to verify its potential to be implemented in

hardware.

The results of the off-line time domain transients studies in the PSCAD software platform

and the real-time hardware-in-the-loop tests using an enhanced version of the RTDS platform

indicate that the developed HVDC grid relay meets all technical requirements including speed,

dependability, security, selectivity, and robustness. Moreover, the developed protection

algorithm does not impose considerable computational burden on the hardware.

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Acknowledgements

I would like to express my utmost gratitude and appreciation to my supervisor

Professor Reza Iravani for his patient guidance, constant encouragement, and unstinting support.

I am eternally thankful to him for the opportunity to learn from him in every aspect of my

academic career.

I would like to thank my Ph.D. examination committee members, Professors Peter Lehn,

Zeb Tate, Olivier Trescases, and Vijay Sood for their constructive comments. I also acknowledge

the generous financial support provided by Professor Reza Iravani and the University of Toronto.

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To Rana

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Table of Contents

LIST OF TABLES .................................................................................................................................................... IX

LIST OF FIGURES .................................................................................................................................................... X

NOMENCLATURE ................................................................................................................................................ XV

1. INTRODUCTION .............................................................................................................................................. 1

1.1. STATEMENT OF THE PROBLEM .................................................................................................................... 1 1.2. THESIS OBJECTIVES .................................................................................................................................... 2 1.3. BACKGROUND ............................................................................................................................................. 2

1.3.1. Features of the HVDC Grid ................................................................................................................... 2 1.3.2. HVDC Converter Topologies ................................................................................................................ 3 1.3.3. HVDC System Configurations .............................................................................................................. 6 1.3.4. Requirements and Challenges of the HVDC Grid Protection ................................................................ 7 1.3.5. Overview and Shortcomings of the Envisioned HVDC Grid Protection Methods .............................. 10

1.4. METHODOLOGY ........................................................................................................................................ 12 1.5. STUDY SYSTEMS ....................................................................................................................................... 12 1.6. THESIS LAYOUT ........................................................................................................................................ 13

2. ENHANCED EQUIVALENT MODEL OF THE MMC .............................................................................. 14

2.1. INTRODUCTION .......................................................................................................................................... 14 2.2. MODELING STRATEGY .............................................................................................................................. 15

2.2.1. MMC Arm Model in the Un-blocked State ......................................................................................... 15 2.2.2. MMC Arm Model in the Blocked State ............................................................................................... 19 2.2.3. Generalized MMC Arm Model ............................................................................................................ 20

2.3. VALIDATION OF THE EQUIVALENT MODEL ............................................................................................... 21 2.3.1. Test System .......................................................................................................................................... 21

2.3.1.1. AC-side Systems ........................................................................................................................................ 22 2.3.1.2. MMC Circuit .............................................................................................................................................. 22 2.3.1.3. Converter Controller .................................................................................................................................. 22 2.3.1.4. HVDC Cable .............................................................................................................................................. 23

2.3.2. Study Results ....................................................................................................................................... 24

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2.3.2.1. Power Ramp-up Scenario ........................................................................................................................... 24 2.3.2.2. DC-side Fault Scenario .............................................................................................................................. 26 2.3.2.3. AC-side Fault Scenario .............................................................................................................................. 27 2.3.2.4. Effects of the Number of MMC Levels ...................................................................................................... 28

2.4. CONCLUSIONS ........................................................................................................................................... 30

3. TRANSIENT RESPONSE TO AC-SIDE DISTURBANCES ...................................................................... 31

3.1. INTRODUCTION .......................................................................................................................................... 31 3.2. HVDC-AC GRID STUDY SYSTEM ............................................................................................................. 32

3.2.1. System-1 .............................................................................................................................................. 33 3.2.2. System-2 .............................................................................................................................................. 33

3.3. RESPONSE TO AC-SIDE DISTURBANCES .................................................................................................... 42 3.3.1. Case I - AC Line Tripping ................................................................................................................... 42 3.3.2. Case II - Generator Tripping ................................................................................................................ 44 3.3.3. Case III - AC System Faults ................................................................................................................ 46

3.3.3.1. Fault on a line ............................................................................................................................................. 46 3.3.3.2. Fault on a Bus ............................................................................................................................................ 49

3.4. CONCLUSIONS ........................................................................................................................................... 51

4. TRANSIENT RESPONSE TO DC-SIDE DISTURBANCES ...................................................................... 52

4.1. INTRODUCTION .......................................................................................................................................... 52 4.2. TRANSIENT RESPONSE WITHOUT PROTECTIVE COMPONENTS ................................................................... 54

4.2.1. Change of Converter Power Set Point ................................................................................................. 54 4.2.2. Converter Outage and DC Voltage Droop Control .............................................................................. 55 4.2.3. DC-Side Fault Response ...................................................................................................................... 57

4.2.3.1. DC-side Line-to-Line Fault ........................................................................................................................ 58 4.2.3.2. DC-side Line-to-Ground Fault ................................................................................................................... 58

4.3. TRANSIENT RESPONSE WITH PROTECTIVE COMPONENTS .......................................................................... 60 4.3.1. Protective Components of the HVDC Grid ......................................................................................... 61

4.3.1.1. DC Surge Arrester ...................................................................................................................................... 61 4.3.1.2. DC Circuit Breaker .................................................................................................................................... 63 4.3.1.3. DC Line Reactor ........................................................................................................................................ 66

4.3.2. DC-Side Fault Response ...................................................................................................................... 70 4.3.2.1. DC-Side Line-to-Line Fault ....................................................................................................................... 71 4.3.2.2. DC-side Line-to-Ground Fault ................................................................................................................... 72

4.4. CONCLUSIONS ........................................................................................................................................... 76

5. HVDC GRID PROTECTION ......................................................................................................................... 77

5.1. INTRODUCTION .......................................................................................................................................... 77 5.2. FAULT SURGE PROPAGATION IN THE MMC-HVDC GRID ......................................................................... 78

5.2.1. Incident Wave ...................................................................................................................................... 79

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5.2.2. Wave Reflection and Transmission at the MMC Station ..................................................................... 80 5.3. ISSUES OF THE TRAVELLING WAVE PROTECTION STRATEGIES ................................................................. 91 5.4. LOCATING FAULTS USING THE INCIDENT VOLTAGE .................................................................................. 92

5.4.1. Operation Principle of Incident Voltage Relay .................................................................................... 93 5.4.2. Implementation and Settings of the Relay ........................................................................................... 95

5.5. PERFORMANCE EVALUATION BASED ON OFF-LINE SIMULATION ............................................................... 98 5.5.1. Line-to-Ground Fault ........................................................................................................................... 99

5.5.1.1. Line-to-Ground Fault on a Cable ............................................................................................................... 99 5.5.1.2. Line-to-Ground Fault on an Over-head Line .............................................................................................. 99

5.5.2. Line-to-Line Fault ................................................................................................................................ 99 5.5.2.1. Line-to-Line Fault on a Cable .................................................................................................................... 99 5.5.2.2. Line-to-Line Fault on an Over-head Line ................................................................................................ 103

5.5.3. Operation Time of the Incident Voltage Relay .................................................................................. 104 5.6. CONCLUSIONS ......................................................................................................................................... 105

6. HIL TESTING OF THE HVDC GRID RELAY ......................................................................................... 107

6.1. INTRODUCTION ........................................................................................................................................ 107 6.2. REAL-TIME SIMULATION OF THE HVDC GRID ....................................................................................... 108 6.3. HARDWARE IMPLEMENTATION OF THE HVDC GRID RELAY ................................................................... 109 6.4. STUDY RESULTS ...................................................................................................................................... 113

6.4.1. Real-time HVDC Grid Model Verification ....................................................................................... 113 6.4.2. Relay Performance............................................................................................................................. 113

6.5. CONCLUSIONS ......................................................................................................................................... 118

7. CONCLUSIONS ............................................................................................................................................ 119

7.1. SUMMARY ............................................................................................................................................... 119 7.2. CONCLUSIONS ......................................................................................................................................... 119 7.3. CONTRIBUTIONS ...................................................................................................................................... 120 7.4. FUTURE WORK ........................................................................................................................................ 121

APPENDIX A: DEFINITIONS .............................................................................................................................. 122

REFERENCES ........................................................................................................................................................ 124

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List of Tables

1.1 Recent MMC-HVDC Transmission Projects by Siemens .......................................................... 5

2.1 Comparison of RTh with Rc+R1 for Different Simulation Time Steps (On-state) .......................... 18

2.2 Comparison of RTh with R2 for Different Simulation Time Steps (Off-state) ............................... 18

3.1 Bus Data of System-1 ................................................................................................................... 34

3.2 Line Data of System-1 ................................................................................................................. 35

3.3 MMC Operation Modes and Set Points ....................................................................................... 37

3.4 MMC Circuit Parameters ............................................................................................................. 37

3.5 MMC Current Ratings .................................................................................................................. 37

3.6 System-2 HVDC Line Data ......................................................................................................... 39

3.7 MMC Controller Parameters ........................................................................................................ 41

3.8 MMC Controller Low Pass Filter Parameters .............................................................................. 41

4.1 MMC3 blocking delays under DC-side line-to-line faults at different locations on cable 1......... 67

4.2 MMC3 blocking delays under DC-side line-to-ground faults at different locations on cable 1.... 67

4.3 MMC blocking delay of the System-2, under DC-side line-to-line faults .................................... 68

4.4 MMC blocking delay of the System-2, under DC-side line-to-ground faults ............................... 69

5.1 Ratios of the line-to-ground fault-imposed voltages that appear across the components of each station in System-2 ........................................................................................................................

90

5.2 Ratios of the line-to-line fault-imposed voltages that appear across the components of each station in System-2 ........................................................................................................................

90

5.3 Operation delay of the incident voltage relays, under DC-side faults .......................................... 104

6.1 Optimal allocation of analogue input signals for PXI 7854-R FPGA to maximize the number of relays implemented in the PXI Platform ...................................................................................

110

6.2 Details of the incident voltage relays implemented in PXI ........................................................... 111

6.3 Operation delay of the incident voltage relays, under DC-side faults .......................................... 117

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List of Figures

1.1 Circuit diagrams of (a) diode clamped converter, (b) flying capacitors converter, (c) cascaded

H-bridge converter, (d) modular multilevel converter .................................................................. 4

2.1 Circuit diagram of a half-bridge symmetrical monopole MMC ................................................... 16

2.2 BEM of each sub-module of the MMC ......................................................................................... 16

2.3 Effective circuit of the blocked and bypassed sub-module when (a) the current enters from terminal A, (b) the current enters from terminal B ......................................................................

19

2.4 Proposed generalized MMC arm model ..................................................................................... 20

2.5 Single-line diagram of the France-Spain point-to-point HVDC system ....................................... 21

2.6 Block diagram of the inverter and rectifier main controllers ...................................................... 23

2.7 Block diagram of the inverter and rectifier circulating current controllers .................................. 23

2.8 Configuration and dimensions of the utilized cable model ......................................................... 24

2.9 Dynamic response of the 11-level inverter detailed model, during the power ramp-up scenario, (a) & (b) phase-A sub-module voltages of upper and lower arms, (c) DC-link voltage, (d) DC-terminal current, (e) phase-A currents of upper and lower arms ..................................................

25

2.10 Dynamic response of the 11-level inverter EEM, during the power ramp-up scenario, (a) & (b) phase-A sub-module voltages of upper and lower arms, (c) DC-link voltage, (d) DC-terminal current, (e) phase-A currents of upper and lower arms ................................................................

25

2.11 DC-link voltage error corresponding to Figs. 2.9(d) and 2.10(d) ............................................... 25

2.12 Same waveforms as those of Fig. 2.9, obtained from the rectifier detailed model, under DC-side line-to-line fault conditions ....................................................................................................

26

2.13 Same waveforms as those of Fig. 2.10, obtained from the rectifier EEM, under DC-side line-to-line fault conditions ................................................................................................................

26

2.14 Comparison of the inverter DC-terminal currents obtained from the EEM and the detailed model, under a DC-side line-to-line fault, (a) DC-terminal currents, (b) error associated with the DC-terminal currents of (a) ...................................................................................................

26

2.15 Same waveforms as those of Fig. 2.10, obtained from the rectifier EEM, under AC-side three-phase fault ...................................................................................................................................

27

2.16 Error of (a) the DC-link voltage and (b) the DC-link current, obtained from the EEM and the detailed model .............................................................................................................................

28

2.17 Same waveforms as those of Fig. 2.10, obtained from the 401-level EEM ................................. 29

2.18 Comparison of the dynamic responses of the 11-level EEM and the 401-level EEM of the

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inverter, (a) DC-link voltages, (b) DC-link currents .................................................................... 29

3.1 A single-line diagram of System-1 ............................................................................................... 32

3.2 A single-line diagram of System-2, i.e., the HVDC-AC grid ....................................................... 36

3.3 DC cable configuration and dimensions ....................................................................................... 38

3.4 DC over-head line configuration and dimensions ....................................................................... 38

3.5 Main controller of the MMCs for each phase .............................................................................. 39

3.6 Circulating current controller of the MMCs for each phase ....................................................... 39

3.7 Power flow of the HVDC grid and its AC terminals ................................................................... 41

3.8 Transient response of MMC2 to line 21 outage at t = 0.5 s, (a) active power injected in the HVDC grid, (b) AC terminal voltage magnitude, (c) DC terminal voltage .................................

43

3.9 Transient response of System-1 to tripping of line 21 at t = 0.5 s, (a) active power outputs of generators, (b) terminal voltages of generators .............................................................................

43

3.10 Transient response of System-2 to tripping of line 21 at t = 0.5 s, (a) active power outputs of generators, (b) terminal voltages of generators .............................................................................

44

3.11 Transient response to disconnection of G8 at t=0.5 s, (a) active powers of generators of System-1, (b) active powers of generators of System-2 ...............................................................

45

3.12 Active powers injected in the HVDC grid by MMCs 1-5 during the disturbance of Fig. 3.11(b) 45

3.13 Response of System-2 to a three-phase to ground AC-side fault on line 5, (a) line voltages at Bus 4, and (b) line currents at Bus 4 .............................................................................................

47

3.14 Variations of real powers injected in the HVDC grid by MMCs 1-5 subsequent to a three-phase to ground AC-side fault on line 5 ........................................................................................

47

3.15 Response of the HVDC grid to a three-phase to ground AC-side fault on line 5, (a) MMC DC-link voltages, and (b) MMC DC-link currents ..............................................................................

48

3.16 Response of MMC2 to the three-phase to ground AC-side fault on line 5, (a) AC terminal currents, (b) upper arm currents, and (c) lower arm currents ........................................................

49

3.17 Transient response of System-2 to a three-phase to ground AC-side fault on Bus 31, (a) fault currents, (b) Bus 31 voltages, (c) AC-terminal currents of MMC4, (d) DC-link voltage of MMC4, and (e) DC-link currents of MMC4 .................................................................................

50

3.18 Transient response of System-2 to the three-phase to ground AC-side fault on Bus 31, (a) variations of the active powers injected in the HVDC grid by MMCs1-5, and (b) AC terminal voltages of MMC2 ........................................................................................................................

50

4.1 Single-line diagram of the investigated MMC-based HVDC-AC grid (System-2) ...................... 53

4.2 Transient response of the HVDC grid to a change in MMC3 power set point, (a) active powers injected in the HVDC grid by MMCs, (b) DC terminal voltages of MMCs, (c) AC terminal voltages of MMCs, (d) voltages of the first sub-modules of MMC1 phase A upper and lower arms, (e) currents of MMC1 phase A arms ...................................................................................

55

4.3 Effects of the DC voltage droop controller gain of MMC1 on the HVDC grid transients in response to blocking MMC2, (a) power of MMC2, (b) power of MMC3, (c) power of MMC1, (d) DC terminal voltage of MMC3 ...............................................................................................

56

4.4 Transient response of MMC3 to a line-to-line fault on cable 1 at 10 km from Bus C, (a) DC-link voltage, (b) magnification of (a), (c) DC-link current, (d) AC terminal voltages, and (e)

59

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AC terminal currents .....................................................................................................................

4.5 Transient response of MMC3 to a line-to-ground fault on cable 1 at 10 km from Bus C, (a) DC-link voltage, (b) positive line voltage with respect to ground, (c) negative line voltage with respect to ground, (d) DC-link current, (e) AC terminal voltages, and (f) AC terminal currents

60

4.6 Single-line diagram of the investigated MMC-based HVDC grid with the added protective components. ..................................................................................................................................

62

4.7 Nonlinear v-i characteristic for the cable surge arresters .............................................................. 62

4.8 Modular Hybrid DCCB ................................................................................................................ 63

4.9 Operation steps of the hybrid DCCB: (a) Step 1, (b) Step 2, (c) Step 3, (d) Step 4, (e) Step 5, (e) Step 6 .....................................................................................................................................

65

4.10 Nonlinear v-i characteristic for the DCCB energy absorption element ........................................ 66

4.11 Impact of the DC line reactor size on the minimum blocking time of the MMCs ...................... 70

4.12 (a) line-to-line voltages at both sides of the reactor connected to Cable 2 at Bus D, (b) current of Cable 2 at Bus D, (c) upper arm currents of the MMC4, (d) lower arm currents of the MMC4 ..........................................................................................................................................

71

4.13 (a) line-to-line voltages at both sides of the reactor connected to Cable 2 at Bus D, (b) current passing through the DCCB mechanical switch, (c) current passing through the DCCB commutation branch, (d) current passing through the DCCB energy absorbing element, (e) voltage across the DCCB, (f) energy discharged in the DCCB energy absorbing element .........

73

4.14 (a) Upper arm currents and (b) lower arm currents of the MMC4 under the fault scenario of Fig. 4.12 ........................................................................................................................................

73

4.15 (a) line-to-line voltages at both sides of the reactor connected to Cable 2 at Bus D, (b) voltages of the cables with respect to ground, (c) cable currents at Bus D, (d) current of the surge arrester that protects the healthy line at Bus D, (e) energy of the surge arrester that protects the healthy line at Bus D ...............................................................................................................

74

4.16 (a) line-to-line voltages at both sides of the reactor connected to Cable 2 at Bus D, (b) cable currents at Bus D, (c) current of the surge arrester that protects the healthy line at Bus D, (d) energy of the surge arrester that protects the healthy line at Bus D, (e) currents of the DCCB branches, (f) voltage across the DCCB, (g) energy discharged in the DCCB energy absorbing element ..........................................................................................................................................

75

5.1 Incident waves on (a) Cable 1, and (b) over-head Line 2, measured at different distances from the fault location ............................................................................................................................

80

5.2 A schematic diagram of the MMC station connected to a faulted line ......................................... 81

5.3 Simplified equivalent circuit of the MMC station of Fig. 5.2 in frequency domain ..................... 83

5.4 Bode diagram of the reflection coefficient of station MMC3 ....................................................... 85

5.5 Bode diagrams of the transfer functions that determine the fault-imposed voltages transmitted to the healthy lines, i.e., transmission coefficients, of station MMC3 ..........................................

85

5.6 Fault-imposed transient voltages at Bus C under faults on Cable 1, at the distances of (a) 5 km, (b) 50 km, (a) 100 km, and (a) 200 km, from Bus C ....................................................................

87

5.7 Fault-imposed transient voltages at Bus A under faults on over-head Line 2, at the distances of (a) 5 km, (b) 50 km, (a) 100 km, and (a) 200 km, from Bus A .....................................................

87

5.8 High-frequency equivalent circuits of an MMC station with three lines on each pole, where the fault takes place on one of the positive polarity lines ...................................................................

88

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5.9 Connection diagram of the protection system corresponding to Line-Pj and Line-Nj in Fig. 5.2 95

5.10 Filtered (solid line) and unfiltered (dashed line) terminal voltages of Cable 1 under PLG faults at the distance of (a) 5 km, (b) 50 km, (c) 100 km, and (d) 200 km .............................................

97

5.11 Filtered (solid line) and unfiltered (dashed line) voltages across the reactor of Cable 1 under PLG faults at the distance of (a) 5 km, (b) 50 km, (c) 100 km, and (d) 200 km ...........................

97

5.12 Filtered (solid line) and unfiltered (dashed line) terminal voltages of over-head Line 2 under PLG faults at the distance of (a) 5 km, (b) 50 km, (c) 100 km, and (d) 200 km ...........................

97

5.13 Filtered (solid line) and unfiltered (dashed line) voltages across the reactor of over-head Line 2 under PLG faults at the distance of (a) 5 km, (b) 50 km, (c) 100 km, and (d) 200 km .................

97

5.14 Logic diagram of the incident voltage relay ................................................................................ 98

5.15 Trajectory of the positive polarity voltages measured by the incident voltage relay installed at Bus C for protection of Cable 1, under a PLG fault at 50 percent of the length of Cable 1 .........

100

5.16 Trajectory of the negative polarity voltages measured by the incident voltage relay installed at Bus C for protection of Cable 1, under a PLG fault at 50 percent of the length of Cable 1 .........

100

5.17 Trajectory of the positive polarity voltages measured by the incident voltage relay installed at Bus D for protection of Cable 2, under a PLG fault at 50 percent of the length of Cable 1 .........

100

5.18 Trajectory of the negative polarity voltages measured by the incident voltage relay installed at Bus D for protection of Cable 2, under a PLG fault at 50 percent of the length of Cable 1 .........

100

5.19 Trajectory of the positive polarity voltages measured by the incident voltage relay installed at Bus A for protection of over-head Line 3, under a PLG fault at 50 percent of the length of over-head Line 3 ...........................................................................................................................

101

5.20 Trajectory of the negative polarity voltages measured by the incident voltage relay installed at Bus A for protection of over-head Line 3, under a PLG fault at 50 percent of the length of over-head Line 3 ...........................................................................................................................

101

5.21 Trajectory of the positive polarity voltages measured by the incident voltage relay installed at Bus F for protection of over-head Line 2, under a PLG fault at 50 percent of the length of over-head Line 3............................................................................................................................

101

5.22 Trajectory of the negative polarity voltages measured by the incident voltage relay installed at Bus F for protection of over-head Line 2, under a PLG fault at 50 percent of the length of over-head Line 3 ...........................................................................................................................

101

5.23 Trajectory of the positive polarity voltages measured by the incident voltage relay installed at Bus C for protection of Cable 1, under a LL fault at 50 percent of the length of Cable 1 ............

102

5.24 Trajectory of the negative polarity voltages measured by the incident voltage relay installed at Bus C for protection of Cable 1, under a LL fault at 50 percent of the length of Cable 1 ............

102

5.25 Trajectory of the positive polarity voltages measured by the incident voltage relay installed at Bus D for protection of Cable 2, under a LL fault at 50 percent of the length of Cable 1 ...........

102

5.26 Trajectory of the negative polarity voltages measured by the incident voltage relay installed at Bus D for protection of Cable 2, under a LL fault at 50 percent of the length of Cable 1 ...........

102

5.27 Trajectory of the positive polarity voltages measured by the incident voltage relay installed at Bus A for protection of over-head Line 3, under a LL fault at 50 percent of the length of over-head Line 3 ....................................................................................................................................

103

5.28 Trajectory of the negative polarity voltages measured by the incident voltage relay installed at Bus A for protection of over-head Line 3, under a LL fault at 50 percent of the length of over-head Line 3 ....................................................................................................................................

103

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5.29 Trajectory of the positive polarity voltages measured by the incident voltage relay installed at Bus F for protection of over-head Line 2, under a LL fault at 50 percent of the length of over-head Line 3 ....................................................................................................................................

103

5.30 Trajectory of the negative polarity voltages measured by the incident voltage relay installed at Bus F for protection of over-head Line 2, under a LL fault at 50 percent of the length of over-head Line 3 ....................................................................................................................................

103

6.1 Schematic diagram of the components that constitute the real-time HVDC grid model ............. 108

6.2 Altera FPGA board used for MMC arm sub-modules equivalent voltage calculation ................. 109

6.3 GUI of the incident voltage relay implemented in PXI platform .................................................. 111

6.4 Hardware setup used for HIL real-time testing the incident voltage relay ................................... 111

6.5 Single-line diagram of the HVDC grid test system including the incident voltage relays implemented in hardware ..............................................................................................................

112

6.6 Comparison of the transient responses of the off-line and real-time HVDC grid models to faults: faulted line terminal voltage under positive-line-to-ground fault on (a) Cable 1, (b) Cable 2, (c) Cable 3, (d) Cable 4, (e) Over-head line 1, and (f) Over-head line 2 ........................

114

6.7 A snapshot of the HVDC grid relay fault recorder after a PLG fault on Cable 1 ......................... 115

6.8 Performance of the developed protection scheme in detecting and isolating the faulted line under a PLG fault: (a) currents of the sending end, (b) currents of the receiving end, (c) line-to-line voltages at the DC-side terminals of MMCs 1-5 ...................................................................

115

6.9 A snapshot of the HVDC grid relay fault recorder after a PLG fault on Cable 1 ......................... 116

6.10 Performance of the developed protection scheme in detecting and isolating the faulted line under a LL fault: (a) currents of the sending end, (b) currents of the receiving end, (c) line-to-line voltages at the DC-side terminals of MMCs 1-5 ...................................................................

116

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Nomenclature

R1 Two-stage resistance representing IGBT

R2 Two-stage resistance representing IGBT

Rc Resistance of the sub-module capacitor model

VcEQ Voltage of the sub-module capacitor model

Δt Simulation time step

Ic Current of the sub-module capacitor

n Number of the MMC levels

non Number of the MMC sub-modules in on-state

RarmEQ Equivalent resistance of sub-modules in each MMC arm

VarmEQ Equivalent voltage of sub-modules in each MMC arm

VTHi Thevenin equivalent voltage of the sub-module i

RThy Resistance of the sub-module bypass thyristor

La MMC arm inductance

iuj Upper arm current of the phase j arm

ilj Lower arm current of the phase j arm

vi Incident voltage

Eo Initial line to ground voltage

Propagation constant of line

Z Series impedance of line

Y Shunt impedance of line

v Electromagnetic wave velocity

Line-Pj Jth transmission line connected to the positive polarity terminals of the MMC

Line-Nj Jth transmission line connected to the negative polarity terminals of the MMC

LPj Inductance connected to the terminal of Line-Pj

LNj Inductance connected to the terminal of Line-Nj

vr-P1 First reflected voltage wave on the faulted line P1

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vr-N1 First reflected voltage wave on the faulted line N1

vt-Pj Voltage waves transmitted to Line-Pj

vt-Nj Voltage waves transmitted to Line-Nj

vL-Pj Voltages across the reactors of Line-Pj

vL-Nj Voltages across the reactors of Line-Nj

Zc Equivalent surge impedance of converter

Zarm Surge impedance of MMC arm

ZL-Pi Surge impedance of the reactor of Line Pi

ZL-Ni Surge impedance of the reactor of Line Ni

Zline-Pi Surge impedance of Line Pi

Zline-Ni Surge impedance of Line Ni

ΓPi Reflection coefficient of line Pi

Vr-Pi Reflected voltage on line Pi

α1 Ratio of the voltage imposed across the reactor of the faulted line to the incident voltage

α2 Ratio of the voltage imposed across the reactor of the healthy line (faulted pole) to the incident voltage

α3 Ratio of the voltage imposed across the reactor of the healthy line (healthy pole) to the incident voltage

α4 Ratio of the voltage imposed across the MMC station to the incident voltage

Vth1 Threshold of the line terminal voltage

Vth2 Threshold of the line reactor voltage

k1 Relaxation coefficient of Vth1

k2 Relaxation coefficient of Vth2

1

Chapter 1

1. Introduction

1.1. Statement of the Problem The Voltage-Sourced Converter (VSC) -based High Voltage DC (HVDC) power transmission

technology, [1]-[3], has been increasingly used for long distance transmission of bulk power, and

interconnection of AC systems and offshore/remote generation resources. The VSC has become

even more attractive for HVDC power transmission since introduction of its newest

configuration, i.e., the Modular Multilevel Converter (MMC) [4].

The VSC-based HVDC technology has only been used for point-to-point power transmission

although it enables realization of the HVDC grid which offers remarkable economic,

environmental, and technical advantages, as discussed in Section 1.3.1. The development of the

HVDC grid is constrained by the lack of a sufficiently high-speed1 and reliable2 relay for DC-

side fault protection. The relay should enable the HVDC grid to ride-through DC-side faults

before any converter station is blocked. This requires identification and isolation of the faulted

line before the power-electronic switches of the VSCs reach their current carrying limits.

The existing HVDC grid protection methods suffer from multiple technical issues as

discussed in Section 1.3.5. As of now only a few studies, [5]-[9], have reported general analyses

of the HVDC grid subject to DC-side faults. The technical literature does not provide in-depth

analysis of the transient response of the HVDC grid to DC-side faults, which is needed to design

a high-speed and reliable HVDC grid relay.

1 Refer to Appendix A for the definition 2 Refer to Appendix A for the definition

Chapter 1. Introduction 2

1.2. Thesis Objectives The main objectives of this research is to (i) develop a high-speed and reliable protection

method for fault detection and location in the HVDC grid, and (ii) provide a systematic

coordination method for the designed relays. The HVDC grid relay preferably should be:

● based on the state-of-the-art technologies that are currently being used in protection systems;

● non-pilot3;

● independent of the DC transmission line type, i.e., cable or over-head line;

● secure against fault resistance, harmonics, and noise.

1.3. Background This section highlights the features of the HVDC grid, compares the AC/DC converter

topologies used in HVDC transmission, briefly introduces the different HVDC system

configurations, and specifies the protection requirements of the HVDC grid.

1.3.1. Features of the HVDC Grid Accommodation of the power generation growth and/or reliable power delivery in mature

networks, such as those in Europe and North America, requires transmission system

reinforcement [10]. Building new power transfer corridors in such systems is impeded by the

very slow and politically controversial regulatory processes. Using AC cables is not a solution

either since it is not technically feasible for distances above fifty km [11]. In addition, expanding

the AC grids by adding new over-head lines or underground cables, often results in increased

short-circuit current levels and loop flow problems [12]. Modernization of the legacy grids using

HVDC transmission technologies can largely overcome the above-mentioned problems, [11],

particularly in view of selectively converting the existing AC lines to DC lines [10].

3 Refer to Appendix A for the definition


An HVDC grid (i) includes minimum of four VSC stations which are interconnected by a

network of HVDC over-head lines, cables, or a hybrid of over-head lines and cables, and (ii) can

provide continuity of service under N-1 contingency scenarios [10]. Integration of the HVDC

grid within the interconnected AC power system is emerging as a technically viable approach to

address a wide range of control and operational issues of the legacy AC power system. The

HVDC grid embedded in the AC system (HVDC-AC grid) can facilitate [5]:

● grid integration of multiple (off-shore) wind power plants;

● congestion management of major AC power corridors and loop-flow control;

● utilization of hydro power plants as large-scale storage media to enable high depth of

penetration of renewables;

● enhancement of angle/voltage stability and prevention of cascading events and blackouts.

1.3.2. HVDC Converter Topologies An HVDC transmission system can be based on the LCC or the VSC topologies. Unlike the

LCC-based HVDC technology, the VSC-based HVDC transmission system [10]:

1) does not require a change of voltage polarity to change the power direction;

2) does not require a strong AC system for reliable operation;

3) does not require large capacitor banks for reactive power compensation;

4) is more controllable, improves stability, and provides fault ride-through capability;

5) enables independent control of voltage, frequency, active power, and reactive power at its AC

terminals [10], [13], [14].

Due to the technical issues associated with integration of the LCC to the HVDC grid [10], the

future HVDC grids are expected to be mainly based on the VSC technology. Thus, this study

only focuses on the VSC-based HVDC grid.

The VSC-based HVDC transmission system can be based on two-level, three-level or

multilevel converters. The two-level and three-level converters suffer from higher conversion

loss, i.e., lower efficiency, and expose the interfacing transformer to high voltage stresses [15].

The existing multilevel converter configurations are categorized as [12]:

● diode clamped or Neutral Point Clamped (NPC) converter

● Flying Capacitors (FC) or capacitor clamped converter

● cascaded H-bridge converter

● MMC

Chap

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Table 1.1: RECENT MMC-HVDC TRANSMISSION PROJECTS BY SIEMENS

Project name Location Power rating Supplier DC voltage level Link Status

Trans Bay Link CA, USA 400 MW Siemens ±200 kV DC 85 km submarine cable Commissioned in 2010

INELFE Spain-France 2×1000 MW Siemens ±320 kV DC 65 km underground cable Scheduled for operation in 2015

BorWin2 Germany 800 MW Siemens ±300 kV DC 200 km submarine cable Scheduled for operation in 2015

HelWin1 Germany 576 MW Siemens ±250 kV DC 130 km submarine cable Platform installed in 2014

SylWin1 Germany 854 MW Siemens ±320 kV DC 205 km submarine cable Scheduled for operation in 2015

HelWin2 Germany 690 MW Siemens ±320 kV DC 130 km submarine cable Scheduled for operation in 2015

BorWin3 Germany 900 MW Siemens ±320 kV DC 160 km submarine cable Scheduled for 2015-20

For the NPC with a high number of levels, voltage balancing is a challenging task [16]. It

also requires a large number of clamping diodes that increases its cost and configuration

complexity [16], [17]. Thus, the number of levels for an NPC converter is limited to about seven

or nine [17].

For a high-level FC converter [16], [17]:

1) excessive number of storage capacitors with high energy storage capacity is needed;

2) the switching frequency and the switching loss are high for bulk power transmission;

3) the converter is costly due to the required bulky capacitors.

The cascaded H-bridge converter with separate DC sources, [17], needs multiple independent

DC sources for real power conversions, and thus its applications are limited [16].

The applications of the recently introduced MMC is rapidly expanding in the HVDC

transmission systems [18]-[21]. Table 1.1 shows a list of the MMC-based HVDC transmission

projects delivered by only one manufacturer that are in service or scheduled for commissioning

in the near future [22]. Higher reliability [23]-[25], efficiency [23], [26]-[30], operational and

control flexibility [6], [30], scalability [23], modularity [23]-[25], [30], and lower harmonics

content [23], [24], [29]-[31], are the inherent characteristics of the MMC. Due to its

abovementioned advantages over the other VSC configurations the trends are towards the

application of the MMC [10]. Therefore, the focus of this study is mainly on the MMC-based

HVDC transmission systems.


An MMC can be based on half-bridge or full-bridge sub-module topologies. The full-bridge

MMC has the DC-side fault current blocking capability. However, it requires twice the amount

of semiconductor switches of a half-bridge MMC with equivalent ratings and thus is more costly

[10]. The is the main reason that the MMC-based HVDC transmission systems that are currently

in service or are scheduled for operation in the near future are all half-bridge type. In this study,

only the half-bridge MMC is considered for two reasons:

1) The HVDC grid relay is expected to enable clearing DC-side faults before any VSCs are

blocked. The two types of the MMC have identical behavior before their sub-modules are

blocked.

2) Although the full-bridge MMC has DC-side fault current interruption capability, it does not

offer selective protection of DC transmission lines. Thus, the HVDC grid would still need

DC Circuit Breakers (DCCB) even if the converters were all full-bridge MMCs. This

implies that the inherent fault current blocking capability of the full-bridge MMC may not

necessarily justify its extra cost in HVDC grids.

It should be noted that the term VSC-based HVDC stands for the HVDC transmission system

based on both the two-level and the multi-level converters including the MMC, in this document.

Therefore, any statement that refers to only the HVDC transmission systems based on the MMC

technology will use the 'MMC-based HVDC' terminology instead of the 'VSC-based HVDC'.

1.3.3. HVDC System Configurations An HVDC power transmission system can be based on the following configurations [10],

[32], [33]:

● symmetrical monopolar;

● asymmetrical monopolar with or without metallic return conductor;

● bipolar with or without metallic return conductor;

● a combination of the above configurations.

Depending on (i) the type of the fault, (ii) the grounding of the HVDC system, and (iii) the

configuration of the HVDC system, DC-side faults in the VSC-based HVDC grid fall into one of

the following two categories:


- Type-1: This type of fault significantly reduces the Thevenin equivalent resistance seen by

the converters at their DC-side terminals. Consequently, it results in a significantly high

steady-state current and a negligible steady-state voltage at the converter terminals and

on the faulted line.

- Type-2: This type of fault shifts the ground reference voltage in the DC system. The fault

results in a steady-state voltage rise on the opposite polarity lines and also causes transient

oscillations due to discharge of the stray capacitances between the faulted line and the

ground.

Type-1 consists of DC-side line-to-line faults and DC-side line-to-ground faults in effectively

grounded HVDC systems. Type-2 corresponds to the rest of the DC-side faults, i.e., line-to-

ground faults in HVDC systems that are not effectively grounded [10] and [32]. Therefore, a

relay that detects and locates both types of DC-side faults can successfully protect all of the

HVDC system configurations.

The majority of VSC-based HVDC systems to date are based on the symmetrical monopolar

configuration [10]. In addition, both Type-1 and Type-2 faults occur in a symmetrical monopolar

HVDC system that is not effectively grounded. Thus, this study only focuses on protection of the

symmetrical monopolar HVDC grid. However, the envisioned relay can be used to effectively

protect all the HVDC system configurations.

1.3.4. Requirements and Challenges of the HVDC Grid Protection Development of the VSC-based HVDC grid is significantly constrained by its DC-side fault

vulnerability and unresolved protection issues [6], [11], [13]. The VSC-based HVDC grid

requires relays to enable protection of its components against damages and increase the

reliability of the energy delivery [10], i.e., minimize the impacts of faults. During AC-side faults,

the control system of a VSC can effectively limit the AC-side and DC-side currents [7] and [34].

However, protection of the VSC under DC-side faults is more challenging. It is mentioned in

Section 1.3.3 and shown in Chapter 3 that depending on the grounding arrangement, the HVDC

system configuration, and the type of the fault, i.e., line-to-line or line-to-ground, a DC-side fault

results in over-current and/or over-voltage stresses on the HVDC system components.


The IGBT switches of the VSC have limited over-current withstand capability, [8], and thus

should be blocked upon detection of any over-current stress [10], [23]. Under (i) line-to-ground

faults in effectively grounded HVDC systems, and (ii) line-to-line faults, the DC-side current

rises until the VSC is blocked. Subsequently, the half-bridge MMC and the conventional VSC

both continue to feed the fault as an uncontrolled bridge rectifier [10]. Therefore, the fault should

be quickly cleared to prevent damages to the VSC and the DC transmission line.

Under a DC-side line-to-ground fault in an HVDC system that is not effectively grounded,

the voltage of the healthy line rises, as discussed in Chapter 3. Therefore, to minimize damages

to the line surge arresters and the risk of evolving faults this type of DC-side fault should also be

cleared in a timely manner.

Based on the above-mentioned requirements, a high-speed, secure4, dependable5, and

selective6 HVDC grid relay is needed to detect and locate the DC-side faults and minimize the

affected area, since a delayed or erroneous trip significantly reduces the reliability of the

supplied power.

Selective protection of the HVDC grid also requires the DCCB which must operate

significantly faster than the AC Circuit Breaker (ACCB) [10]. Without a selective relay and the

DCCB the entire HVDC grid must be de-energized to clear a DC-side fault or a fault inside a

converter, which adversely affects the reliability and limits the advantages of the HVDC grid.

The DCCB technology is an active area of research. Currently, there is no commercially

available DCCB for HVDC applications [9]. Indeed, a DCCB for HVDC based on solid-state

switches is technically feasible in principle, but the costs and the steady-state operation losses are

the limiting factors [9], [10]. Therefore, the DCCB of the future HVDC grid is expected to be

based on the hybrid technology, [35], i.e., a combination of solid-state and mechanical

components. The structure and operation principle of the hybrid DCCB are explained in detail in

Chapter 4. There is a shared confidence that a commercial high voltage DCCBs will be available

in a time frame of 5-10 years [9], [10].

4 Refer to Appendix A for the definition 5 Refer to Appendix A for the definition 6 Refer to Appendix A for the definition


The DCCB should interrupt the HVDC grid fault current before the current exceeds the

maximum breaking capacity of the breaker. However, the operating time of the hybrid DCCB

may not be less than the opening time of its fast mechanical switch [36], which is about 1 to 3 ms

[35]. Thus, currently it is necessary to place reactors in series with the DCCB to limit the rate of

change of the current during the breaker operating time [36].

It should be noted that the required operation speed of the HVDC grid protection system is

determined based on (i) the effects of DC-side faults on the operation of the converters, as

discussed in Chapter 4, (ii) the operation time and breaking capacity of the DCCB, and (iii) the

inductances of the line series reactors. Based on these constraints, it is shown in Chapter 5 that

the HVDC grid relay should locate the DC-side faults within about 1 ms after the fault inception.

Designing a reliable HVDC grid protection system faces the following challenges:

● Chapter 4 shows that (i) the DC-side fault voltage and current in the HVDC grid include

transient components caused by the electromagnetic wave reflections and the oscillations

caused by the energy-storing components of the converter station, (ii) these transients do not

considerably damp out within the time frame that the HVDC grid relay needs to make a

protective decision, (iii) during the relay operation time frame the magnitudes of the

aforementioned distortions are significantly larger than those of the corresponding steady-

state components. Thus, developing an HVDC grid fault location algorithm based on the

steady-state components of the measured signals is not practical.

Even if such a protection algorithm was available, unlike the AC distance relay it would only

estimate the fault loop resistance, and its accuracy would be affected by the fault resistance [10].

● Chapter 4 shows that to prevent cascading outages the operation delay of the HVDC grid

relay should not be considerably more than about 1 ms. This necessitates application of very

fast (short data-window) digital filters and high sampling rate. Thus, the relay should be

designed such that its reliability is not adversely affected by noise and disturbances.

● A realistic HVDC grid may include different VSC topologies and both cables and over-head

lines. Similar to the AC grids, its topology may also change due to disconnection of lines and

converters. Therefore, the performance of a reliable HVDC grid relay does not depend on the

type of the faulted line and should be robust7 against changes in the HVDC grid topology.

7 Refer to Appendix A for the definition


1.3.5. Overview and Shortcomings of the Envisioned HVDC Grid Protection Methods

Since the HVDC grid is an emerging technology, the few HVDC grid protection methods

that are reported in the existing technical literature are not mature and exhibit fundamental

technical problems.

The protection method of [37] is based on extracting the features of the fault current, i.e., rise

time, rate of change, and oscillation pattern. The faulted line is disconnected using fast

mechanical switches, after all HVDC lines are de-energized using semiconductor DCCBs.

Subsequently, the HVDC grid is re-energized. This method suffers from the following issues:

● The features of the current signal that are used for detection of the faulted line highly depend

on the fault location, fault resistance, line parameters, and grid configuration.

● This method is devised for the HVDC grids that consist of only two-level VSCs since it relies

on the voltage support from the DC-link capacitors of the VSCs.

● This method results in shut down of the entire HVDC grid for at least 100 ms, which

significantly affects the reliability of the supplied energy.

● Performance of this method is evaluated based on lumped models of the HVDC transmission

lines, which do not accurately represent long HVDC transmission lines.

In the “hand-shaking” method of [8] the entire HVDC grid is de-energized by blocking the

VSCs and tripping the ACCBs upon detection of a DC-side fault. Subsequently, at each

converter station the line that is more likely to be faulted, i.e., has the maximum positive current,

is disconnected using fast mechanical switches. This method assumes that the faulted line would

be disconnected at both ends since it is assumed to carry the highest currents among all the lines.

Subsequently, the HVDC grid is re-energized and the healthy lines are re-connected after the

voltage is restored. This method suffers from the following technical issues:

● Upon detection of any DC-side fault, the entire HVDC grid is de-energized and one line is

disconnected from every DC busbar, which results in long restoration time and significantly

affects the HVDC grid reliability.

● This method may lead to false detection of the faulted line when the fault takes place at the

remote end of one of two parallel lines.

● This method may fail to detect the faulted line if the HVDC grid includes both cables and

over-head lines.


A DC voltage divider (voltage reference measurement method) is used for fault distance

measurement in [7] and [38]. The performance of this method is highly affected by the fault

resistance since the measured line-to-ground voltage at the converter station includes the voltage

drop across the fault resistance. For ground faults at the remote end of the line, a small ground

resistance causes under-reaching of the relay, i.e., the relay considers the fault out of its

operation zone. In addition, this method is devised based on lumped HVDC line models.

Therefore, the voltage reflections, caused by the fault, are not taken into consideration.

The operation delay and distance estimation error of the iterative voltage reference

measurement method of [6] are highly sensitive to the ground fault resistance. Furthermore, the

performance of this method is not validated under realistic high-resistance fault conditions, i.e., it

is assumed that the remote-end converter is disconnected, which is not a realistic scenario.

The reliability of fault location based on traveling-wave may be influenced by reflections in a

large meshed grid [6]. Furthermore, the fault location method based on measuring the arrival

time of the first wave front results in a limited distance resolution. For instance, the protection

method of [39], which utilizes a sapling frequency of 1 MHz, offers a maximum accuracy of

about 300 m for the over-head line and about 150 m for the cable. Thus, it can make wrong

decisions under faults close to the ends of the line.

The HVDC grid fault location method of [40] is based on differential protection of the

HVDC lines and thus is a pilot protection approach, i.e., requires fast remote communication.

The non-pilot HVDC grid protection method of [36] is based on the rate of change of the

voltage at the line-side of the reactor connected in series with each DCCB. Although this

protection approach resolves most of the issues mentioned above, it is prone to false operation

due to amplification of noise by its derivative function. Using low-pass filters to remove the

noise is not an option since this protective approach relies on high frequency components of the

measured voltage.

It can be concluded that, due to lack of speed and/or reliability, the existing HVDC grid

protection methods are neither fully practical nor comprehensively addresses the relevant issues

and therefore needs to be enhanced.


1.4. Methodology The methodology to achieve the thesis objectives includes:

● Off-line time-domain simulation

Off-line time-domain simulation in the PSCAD-EMTDC platform is used to study the

transient response of the HVDC-AC grid test system to faults and disturbances, which is the base

for designing the proposed HVDC grid relay. The comprehensive performance evaluation of the

designed relay is also carried out using off-line time-domain simulation.

Time-domain simulation of a 401 level MMC represented by its detailed model, i.e.,

including its IGBTs and diodes, is not efficient. The reason is that the resulting large admittance

matrix must be inverted every time a switch changes state, which results in significantly long

simulation time [18]. Therefore, to reduce the number of nodes and switching elements, an

Enhanced Equivalent Model (EEM) of the MMC [41], is used in this study to decrease the

computational burden without compromising the accuracy of the results. The details of the

developed EEM are presented in Chapter 2.

Various DC-side faults in the HVDC-AC grid based on the proposed EEM are investigated to

determine the typical responses of the converters to DC-side faults. The acquired information

about the transient components of the voltage and current signals, measured at the two ends of

the DC cables and over-head lines, are used to design reliable DC grid relays.

● RTDS-based real-time Hardware-In-the-Loop (HIL) time-domain simulation

RTDS-based HIL time-domain simulation is used to verify practicality of the proposed

HVDC grid protection system, e.g., hardware implementation, and computational burden. The

real-time simulation enables interfacing the relay, which is implemented in an FPGA board, to

the HVDC-AC grid modeled in an enhanced version of the RTDS platform, to investigate and

verify performance of the proposed protection method.

1.5. Study Systems Two different study systems are used for time-domain electromagnetic transient studies:

1. MMC-based HVDC link test system

2. HVDC-AC grid test system


The former represents the France-Spain HVDC link and is used in Chapter 2 to verify

accuracy of the MMC EEM. The latter is used in Chapter 3 to study the transient response of a

large VSC-based HVDC grid embedded in the AC system, to AC-side and DC-side faults and

disturbances. The HVDC-AC grid transient response is used to design and verify acceptable

speed, security, and dependability of the HVDC grid Relay.

Detailed information of the aforementioned study systems is given in the Appendix B.

1.6. Thesis Layout The next chapters of this thesis are organized as follows:

■ Chapter 2 introduces the enhanced equivalent model of the MMC for time-domain

electromagnetic transient studies. Accuracy of the developed equivalent model is validated

under different operating conditions, i.e., power ramp-up, DC-side fault, and AC-side fault.

The effects of lower level approximation of an MMC, i.e., reducing the sub-module number,

on the accuracy of the simulation results is also investigated in Chapter 2.

■ Chapter 3 investigates the transient response of the HVDC-AC grid to AC-side disturbances.

■ Chapter 4 investigates the transient response of the HVDC-AC grid to DC-side disturbances.

The impacts of the DC reactors in series with the DC transmission lines are studied.

Moreover, the fault clearing performance of the hybrid DCCB in the HVDC grid is

evaluated. The results of the studies presented in Chapter 4 are used to identify the HVDC

grid protection requirements and constraints. The results provide the information necessary to

design the HVDC grid relay.

■ Chapter 5 develops the HVDC grid protection strategy. The DC-side fault response of the

HVDC grid is analyzed and the results are used to establish the principles of fault detection

and location in the HVDC grid. The acceptable performance, i.e., speed and reliability, of the

developed protection strategy under various fault scenarios and operating conditions is

verified through comprehensive off-line time-domain electromagnetic transient studies.

■ Chapter 6 uses HIL real-time tests to demonstrates the potential of the developed HVDC grid

protection strategy to be implemented in hardware. The relay, which is implemented in an

FPGA board, is interfaced with the HVDC-AC grid which is modeled in the RTDS platform.

■ Chapter 7 provides the summary and conclusions of the thesis and highlights its

contributions.

14

Chapter 2

2. Enhanced Equivalent Model of the MMC

2.1. Introduction The design and performance evaluation of the MMC for HVDC system applications, in

particular for the investigation of control and protection systems, require the MMC model for

digital time-domain simulation of the electromagnetic transients. Modeling of the MMC based

on detailed representation of the IGBTs, diodes, and bypass thyristors of its sub-modules is

neither feasible, due to the large number of switches that results in an excessive computation

burden [18], nor required for system-level studies. Consequently, significant effort has been

devoted to the development of the MMC equivalent model for system-level analysis of MMC–

based HVDC systems.

An MMC equivalent model based on the Thevenin equivalent circuit of the series-connected

sub-modules for the analysis of power system electromagnetic transients is introduced in [18].

When the DC-side fault condition is not being studied, the model of [18], which we refer to it as

the Basic Equivalent Model (BEM) in this paper, reduces the simulation computational burden

with no loss of accuracy. However, the blocking of the IGBT switches [10] under DC-side faults

is not taken into account in this model. The equivalent model of [19] represents the DC-side of

the MMC based on an approximate loss calculation. Consequently, its DC-side fault response

does not accurately match that of the 'detailed model', that is, the model based on representation

of the IGBT and diode switches of each sub-module by their nonlinear characteristics. Therefore,

the existing equivalent models of [18] and [19] do not accurately represent the MMC under DC-

side fault conditions.

Chapter 2. Enhanced Equivalent Model of the MMC 15

Upon detection of an over-current stress on the power-electronic switches of the MMC, its

IGBT switches are blocked [10] and [23]. Simultaneously, the bypass thyristor connected in

parallel with each sub-module is gated to protect the free-wheeling diodes from the surge

currents [23], [26], [31]. The proposed EEM accurately represents the MMC under both

unblocked and blocked states.

In this chapter an Enhanced Equivalent Model (EEM) of the MMC is proposed which

improves the BEM [18] by accurately representing the performance of the MMC under all

possible operating conditions, including DC-side faults. This is achieved by taking into account

the nonlinear characteristics of the free-wheeling diodes and the bypass thyristors to represent

the natural commutation of the current between the converter arms after the IGBT switches are

blocked. In addition, the proposed model provides a feature to decrease the computational time

for the MMC simulation, compared with the existing models, [18] and [19], without

compromising the accuracy. The aforementioned simplification is based on the assumption that

the off-state resistance of the switches is very large and approaches infinity.

2.2. Modeling Strategy In this section, the equivalent models of the MMC arm in the un-blocked state and the

blocked state are developed. A generalized MMC arm model is developed based on the

aforementioned two models to accurately represent the MMC behavior under all possible

operating conditions.

2.2.1. MMC Arm Model in the Un-blocked State Fig. 2.1 shows a circuit diagram of the MMC, based on half-bridge sub-modules. Each phase

of the MMC consists of an upper arm and a lower arm. Each arm is a series connection of

multiple sub-modules and a current limiting arm reactor. The sub-modules can be either half-

bridge or full-bridge VSCs. The AC terminals of the MMC are usually connected to the AC grid

through a DYn-connected transformer. A grounding device can be used to create a voltage

reference at the ungrounded side of the transformer (Fig. 2.1).

Since the sub-module capacitor voltages cannot be negative under un-blocked IGBT

conditions, only the gated switch in each sub-module, i.e., S1 or S2 in Fig. 2.1, conducts. This is

regardless of the direction of the arm current. Therefore, based on the BEM [18], each switch is

represented by the two-state resistances R1 and R2, Fig. 2.2. If a switch is gated, its corresponding


Fig. 2.1. Circuit diagram of a half-bridge symmetrical monopole MMC.

Fig. 2.2. BEM of each sub-module of the MMC

equivalent resistance is set equal to the on-state resistance Ron, otherwise, it is set equal to the

off-state resistance Roff. In addition, each sub-module capacitor is represented by an equivalent

voltage source VcEQ in series with resistance Rc. The values of the VcEQ and the Rc are [18]:

CtRc 2

, (2.1)

)(2)()( ttIRttVtV cccEQcEQ , (2.2)

where C is the sub-module capacitance, Δt is the simulation time-step, and Ic is the current

passing through the sub-module capacitor. The BEM uses the Thevenin equivalent circuit of the

sub-module, Fig. 2.2, to represent the MMC.


It should be noted that the voltage across each sub-module is always a positive value. The

reason is that the sub-module free-wheeling diodes simultaneously conduct and apply a short-

circuit across the capacitor whenever its voltage tends to be negative. This observation is

important during a DC-side fault, if the IGBTs are not blocked before the sub-module capacitors

fully discharge. Under such conditions, without considering the above-mentioned behavior, the

capacitors of the BEM begin to charge in the reverse direction. Therefore, the BEM algorithm is

modified to reset the sub-module capacitor voltage to zero whenever it tends to be negative.

Based on this modification, under un-blocked IGBT conditions, the BEM properly represents the

behavioral characteristic of the sub-module detailed model.

The BEM, with or without considering the above-mentioned modification, can be further

simplified to reduce the computation burden and the simulation time, without compromising the

accuracy. The typical values for the resistances Ron and Roff, associated with the BEM, are about

2 mΩ and 165~550 kΩ, respectively [42] and [43]. The value of Rc, for a typical MMC, with the

sub-module capacitance of 10 mF [9], varies between 50 µΩ and 50 mΩ corresponding to a

simulation time-step within the range of 1 µs to 1 ms. Consequently, there is always a significant

difference between the value of R1 in series with Rc and the value of R2. This implies that one can

assume Roff = ∞ without any practical impact on the numerical results of the sub-module

Thevenin equivalent resistance and voltage. This modeling strategy does not take into account

the sub-module capacitor discharge through R1 when the sub-module is in the off-state.

However, the aforementioned limitation has negligible impact on the results of the studies that

are performed in this research since the time-constant of the discharge is about 27 minutes.

The Thevenin equivalent resistance RTh of the sub-module in the on-state and the off-state,

for different time-step values, are given in Tables 2.1 and 2.2, respectively. To investigate the

most pessimistic scenario, the minimum value of Roff, i.e., 165 kΩ, is considered in this study.

Table 2.1 shows that the difference between the values of RTh and the value of the series

connection of R1 and Rc is negligible when the sub-module is in the on-state. Moreover, Table

2.2 demonstrates that the difference between the values of RTh and the value of R2 is negligible

when the sub-module is in the off-state. As a result, the following assumptions, without

compromising the accuracy of the results, are valid and applicable:

● a switch in the off-state can be represented by an open-circuit; ● a switch in the on-state can be represented by its Ron; ● Ic(t) is equal to the corresponding arm current when the sub-module is in the on-state,

otherwise, it is zero.


Table 2.1: Comparison of RTh with Rc+R1 for Different Simulation Time Steps (On-state)

Δt (µs) State Rc (mΩ) Rc+R1 (mΩ) RTh(mΩ)

1 On 0.05 2.05 2.049999975 10 On 0.5 2.5 2.499999962 100 On 5 7 6.999999703

1000 On 50 52 51.99998361

Table 2.2: Comparison of RTh with R2 for Different Simulation Time Steps (Off-state)

Δt (µs) State Rc (mΩ) R2 (mΩ) RTh(mΩ)

1 Off 0.05 2 1.999999975 10 Off 0.5 2 1.999999975

100 Off 5 2 1.999999975 1000 Off 50 2 1.999999975

These assumptions eliminate the need for current division and voltage division calculations at

each simulation time-step to determine the values of Ic(t) and the sub-module terminal voltage.

Obviously, this feature becomes more important when the developed equivalent model is used

for real-time simulation.

As a result of the above-mentioned simplifications, each of the MMC arms can be modeled

as the series connection of the arm inductor La, an equivalent voltage source VarmEQ, and the

equivalent resistance RarmEQ, where

)()( 1 tVtVni TharmEQ i . (2.3)

In (2.3), i is the sub-module index, n is the total number of sub-modules in the arm, and

onisSMiftVoffisSMif

tVicEQ

iTh

ii ).(

,0)( . (2.4)

Meanwhile,

onconarmEQ RnRntR )( , (2.5)

where non is the number of sub-modules in the on-state.

Chap

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Rc). Thus,

(2.6)

capacitor


When the arm current enters the sub-modules from terminal B, Fig. 2.3(b), the arm can be

represented by the resistance n×(Ron║Rthy), where Rthy is the on-state resistance of each thyristor.

In addition, Ic(t) should be set at zero in this case. The reason is that no current passes through

the sub-module capacitors and the equivalent capacitor voltage given by (2.2) should remain

unchanged for each sub-module.

2.2.3. Generalized MMC Arm Model Fig. 2.4 depicts the proposed generalized MMC arm model that represents each arm un

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