Non – overlapping Clock...
Transcript of Non – overlapping Clock...
Non – overlapping Clock Generator
By: Hem Doshi
Outline
• Introduction• Architecture
– Working functionality– Why?
• Test Logic Implementation• Conclusion
– Based on our need, and most proven on Silicon!
Conceptual circuit and Signal Flow
Del
ay
Delay Equations
Del
ay
Architecture
Highlights
• Conventional Design• Proven on Silicon• Usage of minimum size NAND and then scaling
Super Buffer to drive larger load.• Usage of Inverters to attain Non-Overlap.• # of Inverters in feedback controls Non-Ov-Time • Advanced clocks can be tapped out a couple
Inverters before delayed clock.• Easy knobs available to control Tnov and Tlag
Design Flow• Calculating Load Capacitance
– Major Contributing Factors• Gate Caps of all the transistors driven by clock
– Stage 1 through 6– Main Sample/Hold Circuit– Comparator of final stage… ?– Digital Decode buffers
• Parasitics– clock distribution network
» Fringe Component» Area Component
– What I haven’t consider• Drain Cap of PMOS/NMOS of final stage of inverter chain
– As it scales with the inverter chain itself– Have some margin and design to drive extra load
• Usage of minimum L– Realization of sharp edges – circumvents jitter @ distribution
• Total ‘W’ for final stage = Cload/(Lmin*Cox* 3)
Design Flow (Continued)• Distribute total W with 3:1 ratio between PMOS and
NMOS– Ensures symmetric rise and fall time– Assumes mobility ratio of 3:1 between Pmos and Nmos
• Continue shrinking W by factor of 3 until hit by minimum W supported by process
• Calculate the delay incurred by the driver chain• If required Non-Ov-time is greater ~ 4.9ns
– add series of minimum size inverters in the feedback chain to obtain required delay
• Advanced clock driver is some smaller then Delayed clock as load Cap is diff.
Total W for Stage 1
Total W for Stage 2
Total W for Stage 1-6
• Ø1 = 3 * (220+88) = 924 W• Ø2 = 3 * (220+88) = 924 W• Ø1’= 3 * (72) = 216 W• Ø2’= 3 * (72) = 216 W
Total W for S/H Circuit
Digital Decode and 7th stage
Parasitics
• Active Chip Area is 1×1 mm2
• Estimated Routing channel length in Metal 3 is– 1 mm + 1 mm + 0.4 mm = 2.4mm
• Metal 3 to Metal 3 capacitance Calculation– Total distance between Metal 3 and Substrate is
2.575 um– Distance between Clock Distribution channels is 2
µm..!– Not a huge difference, so a good estimate would be
to associate total fringe Capacitance to either Metal to metal or metal to Substrate Fringe.
Total Fringe and Area Component
Total Parasitic Capacitance is thus 141.12 + 350.4 = 491.42fF ≈ 500fF ≈ 0.5pF
Final Cap Calculation
Test Logic
• Implements Tri-state buffers to reduce/increase the delay in feedback path.
• Lay out inverter chains with different delay– Preliminary Desgin
• 3 chains (1 ns, 2 ns, 3 ns) delay
• Last inverter in each series will have ability to tri-state its output
• Succeeding chain will bypass the last inverter in preceding chain
• Test logic chains will have odd # of inverters.
Tri State Buffer
Proposed Test Logic Model
Test Logic model (Continued)
100011
010001
001010
000100
Chain4Chain3Chain2Chain1Sel(2)Sel(1)
OutputTest Input
Truth Table
Timing Calculations
• Worst Case OP-AMP Settling time Calculation:• Worst case SS corner UGBW for the OP-AMP is
250 MHz.• Worst-Case settling time• = = 17.825 nS• Worst Case Comparator Settling Time ≈ 3 ns• Total Worst Case time
• 3 + 17.825 = 20.825ns ≈ 21 ns
• Available max duty cycle is 50% of 20 MHz clock. Thus max time available is 25 nS.
FactorBFUGBW ..27××× π 4
12102507
6 ×××× π
Timing Calc (Contd.)
• Available theoretical margin = 25 – 21 = 4nS.• Equally dividing for between OPAMP and
Comparator settling makes on-time of clock = 20 nS.
• Required duty Cycle = 20/50 =40%• T-T corner Non-Overlap time is 5nS and
available margin would be ±2nS.
Process Corners
0.2970.2584.431.45TT27 temp
5 V
0.1670.1672.7850.991FF0 temp5.5 V
0.4240.3966.962.39SS85 temp
4.5 V
TfTrTnovTlag
Actual Supply
Testbench
Sizing of the Device
Testbench
Fall Time
Rise Time
Tlag
Tnov
Bad Wave !