New PSB Beam Control

New PSB Beam Control

A. Blas, P. Leinonen, J. Sanchez-Quesada Working group meeting 18/09/2009 1

1. Summary from previous meeting (27/8/09) 2. ADC comparison3. DAC comparison4. Memory comparison5. FPGA6. Daughter card interconnection7. MDDS and its PLL8. Analogue front-end

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New PSB Beam ControlSummary from previous meeting


• Vita 57 connector between daughter cards and motherboards?

• Clock signals from mother board?

• Clock connector 1394, eSATA or RJ45?

• Vita 57 front panel?

• tag and clock on separated twisted pairs sharing the same cable?


New PSB Beam Control ADC specifications


Expected specifications for the ADC:

• Resolution >= 14 bits. The present ADC has 14 bits and a signal to noise and distortion level (SINAD) below 71 dBFS. Although this value seems sufficient for accelerating sychlotrons as LEIR and the PSB, an higher value could be of interest for machine having a higher dynamic range in term of beam current like the AD or for accumulators.

• Sampling >= 80 Msps. 80 Msps is the present maximal value. Its is also the value that prevails in many accelerators worldwide. For narrow band cavities, the signal is typically mixed down to 20 MHz and then sampled at 80 MHz to get directly I/Q without further digital mixing. In a context where the direct sampling of the signals has been chosen it is wise to have the highest possible sampling frequency to remove constraints from the anti-alias filter. For example, at the PSB extraction, the h2 beam has a spectrum up to 60 MHz and any signal above the Nyquist limit should be lowered down to less than -96 dBc. It has to be kept in mind that the sampling frequency has a price in term of FPGA, the 80 Msps are marginally achieved now with a Stratix 1 chip. Keep also in mind that in a frequency swept accelerator, 80 MHz max sampling means 40 MHz min sampling. This latter value is the one to be used to dimension the analogue Nyquist filter.

•Low power to avoid a heat sink and a possibly required increase of the front panel size

•Low latency (pipeline delay < 100 ns at the maximum sampling rate) for more loop stability margins.


New PSB Beam Control Current ADC: Analog Devices AD9245


Current ADC AD9245:

14 bit/80MSPS. 366mW 3V single supply Input BW = 500MHz Data latency = 7 cycles Parallel CMOS interface SINAD -71.2 dBFS at 70MHz 5 x 5mm with 32 pins Latest revision 2006


New PSB Beam Control Alternative ADC: Analog Devices AD9268


AD9268:

Dual 16 bit/125MSPS. 375mW/per channel 1.8V single supply Input BW: 625MHz Data latency = 12 cycles Parallel CMOS/LVDS interface SINAD 77.8 dBFS at 70MHz 9 x 9mm with 64 pins Latest revision 2009


New PSB Beam Control Alternative ADC: National Semiconductor ADC16V130


ADC16V130:

Dual 16 bit/130MSPS. 650mW = 325mW/channel 3.3V analog and 1.8V digital supplies Input BW : 1.4GHz Data latency = 11 cycles Parallel CMOS/LVDS interface SINAD 77.5 dBFS at 70MHz9 x 9mm with 64 pins Latest revision 2009


New PSB Beam Control Alternative ADC: Linear LTC2209


LTC2208 (LTC2209):

Dual 16 bit/130MSPS (160MSPS)1.25W (1.45W) => 625mW/channel 3.3V single supply Input BW = 700MHz Data latency = 7 cycles Parallel CMOS/LVDS interface SINAD 77.4 dBFS at 70MHz 9 x 9mm with 64 pins Latest revision 2009


New PSB Beam Control Alternative ADC: Texas Instruments ADS5483


ADS5483:

Dual 16 bit/135MSPS. 2.2W (= 1100mW/channel !!) 5V analog and 3.3V digital power supplies Input BW = 485MHz Data latency = 5 cycles Parallel CMOS/LVDS interface SINAD 77.4 dBFS at 70MHz 9 x 9mm with 64 pins Latest revision 2009


New PSB Beam Control ADCs overall comparison


ADC comparison between the current ADC and alternative choices:

Manufacturer Part MSPS Bits Power / ch SINAD Input BW Psupply Pipeline delay

Analog Devices AD9245 80 14 0.366W 70dB 500MHz 3V 7

Analog Devices AD9268 125 16 0.375W 75.8dBFS 650MHz 1.8V 12

National ADC16V130 130 16 0.65W 76.3dBFS 1.4GHz 3V,1.8V 11

Linear LTC2208 130 16 1.25W 76.4dBFS 700MHz 3.3V 7

Linear LTC2209 160 16 1.45W 75.7dBFS 700MHz 3.3V 7

TI ADS5483 135 16 2.2W 76dBFS 485MHz 5v,3.3v 5

Manufacturer Part Max Vi InterfacePackage size /

ch Pins DNL +/- INL +/- Obsolence Price

Analog Devices AD92451V to 2V (p-

p) Parallel 5x5mm / 1 32 0.5 LSB 1.4 LSB Rev. 01/2006 ~ 30-40$

Analog Devices AD9268 2vpp Parallel/LVDS 9x9mm / 2 64 0.7 LSB 3.0 LSB Rev. 05/2009 136$

National ADC16V130 2.4vpp Parallel/LVDS 9x9mm / 1 64 0.45 LSB 1.5 LSB Rev. 04/2009 69$

Linear LTC2208 2.25vpp Parallel/LVDS 9x9mm / 1 64 0.3 LSB 1.2 LSB Rev. 07/2009 100$

Linear LTC2209 2.25vpp Parallel/LVDS 9x9mm / 1 64 0.3 LSB 1.5 LSB 124$

TI ADS5483 3vpp Parallel/LVDS 9x9mm / 1 64 0.5 LSB 3.0 LSB Rev. 07/2009 81.25$


New PSB Beam Control Current DAC: Analog Devices AD9754


Block diagram for current DAC AD9754: 14 bit/125 MSPS 185mW/1 channel Settling time = 35ns Propagation delay 1ns Single supply +5V SFDR, 82dBc (at 50 MSPS/1MHz) Parallel input CMOS/TTL 9.8 x 4.5mm for 28 pins Commercially available and cheap Latest release 1999 Used in communication, RF and DDS applications.

A variant: the AD9764 is used inour section by Daniel and José. It can be powered by a single +3V/45mW at the price of decreased performances (not specified in the datasheet).


New PSB Beam Control Current DAC: Analog Devices AD9754


Chip layout for current DAC AD9754:

AD9754 and AD9764 have the same chip layout.The dimensions are 9.8 x 4.5mm for 28 pins.


New PSB Beam Control Alternative DAC: Analog Devices AD9772A


Block diagram and chip layout for DAC AD9772A:

14 bit/160MSPS 1 channel/single power supply of 3.3V 272mW (+50% compared to present one) settling time < 11ns Propagation delay 17ns SFDR 82dBc (at 65MSPS/1MHz) Parallel input CMOS/TTL 9 x 9mm (double of current) with 48 pins Integrated interpolation circuit (x2/x4) Latest release in 2008


New PSB Beam Control Alternative DAC: Analog Devices AD9747


Block diagram and chip layout for AD9747: Dual 16b DAC /250 MSPS 315mW => 158mW per channel 3.3V analog and 1.8V digital power supplies Parallel LVCMOS interface SFDR 82 dBc (at 250 MSPS/20MHz) Chip dimensions 10 x 10mm/72 pins CSP case (pins not going outside the ship borders) Latest release in 2007

SAME power per channel 2 more bits Twice the speedAdditionally 10-bit auxiliary DACs for external offset nulling and gain scaling for full-scale current for 16-bit DACs 1 and 2


New PSB Beam Control Alternative DAC : Texas Instruments DAC5686


Block diagram for DAC5686:

Dual 16 bit DAC/500MSPS 445mW/223mW per channel 3.3V analog and 1.8V digital powerSupplies Settling time 12ns Propagation delay 2.5ns Parallel CMOS interface. SFDR 89 dBc at 52MSPS/14MHz using x4 interpolation and dual mode10 x 10mm with 100 pins Latest release in 2009 Integrated 2x-16x interpolation filters


New PSB Beam Control Alternative DAC : Texas Instruments DAC 5686


Chip dimensions 10 x 10mm with 100 pins.

Chip layout for DAC5686:




DAC5672:

14 bit dual converter /275 MSPS 330mW and 165mW/channel Settling time 20ns Propagation delay 1.5ns 3.3V analog and 3.3V digital powersupplies Parallel CMOS/TTL interface SFDR 83dBc (at 50MSPS/1MHz)10 x 10mm with 48 pins Latest release in 2009




Chip layout for DAC5672:

Chip dimensions 10 x 10mm and 48 pins.


New PSB Beam Control DAC overall comparison


Comparison between current DAC and alternative choices:

Manufacturer Part MSPS Bits Power / ch SFDR Psupply Prop. Delay [ns]

Analog Devices AD9754 125 14 0.185W 82dBc (at 50 MSPS/1MHz) 5.0V 1

Analog Devices AD9747 250 16 0.158W 82dBc (at 250 MSPS/20MHz) 3.3V,1.8V 2.8

Analog Devices AD9746 250 14 0.158W 82dBc (at 250 MSPS/20MHz) 3.3V,1.8V n/a

Analog Devices AD9772A 160 14 0.272W 82dBc (at 65 MSPS/1MHz) 3.3V 17

Analog Devices AD9764 125 14 0.170W 80dBc (at 50 MSPS/1MHz) 5.0V 1

TI DAC5672 275 14 0.165W 83dBc (at 50MSPS/1MHz) 3.3V, 3.3V 1.5

TI DAC5686 500 16 0.222W89dBc (at 52MHz/14MHz x4 interp.

Dual DAC mode) 3.3V,1.8V 2.5

Manufacturer Part InterfaceSettling

time Package size / ch Pins DNL +/- INL +/- Last revision PriceAnalog Devices AD9754 Parallel/CMOS/TTL 35ns 9.8x4.5mm / 1 28 0.5 LSB typ. 1.5 LSB typ. May-99 8.30$Analog Devices AD9747 Parallel/LVCMOS n/a 10x10mm / 2 72 2 LSB typ. 4 LSB typ. May-07 16.09 $Analog Devices AD9746 Parallel/LVCMOS n/a 10x10mm / 2 72 0.5 LSB typ. 1 LSB typ. May-07 13.41 $Analog Devices AD9772A Parallel/CMOS/TTL 11ns 9x9mm / 1 48 2.0 LSB typ. 3.5 LSB typ. Feb-08 15.13$Analog Devices AD9764 Parallel/CMOS/TTL 35ns 9.8x4.5mm / 1 28 1.5LSB typ. 2.5 LSB typ. Nov-99 7.94$

TI DAC5672 Parallel/CMOS/TTL 20ns 10x10mm / 2 48 3 LSB typ. 4 LSB typ. May-09 13.25$TI DAC5686 Parallel/CMOS 12ns 10x10mm / 2 100 9 LSB typ. 12 LSB typ. Jun-09 24.70 $


New PSB Beam Control Current memory: Cypress CY7C1061BV33


1M x 16 bit memory 10ns access time 3.3V power supply 0.990W power dissipation 54 pins in a ~22x17mm chip Latest revision 2009

10ns access time provides 100MHz sampling frequency.If we want to have higher speed, we should go under 10ns.


New PSB Beam Control Alternative memory: Cypress CY7C1480V33


1M x 18 bit memory 3ns access time (250MHz) 3.3V power supply 1.5W power dissipation 100 pins in a 20x14 mm chip Latest revision 2007

includes JTAG connectivity


New PSB Beam Control Alternative memory : Cypress CY7C1372D


1M x 18 bit memory 2.6ns access time (250MHz) 3.3V power supply 1.0 W power dissipation 100 pins in a 20x14 mm chip Latest revision 2006


New PSB Beam Control Alternative memory: Cypress CY7C1440AV33


1M x 36 bit memory 2.6ns access time 3.3V power supply 1.7W power dissipation(at 250MHz) 100 pins in a 20x14mmchip Latest revision 2008


New PSB Beam Control Alternative memory: Cypress CY7C1460AV25


1M x 36 bit memory 2.6ns access time 2.5V power supply 1.14W power dissipation (at 250MHz) 100 pins in a 20x14mmchip Latest revision 2008


New PSB Beam Control Alternative memory : Samsung K7A321830C


2M x 18 bit PSBSRAM 5ns access time 3.3V or 2.5V power supply 1.6W power dissipation 100 pins in a 20x14mm chip Latest revision 2008

PSBSRAM = synchronous pipelined burst SRAM memory used as a 2nd level cache of Pentium and Power PC based system


New PSB Beam Control Alternative memory: Samsung K7K1618T2C


1M x 18 bit DDR II memory 0.45ns access time 1.8V power supply 1.52 W power dissipation 165 pins in a 17x15mm chip Latest revision 2008


New PSB Beam Control Alternative memory : Samsung K7Q161862B


1M x 18 bit QDR memory 2.5ns access time 1.8V or 2.5V power supply 1.04W power dissipation 165 pins in a 15x13mm chip Latest revision 2007


New PSB Beam Control Alternative memory: Samsung K7N641845M


4M x 18 bit pipelined NtRAM memory 3.5ns access time 2.5V power supply Power dissipation 1.6W 100 pins in a 20x14mm chip Latest revision 2008

NtRAM = no turnaround random access memory utilizesall the bandwidth in any combination of operating cycles. Address, data inputs, and all control signals except outputenable and linear burst order are synchronized to input clock.


New PSB Beam Control Memory overall comparison


Manufacturer Model Bits Access time Chip size PowerOperating voltages Latest revision Price

Cypress CY7C1061BV33 1M x 16 10ns54 pin 22.313 x

11.735mm 0.990W 3.3 ± 0.3V 2009 ~38$Cypress CY7C1480V33 2M x 36 3ns 100 pin 22 x 16mm 1.5W 3.3V 2007 137.98$Cypress CY7C1372D 1M x 18 2.6ns 100 pin 20 x 14mm 1W 3.3V 2006 30.88$Cypress CY7C1440AV33 1M x 36 2.6ns 100 pin 20 x 14mm 1.7W 3.3V 2008 50$Cypress CY7C1460AV25 1M x 36 2.6ns 100 pin 20 x 14mm 1.14W 2.5V 2008 50$

SamsungK7A321830C (PSBSRAM) 2M x 18 5ns 100 pin 20 x 14mm 1.6W

2.5V or 3.3V ± 5% 2007 n/a

SamsungK7K1618T2C

(DDR II) 1M x 18 0.45ns 165 pin 17 x 15mm n/a 1.8V ± 0.1V 2008 n/a

SamsungK7Q161862B

(QDR) 1M x 18 2.5ns 165 pin 15 x 13mm n/a1.8V or 2.5V ±

0.1V 2007 n/aSamsung K7N641845M 4M x 18 3.5ns 100 pin 20 x 14mm 1.6W 2.5V ± 5% 2008 77-80$


New PSB Beam Control FPGAs


The current Stratix 1 FPGA is using a 130nm technology.•Its capacity in terms of logic cells and memory doesn’t allow the implementation of all the required circuitry.•Its price increases

The search for new candidates has been achieved within the Altera products line. This choice avoids the redesign of the Quartus files.3 different candidates issued from 3 different product families have been compared. Compilation and timing analysis were made implementing the same DDC circuit compiled with Quartus II software.Were compared to the current Stratix chip, a Cyclone III and a Stratix III chips. Both are engineered with a 65nm technology.

Stratix III device is pin compatible with numerous choices inside the family. LEs can beupgraded up to 203520. Additionally, cross-family migration is supported between Stratix III and Stratix IV E device families i.e. pin-to-pin compatible. F780 need to be used.

Cyclone III doesn’t offer the same speed grades as the Stratix families do, but they are available at a lower cost.

Family Device Available Les Consumed area Max. Freq. PriceStratix EP1S20F484C5 18,460 72% 126MHz 750$

Stratix III EP3SL50F780C3N 38,000 30% 140MHz 525$

Cyclone III EP3C55F484C6 55,856 23% 130MHz 212$


New PSB Beam Control FPGAs


This table shows the compatible devices within the Stratix and Cyclone families:Note that for stratix 3 there is also the possibility to get a C2 speed grade (not shown here).For the Cyclone 3, C6 is the maximum speed grade.

Stratix III compatibility list Cyclone III compatibility list

EP3SL50F780C3 EP3C16F484C6EP3SL50F780I3 EP3C40F484C6EP3SL70F780C3 EP3C80F484C6EP3SL70F780I3EP3SL110F780C3EP3SL110F780I3EP3SL150F780C3EP3SL150F780I3EP3SL150F780C3ESEP3SL200F780C3EP3SL200F780I3EP3SE260F780C3EP3SE260F780I3EP3SE50F780I3EP3SE80F780C3EP3SE80F780I3EP3SE110F780C3EP3SE110F780I3




1. Summary from previous meeting (27/8/09) 2. ADC comparison3. DAC comparison4. Memory comparison5. FPGAs6. Daughter card interconnection7. MDDS and its PLL8. Analogue front-end


New PSB Beam Control Daughter card interconnection


Connector stack heights 8.5 and 10 mm Low Pin Count (LPC) 160 pins and High Pin Count (HPC) 400 pins in a same connector LPC 68 and HPC 160 user definable pins Differential and single-ended signaling 3.3V, 12.0V, adjustable and reference voltage power supply pins Clock signal pins JTAG and I2C support pins MultiGigabit pins (up to 10Gb/s)

VITA 57 FMC standard:

In case we would like to adapt to the Vita 57 standard as a daughter card to motherboard interconnection, care should be taken that all the signals being used in the beam control find a location compatible with Vita 57 and its subset defined by the CO group.




High pin count connector




Low pin count connector




SIGNALS Vita57 FMC pinsDSP Address (I) [20..0]21 bits allow to access 2x 1Mword (1M for the memory and < 128 word for the registers)

LA02_P/N ->LA16_P/N + LA19_P/N ->LA23_P/N

DSP Data (I/O) [63..32]32 bits

HA02_P/N -> HA16_P/N + HA18_P/N -> HA23 + HB01_P/N -> HB10_P/N

DSP WRH (I), RDH (I), ACK (I), IRQ0 (O) 4 bits

LA00_P/N_CC, LA01_P/N_CC, LA17_P/N_CC, LA24_P/N

CRC Error (O), INIT DONE (O)2 bits

LA24_P/N, LA25_P/N

JTAG TMS(I), TCK(I), TDI(I), TDO(O), TRST(I) 5 bits

Dedicated pins on the low-pin count area of the connector

FPGA reload (I)1 bit

LA26_P/N

RF Clock(I), DSP Clock (I), 10MHz (I), 3 C2M Clocks

CLK0_C2M_P/N, CLK1_C2M_P/N, LA18_P/N_CCAll LVDS .

RF clock1 (O) + TAG, RF clock2 (O)3 MDDS specific M2C Clocks

CLK0_M2C_P/N, CLK1_M2C_P/N, HA00_P/N_CC

Power Supplies to be refined at the end of DC design+/- 5VA, +5VD, +3.3VD, +2.5V

4 pins with 3PV3 + 2 pins with 12P0V available on low pin countCO has defined +/-15V, +/-5V, and -2V pins!


New PSB Beam Control Digital Direct Synthesizer


Current device: AD9858

RefCLK up to 1GHzFout up to 400MHz

32bit frequency word resolution14bit phase offset resolution

10bit output DAC

Many unused functions as:Automatic frequency rampingInternal PLLInternal analog mixer

Stills being a reasonable option.In fully production state.Commercially available.




Alternative 1: AD9910



14bit output DAC

Internal PLL to be used with the reference clock: 7 bit divider, 1GHz internal VCO.

Cheaper than the former one.




Alternative 2: AD9912



14bit output DAC

Internal PLL multiplier sub-harmonic output spurious to be studied if used.

4uHz resolution.


New PSB Beam Control PLL Chip


The PLL is used to generate the 1 GHz REFCLK to the DDS from the 10 MHz reference.

Some DDS subsystems incorporate an internal PLL which can be used for this task, saving PCB room and costs…

The actual PLL being used is the ADF-4106, which is in full production state and is not an expensive part.

=> We can stay with the actual PLL hardware without any changes, as switching to another model seems not adding any special improvement.


New PSB Beam Control Receiver front-end


The present receiver front-end comprises a Nyquist filter, a broadband differential amplifier and an additional filter to lower the distortions caused by the varying input impedance of the switched capacitor S/H at the input of the ADC.

Each channel uses a different reference voltage source for the A/D converter.

Using a common reference voltage source would balance the gains and the dynamic range of all ADC’s.


New PSB Beam Control Receiver front-end: offset compensation


ADC input offset compensation:

The offset compensation on each analogue input can be automatic.

The procedure is as follow: When required by a special event, the analogue input is grounded while the ADC output value is read by the FPGA. This numerical value is the offset.

It can be memorized and subtracted to the value obtained during operation:It can also feed a DAC that creates a compensating analogue offset.

The analogue compensation has the advantage of keeping the entire dynamic range while the digital compensation doesn’t require any extra hardware.




The analogue offset compensation




The digital offset compensation




Possible architecture of the Nyquist Filter: the tunable active low pass filter

Needs more analysis…


New PSB Beam Control Receiver front-end: input filter


Response varying R from 10 to 1000 ohms in 10 steps: (phase –upper- mag. –lower-)

This is only an example… other slopes and cut-off frequencies are possible.


New PSB Beam Control Receiver front-end: input filter


Integration of the additional tunable filter in the input stage (equivalent for the output stages):

The tuning voltage is driven from a simple PWM DAC.


New PSB Beam Control Receiver front-end: signal switching elements


Switches:-PIN diodes: advantageous for high level signals but maybe too much noisy for small signals (Rdon typ. Of hundreds of ohm.)-FET and MOSFET: very low Ron (less than 1 ohm.) and large signal capabilities if carefully designed.-Integrated solution: ADG619 Good characteristics, rail to rail input signal levels tolerated (up to +-5.5 volts), Ron about 4 ohm. Usable up to 100MHz…-Other option: AD901


New PSB Beam Control Receiver front-end: signal switching elements


Highlights:

•6.5 ohm maximum ON series resistance•2.7 to 5.5 dual power supply•Rail to rail input signal operation•tON ~85nS –max-•tOFF ~400nS –max-•DC to 100MHz bandwith•1$ on big quantities…•MSOP and SOT-23 packages (in mm):

Integrated switch solution: ADG619/ADG620


New PSB Beam Control Conclusion


ADC: The AD9268 offers 2 more bits (16b) and the possibility to sample at 125 MHz (instead of 80 MHz). This means that the minimum sampling will be 62 MHz instead of 40 MHz. The price is 136 USD instead of 40 USD

DAC: The AD9747 offers 2 more bits (16b) for 16 USD instead of 8 USD

Memory: The CY7C1460AV25 offers 1M x 32b (instead of 16b) and 250 MHz sampling ( instead of 100 MHz) for 50 USD instead of 40 USD

FPGA: The Stratix 3 EP3SL50F780C3N makes it possible to implement the expected logic clocked at a higher frequency (140 MHz instead of 126 MHz) with a lot of headroom permitted with the pin compatible upgrades (more logic cells and higher speed grades), all this for a lower price (525 USD instead of 750).

DSP/daughter card interconnection: The hardware defined by the VITA 57 is promising in terms of rf features (2.5Gb/s) and mechanical aspects. The hardware can be made compatible with the low-pin count pin definition, but as the standard misses some features that we require, some high pin count pins need to be defined for our needs. Nevertheless these custom pins can be defined in conjunction with CO/BI so as to allow future collaborations.

Analogue front-end: The addition of a switch makes it possible to make a digital offset compensation. This will improve the S/R by eliminating the rf component at the output of the input mixer.

Front Panel: Vita 57 offers a nice front panel standard but no room for a clock connector.


New PSB Beam Control

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