Nanowires presentation

An Introduction to NanoWires

University of South AlabamaElectrical engineering department

And Their Applications

Amir DindarShoeb Roman

• Bottom-up assembled nanoscale electronics could hold the promise of powering future electronic devices that can outperform existing devices and open up totally new opportunities.

• It will require conceptually new device building blocks, scalable circuit architectures, and fundamentally different fabrication strategies.

• Central to the bottom-up approach are the nanoscale building blocks.

University Of South Alabama, EE Department

An Introduction to Nanowires and their applications

Introduction

• 1D nanostructures represent the smallest dimension structure that can efficiently transport

electrical carriers

• 1D nanostructures can also exhibit critical device function, and thus can be exploited as

both the wiring and device elements in future architectures for functional nanosystems

• In this regard, two material classes: semiconductor nanowires (NWs)

carbon nanotubes (NTs) have shown particular promise

Introduction



Single-walled NTs have been used to fabricate field effect transistors, diodes, and logic circuits.

Problems with Nanotubes to made devices:• Difficulties to control whether building blocks are

semiconducting or metallic • Difficulties in manipulating individual NTs

So, to date, device fabrication by NT largely is a random event, thus pose a significant barrier to achieving highly integrated nanocircuits.

Introduction



Advantages of Nanowires: • NW devices can be assembled in a rational and

predictable because:– Nanowires can be precisely controlled during synthesis, – chemical composition, – diameter, – length,– doping/electronic properties

• Reliable methods exist for their parallel assembly.

• It is possible to combine distinct NW building blocks in ways not possible in conventional electronics.

• NWs thus represent the best-defined class of nanoscale building blocks, and this precise control over key variables has correspondingly enabled a wide range of devices and integration strategies to be pursued

Introduction



• Semiconductor NWs have been assembled into a series of electronic electronics devices: – crossed NW p-n diodes, – crossed NW-FETs, – nanoscale logic gates and computation

circuits, – optoelectronic devices

• More general applications:– Interconnects for nano electronics– Magnetic devices– Chemical and biological sensors– Biological labels

Introduction



• Diameter of nanowires range from a single atom to a few hundreds of nanometers.

• Length varies from a few atoms to many microns

• Different name of nanowires in literature:– Whiskers, fibers: 1D structures ranging from several

nanometers to several hundred microns– Nanowires: Wires with large aspect ratios (e.g. >20), – Nanorods: Wires with small aspect ratios.– NanoContacts: short wires bridged between two larger

electrodes.

• Regarding to size (diameter) we have two different types of nanowires:– Classical nanowires– Quantum nanowires

Introduction



Different techniques can be generally grouped into four categories:

• Spontaneous growth:– Evaporation condensation– Dissolution condensation– Vapor-Liquid-Solid growth (VLS)– Stress induced re-crystallization

• Template-based synthesis:– Electrochemical deposition– Electrophoretic deposition– Colloid dispersion, melt, or solution filling– Conversion with chemical reaction

• Electro-spinning• Lithography (top-down)

Building Blocks Synthesis



General Idea:

• Anisotropic growth is required

• Crystal growth proceeds along one direction, where as there is no growth along other direction.

• Uniformly sized nanowires (i.e. the same diameter along the longitudinal direction of a given nanowire)

Building Blocks Synthesis, Spontaneous Growth



• Referred to as Vapor-Solid (VS) technique.

• Nanowires and nanorods grown by this method are commonly single crystals with fewer imperfections

• The formation of nanowires or nanorods is due to the anisotropic growth.

• The general idea is that the different facets in a crystal have different growth rates

• There is no control on the direction of growth of nanowire in this method

Spontaneous Growth,

Evaporation condensation



Spontaneous Growth,




(Picture from: “Nanostructures of zinc oxide,” by Zhon Lin Wang, http://www.materialstoday.com/pdfs_7_6/zhang.pdf)

Spontaneous Growth,




Mesoporous, single-crystal ZnO nanowires.


Spontaneous Growth,




Picture : Measuring the Work Function at a Nanobelt Tip and at a Nanoparticle surface, http://www.nanoscience.gatech.edu/zlwang/paper/2003/03_NL_2.pdf

Spontaneous Growth,




Ultra-narrow ZnO nanobelts.


• Differs from Evaporation-condensation

• The growth species first dissolve into a solvent or a solution, and then diffuse through the solvent or solution and deposit onto the surface resulting in the growth of nanorods or nanowires.

• The nanowires in this method can have a mean length of <500 nm and a mean diameter of ~60 nm

Spontaneous Growth,

Dissolution condensation



General Idea:A second phase material, commonly referred to as catalyst, is introduces to direct and confine the crystal growth on a specific orientation and within a confined area.

– Catalyst forms a liquid droplet by itself – Acts as a trap for growth species – The growth species is evaporated first and

then diffuses and dissolves into a liquid droplet

– It precipitates at the interface between the substrate and the liquid

Spontaneous Growth,

Vapor Liquid Solid Growth (VLS)



Spontaneous Growth,




Growth species in the catalyst droplets subsequently precipitates at the growth surface

resulting in the one-directional growth

Spontaneous Growth,




Picture : “A Non-Traditional Vapor-Liquid-Solid Method for Bulk Synthesis of Semiconductor Nanowires,” Shashank Sharma, and Mahendra K. Sunkara,

http://www.cvd.louisville.edu/Publications/recentpublications/proceedings_mrs_fall2001.pdf

Spontaneous Growth,




TEM and selected area diffraction image of a single crystal ZnO nanorod.(~20 nm width).

Pictures : “ZnO nanowire growth and devices,” Y.W. Heoa, D.P. Nortona, et al., Materials Science and Engineering R 47 (2004) 1–47

Spontaneous Growth,




Z-contrast scanning transmission electron microscopy image of a (Zn,Mg)O nanorod with a Ag catalyst particle at the rod tip.


General Idea:

• This is the very general method

• Use in fabrication of nanorods, nanowires, and nanotubes of polymers, metals, semiconductors, and oxides.

• Some porous membrane with nano-size channels (pores) are used as templates from conduct the growing of nanowires

• Pore size ranging from 10 nm to 100 mm can be achieved.

Template Base synthesis



• Electrochemical Deposition– Negative template– Positive template

• This is a self-propagating process

• This method can be understood as a special electrolysis resulting in the deposition of solid material on an electrode

• Only applicable to electrically conductive materials: metals, alloys, semiconductors, and electrical conductive polymers.

Template Base synthesis



Negative Template

• use prefabricated cylindrical nanopores in a solid material as templates

• There are several ways to fill the nanopores to form

nanowires, but the electrochemical method is a general and versatile method.

• Electrodeposition often requires a metal film on one side of the freestanding membrane to serve as a working electrode on which electrodeposition takes place

• If dissolve away the host solid material, free-standing nanowires are obtained.

Template Base synthesis,

Electrochemical Deposition



• The diameter of the nanowires is determined by the geometrical constraint of the pores

• Fabrication of suitable templates is clearly a critical first step





A porous Template





Picture: “Fabrication of Polypyrrole Nanowire and Nanotube Arrays,” Fa-Liang Cheng*, Ming-Liang Zhang and Hong Wang, http://www.mdpi.net/sensors/papers/s5040245.pdf

Nanowire array





Picture: “Fabrication of Polypyrrole Nanowire and Nanotube Arrays,” Fa-Liang Cheng*, Ming-Liang Zhang and Hong Wang, http://www.mdpi.net/sensors/papers/s5040245.pdf

nano wires grown in a 80nm template membrane after dissolution of the membrane.

75 nm

210nm

100nm

Advantages

• The ability to create highly conductive nanowires. Because electrodeposition relies on electron transfer, which is the fastest along the highest conductive path.

• electrodeposited nanowires tend to be dense, continuous, and highly crystalline in contrast to other deposition methods.

• the ability to control the aspect ratio of the metal nanowires by monitoring the total amount of passed charge.





Three typical stages in electrodeposition process:

stage I: corresponds to the electrodeposition of metal into the pores until they are filled up to the top surface of the membrane (stage I)

Stage II: the pores are filled up with deposited metal, metal grow out of the pores and forms hemispherical caps on the membrane surface

Stage III: When the hemispherical caps coalescence into a continuous film





stage I





Picture: Template Synthesis of Nanowires in Porous Polycarbonate Membranes: Electrochemistryand Morphology , http://www.phys.ens.fr/~bachtold/publication/wire-JPCB.pdf

stage II






stage III










•To have freely standing nanowires we have to remove the template hosts after forming the nanowires in the templates by dissolving away the template materials in a suitable solvent.

•If want to separate the nanowires from the metal films on which the nanowire are grown, a common method is to first deposit a sacrificial metal.





Positive Template Method

•Use wire-like nanostructures, such as DNA and carbon nanotubes as templates.

•Nanowires are formed on the outer surface of the templates

•Diameter of the nanowires is not restricted by the template sizes and can be controlled by adjusting the amount of materials deposited on the templates

•Removing the templates after deposition, wire-like and tube-like structures can be formed





DNA based template

DNA is an excellent choice as a template to fabricate nanowires because its diameter is ~2 nm and its length and sequence can be precisely controlledGeneral procedure:

Fix a DNA strand between two electrical contacts

Exposed to a solution containing some ions

Ions bind to DNA and are then form some nanoparticles decorating along the DNA chain





DNA based templateGeneral procedure:

•Fix a DNA strand between two electrical contacts

•Exposed to a solution containing some ions

•Ions bind to DNA and are then form some nanoparticles decorating along the DNA chain


Electrophoretic Deposition



Differs from electrochemical deposition in several aspectsThe deposit need not be electrically conductive

Particularly for oxide nanowires: SiO2, TiO2, Bi2O3, etc.

Different sizes of TiO2 nanorods grown in a membrane by sol electrophoretic deposition. Diameters: (A) 180 nm, (B) 90 nm, (C) 45 nm

Picture: “A study on the growth of TiO2 nanorods using sol electrophoresis,” S. J. LIMMER, T. P. CHOU, G. Z. CAO, University of Washington, http://faculty.washington.edu/gzcao/publications/papers/31.pdf


Electrophoretic Deposition



Method:

•over the surface of nanoparticles develops an electrical charge via some chemical techniques. This combination is typically called Counter-Ion

•Upon application of an external electric filed to a system of charged nanosize particle system, the particles are set in motion in response to the electric filed

•This type of motion is referred to as electrophoresis.

•The rest of this technique, in general, is the same as electrochemical deposition.


Surface Step-Edge Templates



General Idea•Atomic-scale steps on a crystal surface can be used as templates to grow nanowires.

•The method takes the advantage of the fact that deposition of many materials on the surface often starts preferentially at defect sites, such as surface step-edges.

•The problem is that these nanowires can not be easily removed from the surface on which they are deposited

Nanowires are promising materials for many novel applications

Not only because of their unique geometry, but also because they possess many unique physical properties, including :

– electrical – magnetic– optical– mechanical

Properties and Application of Nanowires



Different Nanowires

We can categorize different types of nanowires regarding to the materials as follows:

• Metal nanowires• Semiconductor nanowires (Silicon nanowires)• Oxide nanowires• Multi-segment nanowires• Semiconductor quantum wires




The changes in properties arise from quantum confinement.

• Quantum confinement describes how the electronic and optical properties change when the sampled material is in sufficiently small amounts, typically 10 nanometers or less.

• Specifically, the phenomenon results from electrons and holes being squeezed into a dimension that approaches a critical quantum measurement.




Properties and Application of Nanowires,

Magnetic Properties



• Actually the magnetic properties of nanowires depend on the wire diameter and aspect ratio

• It is possible to control the magnetic properties of the nanowires by controlling the fabrication parameters

• Remanence ratio, which measures the remanence magnetization after switching off the external magnetic field

• Coercivity, which is the coercive field required to demagnetize the magnet after full magnetization.

• Giant Magnetoresistance (GMR)

In a viscous solvent, magnetic field can be used to orient the growing nanowires.

Properties and Application of Nanowires,



Optical properties

• Controlling the flow of optically encoded information with nanometer-scale accuracy over distances of many microns, which may find applications in future high-density optical computing.

• Silicon nanowires coated with SiC show stable photoluminescence at room temperature

NanoElectronic Applications of nanowires



The most important application of nanowires in nanoelectronics is using them as junctions or as multi-segment nanowires or crossed nanodevices.

Potential application of nanowires is in:

• very dense logic• dense memory• optoelectronics• sensing devices

NanoElectronic Applications of nanowires



Sensing Devices

A structure for transport measurements sensor by nanowires


NanoElectronic Applications of nanowires,

Quantum wire Transistor



Recent advances in formation methods allowed the fabrication of silicon quantum-wire transistors

•The quantum wires have a width of 65 nm and are fully embedded in silicon dioxide.

•A coulomb staircase, that is, step-like conductance versus gate voltage, was observed at temperature below 4.2 K.

•Some techniques used Single electron Transistor based on a 30 nm wide Si NW, which can be operate at 77 K. The device showed clear single electron tunneling and well-defined single island and two tunnel junctions.


Single Electron Memory



•Single electron memory cells consume extremely low power and can be realized by using the coulomb blockade effect.

•Important components of such a device are a silicon nanowire as a channel, a silicon nanodot as a storage node, and a silicon nanogate as a control gate.

•To realize these memory devices, narrow Si NWs need to be generated.


Metal Semiconductor Junction



•Junctions between carbon nanotubes and silicon nanowires has been done.

•To fabricate NT/SiNW junctions, SiNWs are grown from the end of the NT tips.

•It has a characteristic the same as metal-semiconductor Schottkey diode.


Metal Semiconductor Junction



(Picture from: “Controlled growth and electrical properties of heterojunctions of carbon nanotubes and silicon nanowires,” Jiangtao Hu et al.

, http://cmliris.harvard.edu/publications/1999/nature399_48.pdf)


Metal Nanowire



SEM micrograph of single ZnO nanowire bridging two Al/Pt/Au Ohmic contact



Hierarchical Assembly Nanowires



First: methods are needed to assemble NWs into highly integrated arrays with controlled orientation and spatial position.

Second: approaches must be devised to assemble NWs on multiple length scales and to make interconnects between nano-, micro- and macroscopic worlds.

In this regard, there are two promising approaches:

Electrical field-directed assembly Fluidic flow-directed assembly.

Hierarchical Assembly Nanowires,

Electrical Field-Directed Assembly



•Electrical fields can be used effectively to attract and align NWs due to their highly anisotropic structures and large polarizabilities

•Can also be used to position individual NWs at specific positions with controlled directionality

•can be carried out in a layer-by-layer fashion to produce crossed NW junctions.

Limitations•The need for conventional lithography to pattern microelectrode arrays used to produce aligning fields

•The effect of fringing electric fields at the submicron length scales.

Hierarchical Assembly Nanowires,Electrical Field-Directed Assembly



E-field-directed assembly of NWs. (a) Schematic view of E-field alignment. (b) Parallel array of NWs aligned between two parallel electrodes. (c) Spatially positioned parallel array of NWs obtained following E-field assembly. The top inset shows 15 pairs of parallel electrodes with individual NWs bridging each diametrically opposed electrode pair. (d) Crossed NW junction obtained using layer-by-layer alignment with the E-field applied in orthogonal directions in the two assembly steps.

Picture: “Integrated nanoscale electronics and optoelectronics: Exploring nanoscale science and technology through semiconductor nanowires,”Yu Huang1,2,‡ and Charles M. Lieber3. Pure Appl. Chem., Vol. 76, No. 12, pp. 2051–2068, 2004.


Fluidic Flow-Directed Assembly



•NWs can be aligned by passing a suspension of NWs through microfluidic channel structures over a flat substrate, so all of the NWs are aligned along the flow direction.

•Can be used to organize NWs into more complex crossed NW structures, which are critical for building high-density nanodevice arrays, using a layer-by-layer deposition process.


Fluidic Flow-Directed Assembly



Fluidic flow-directed assembly of NWs. (a,b) Schematic (a) and SEM image (b) of parallel NW arrays obtained by passing a NW solution through a channel on a substrate; (c,d) Schematic (c) and SEM image (d) of crossed NW matrix obtained by orthogonally changing the flow direction in a sequential flow alignment process. (e,f) Schematic (e) and SEM image (f) of regular NW arrays obtained by flowing NW solution over a chemically patterned surface. (g,h) Parallel and crossed NW device arrays obtained with fluidic flow assembly.

Picture: “Integrated nanoscale electronics and optoelectronics: Exploring nanoscale science and technology through semiconductor

nanowires,”Yu Huang1,2,‡ and Charles M. Lieber3. Pure Appl. Chem., Vol. 76, No. 12,

pp. 2051–2068, 2004.

Nanoelectronic application of Nanowires,

Crossed Nanowire devices



The crossed NW structure can be configured into a variety of devices, such as diodes and transistors.

A p-n diode can be obtained by simply crossing p- and n-type NW.

Picture: “Indium phosphide nanowires as building blocks for nanoscale electronic and optoelectronic devices,” Xiangfeng Duan, http://www.phy.cuhk.edu.hk/~jfwang/PDF/2001 Nature InP NW.pdf





(c) Schematics illustrating the crossed NW-FET concept. (d)

Gate-dependent I-V characteristics of a cNW-FET formed using a p-NW as the

conducting channel and n-NW as the local gate. The red and blue curves in the inset show

Isd vs. Vgate for n-NW (red) and global back (blue) gates

when the Vsd is set at 1 V. The conductance modulation

(>105) of the FET is much more significant with the NW gate than that with a global

back gate (<10).

Picture: “Integrated nanoscale electronics and optoelectronics: Exploring nanoscale science and technology through semiconductor nanowires,”Yu Huang1,2,‡ and Charles M. Lieber3. Pure Appl. Chem., Vol. 76, No. 12, pp. 2051–2068, 2004.





SEM micrograph of ZnO nanowire Schottky diode and its I-V curve both in the dark and with UV illumination






SEM micrograph of fabricated FET.






SEM micrographs of ZnO MOSFET structure



Nanoscale Logic Gates and Computational Circuits



•Diodes and transistors represent two basic device elements in logic gates.

•Crossed NW p-n diodes and NW-FETs enable more complex circuits, such as logic gates to be produced.

•A two-input logic OR gate was realized using a 2(p) by 1(n) crossed NW p-n diode array

•A two-input logic AND gate can also be realized using two diodes and one NWFET

•Similarly NOR gate with three NWFETs in series


Nanoscale Logic Gates and Computational Circuits



Picture: “Integrated nanoscale electronics and optoelectronics: Exploring nanoscale science and technology through semiconductor nanowires,”

Yu Huang1,2,‡ and Charles M. Lieber3. Pure Appl. Chem., Vol. 76, No. 12, pp. 2051–2068, 2004.

CONCLUSION



Challenges:•The insufficient control of the properties of individual building blocks•Low device-to-device reproducibility•Lack of reliable methods for assembling and integrating building blocks into circuits

Advances:•Synthesis of nanoscale building blocks with precisely controlled chemical composition, physical dimension, and electronic, optical properties•Some strategies for the assembly of building blocks into increasingly complex structures•New nanodevice concepts that can be implemented in high yield by assembly approaches

Nanowires presentation

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