Nab DAQ + High Voltage Cage Chris Crawford Aaron Sprow.
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Transcript of Nab DAQ + High Voltage Cage Chris Crawford Aaron Sprow.
• Overview– DAQ requirements / selection process
• NI DAQ system– Architecture and hardware– Local and global triggers– Interfaces: GUI / Slow control / Postprocessor
• Contract with NI– SOW: firmware/software development– Hardware: 2-phased purchase + warranty
• Faraday cage
Outline
Event Structure100-750 keV electron, 100 ps systematic, 2 keV resolution, 1.6 kHz singles 30 keV (HV) proton, 12–40 μs TOF delay, 10 ns resolution, 200 Hz coinc.
Data rateCoincidence in adjacent pixel (7/127); accidentals from decay <1% in 40 us256 ch digitizer 100-250 MS/s sample rate, 14-16 bit ADC * 14 pixels * 4 us * 2 * 600 Hz = 34 MB/s = 20 TB/week w/o compression
Trigger schemeTrigger L1) DIGITIZER threshold, L2) FPGA readout, L3) CPU storage levels: separate pixels single particle decay coincidences
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DAQ System Requirements
digitizerFPGA (L1)
ADC30 kV
hits
PXI bus trigger lines fiberoptics
rear I/Omodule
trigger logicFPGA (L2)
readout (L3)
detector detector
hits
PXI bus trigger lines fiberoptics
rear I/Omodule
trigger logicFPGA (L2)
readout (L3)
readout (L2/L3)
✔ July 2013: development of test firmware and software✔ Aug 2013 – Apr 2014: testing of prototype systems at LANL✔ July 2014: hardware vendor selection: National Instruments MILESTONE for Q3 2014, achieved in Q2 Oct 2014: purchase order for complete mini-system (48 channels) Dec 2014: development at LANL UCNB on prototype detector/preamps Mar 2015: purchase order for remaining digitizer cards (208 channels)
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DAQ Schedule
digitizerFPGA (L1)
ADC30 kV
detector detector
Hardware specifications / test results
• FGPA processing power important for advanced trigger filters and global trigger logic
• Memory / bandwidth required for CPU trigger logic
CONCLUSION: the essential discriminator for Nab is NOT online energy resolution, but: CUSTOM TRIGGER and LOGIC DEVELOPMENT
Hardware Decision: NI-5171R• 8 channel, 14-bit ADCs at 250 MS/s
±0.2 – 5 V pp, 50 Ω input single-ended • 8 digital I/O at 50 MHz• Kintex-7 410T FPGA• 12 Gb DDR3 = 428 ms/ch• >3.2 GB/s to PXIe
• 10 MHz OCXO clock over fiber
• 12 GB/s PXIe backplane with clock/trig lines
• Fiber optic PXIe-PCIe bridge
Online Triggering Algorithms• High efficiency detection of events
– Cusp-like shape (step response amplification)• Background noise cancellation
– Symmetric (Gaussian noise cancellation)– Flat-top (finite rise time) + long average time for trigger– Baseline restoration (exponential constant)
• Recursive, real-time implementation
• All coincidence logic in simple C loop• At 50 kHz singles (2 ev/40 us), CPU load = 0.8%
Global Trigger Logic
Control/GUI• Features
– Pixel map to actively track pixels: https://db.tt/wix8Sy64 – Online spectra and waveforms– Event/data rates– Local/remote start and stop
Difference between trigger and post-processingData fit as it comes in (another computer/GPU)Linear/nonlinear fits (pulse height + exponential decay + pedestal + time)Will fit to optimized template pulse accounting for background noise spectrum
Fit Functions Weighted ResponseFunctions
Waveform Coefficients c2
Post-Processing
•Assisting with the development and documentation of system level requirements•Providing architecture/code reviews
Statement of Work
$23.8k (100 hr)•Design and implementation of the synchronization aspects of the system
•Design and implementation of the data storage/retrieval mechanisms
Hardware and Service ContractCost escalation to date: Baseline $282k 1 yr warranty + 1 spare + fiber NI original: $292k + 13k hardware+NRE + 3 yr warranty (67%disc) Final quote: $290k + 34k hardware+NRE + 5 yr warranty (36%disc)
Will need to use contingency to purchase warranty.Will put “operation at HV” working into Statement of Work will require extensive negotiation with NI to include in warranty contractNI “Big Physics” will purchase 1 digitizer for development and quick turnaround for warranty repair
Purchase sequence: (delivery date, 90% confidence level) 2014-11-21: Initial hardware, only 6 modules $75347.65 2015-01-23: Nonrecurring engineering: $23800.00 2015-03 ? Remaining 26 modules $225752.47
Will purchase and develop initial system for development / testing @ LANL / UCNBWill purchase remaining modules after complete verification of specifications.