Mpmc u1 ece_arun

UNIT-I

INTRODUCTION TO 8-BIT AND 16-BIT

MICROPROCESSORS – H/W ARCHITECTURE

M. M. Arun Prasath., AP/ECE 1

8085 INTRODUCTION


8085 INTRODUCTION

The features of INTEL 8085 are :

• It is an 8 bit processor.

• It is a single chip N-MOS device with 40 pins.

• It has multiplexed address and data bus.(AD0-AD7).

• It works on 5 Volt dc power supply.

• The maximum clock frequency is 3 MHz while

minimum frequency is 500kHz.

• It provides 74 instructions with 5 different addressing

modes.


8085 INTRODUCTION

It provides 16 address lines so it can access 2^16 =64K bytes of memory.

It generates 8 bit I/O address so it can access 2^8=256 input ports.

It provides 5 hardware interrupts:TRAP, RST 5.5, RST 6.5, RST 7.5,INTR.

It provides Acc ,one flag register ,6 general purpose registers and two special purpose registers(SP,PC).

It provides serial lines SID ,SOD.So serial peripherals can be interfaced with 8085 directly.


8085 PIN DIAGRAM


8085 PIN DESCRIPTION

Some important pins are :

AD0-AD7: Multiplexed Address and data lines.

A8-A15: Tri-stated higher order address lines.

ALE: Address latch enable is an output signal.It goes high when operation is started by processor .

S0,S1: These are the status signals used to indicate type of operation.

RD¯: Read is active low input signal used to read data from I/O device or memory.

WR¯:Write is an active low output signal used write data on memory or an I/O device.



READY:This an output signal used to check the status of output device.If it is low, µP will WAIT until it is high.

TRAP:It is an Edge triggered highest priority , non mask able interrupt. After TRAP, restart occurs and execution starts from address 0024H.

RST5.5,6.5,7.5:These are maskable interrupts and have low priority than TRAP.

INTR¯&INTA:INTR is a interrupt request signal after which µP generates INTA or interrupt acknowledge signal.

IO/M¯:This is output pin or signal used to indicate whether 8085 is working in I/O mode(IO/M¯=1) or Memory mode(IO/M¯=0 ).



HOLD&HLDA:HOLD is an input signal .When µP receives HOLD signal it completes current machine cycle and stops executing next instruction.In response to HOLD µP generates HLDA that is HOLD Acknowledge signal.

RESET IN¯:This is input signal.When RESET IN¯ is low µp restarts and starts executing from location 0000H.

SID: Serial input data is input pin used to accept serial 1 bit data .

X1X2 :These are clock input signals and are connected to external LC,or RC circuit.These are divide by two so if 6 MHz is connected to X1X2, the operating frequency becomes 3 MHz.

VCC&VSS:Power supply VCC=+ -5Volt& VSS=-GND reference.


8085 ARCHITECTURE


Arithmetic and Logical group

Accumulator: It is 8 bit general purpose register.

It is connected to ALU.

So most of the operations are done in Acc.

Temporary register: It is not available for user

All the arithmetic and logical operations are done in the temporary register but user can’t access it.

Flag: It is a group of 5 flip flops used to know status of various operations done.

The Flag Register along with Accumulator is called PSW or Program Status Word.


Arithmetic and Logical group

Flag Register is given by: S:Sign flag is set when result of an operation is negative. Z:Zero flag is set when result of an operation is 0. AC:Auxiliary carry flag is set when there is a carry out of

lower nibble or lower four bits of the operation. CY:Carry flag is set when there is carry generated by an

operation. P:Parity flag is set when result contains even number of

1’s. Rest are don’t care flip flops.

S Z X AC X P X CY


Register Group

Temporary registers (W,Z):These are not available for user. These are loaded only when there is an operation being performed.

General purpose:There are six general purpose registers in 8085 namely B,C,D,E,H,L.These are used for various data manipulations.

Special purpose :There are two special purpose registers in 8085:

1. SP :Stack Pointer.

2. PC:Program Counter.


Register Group

Stack Pointer: This is a temporary storage memory 16 bit register. Since there are only 6 general purpose registers, there is a need to reuse them .

Whenever stack is to be used previous values are PUSHED on stack and then after the program is over these values are POPED back.

Program Counter: It is 16 bit register used to point the location from which the next instruction is to be fetched.

When a single byte instruction is executed PC is automatically incremented by 1.

Upon reset PC contents are set to 0000H and next instruction is fetched onwards.


INSTRUCTION REGISTER,DECODER & CONTROL

Instruction register:When an instruction is fetched , it is executed in instruction register.This register takes the Opcode value only.

Instruction decoder: It decodes the instruction from instruction register and then to control block.

Timing and control:This is the control section of µP.It accepts clock input .


INTERRUPT CONTROL

It accepts different interrupts like TRAP INT5.5,6.5,7.5and INTR.

SERIAL IO CONTROL GROUP

• It is used to accept the serial 1 bit data by using SID

and SOD signals and it can be performed by using

SIM & RIM instructions.


8085 INSTRUCTION

SET


DATA TRANSFER GROUP

INSTRUCTIONS


DATA TRANSFER GROUP

1. MOV Rd, Rs.(Move data from Rs to Rd).

Example:

MOV C,B. Move the content of register B to C.

Initially After execution

B=10H. B=10H.

C=20H. C=10H.

Flags Affected :No flags affected.

Addressing mode: Register.

Total No. of Instructions: 49


DATA TRANSFER GROUP

2. MOV Rd, M (Move data from Memory to Rd).

Example:

MOV C,M. Move the content of Memory i.e. “H or L” to C.

Suppose the Data at memory pointed By HL pair at C200H is 10H.


H=C2,L=00,C=30H H=C2,L=00,C=10H.


Addressing mode: Register Indirect.



DATA TRANSFER GROUP

3. MOV M, Rs (Move data from Rs to Memory).

Example:

MOV M, B. Move the content of B register to Memory.


H=C2,L=00,B=40H C200=40H.

C200=10H B=40H





DATA TRANSFER GROUP

4. MVI R, Data.(Move Immediate data to Register).

Example:

MVI B, 30H. (Move the data 30 H to Register B)


B=40H B=30H


Addressing mode: Immediate.



DATA TRANSFER GROUP

5. MVI M, Data.(Move Immediate data to Memory).

Example:

MVI M, 40H. (Move the data 40H to Memory address specified in HL pair)


H=20H L=50H 2050H=40H

2050H=10H


Addressing mode: Register Indirect or Immediate.

Total No. of Instructions: 7 M. M. Arun Prasath., AP/ECE 24

DATA TRANSFER GROUP

6. LXI Rp,16 bit .(Load 16 bit data to Register pair Immediate).

Example:

LXI SP, C200H. (Load Stack pointer with C200H).


SP=C800H SP=C200H.





DATA TRANSFER GROUP

7. STA address.(Store Acc data to address).

Example:

STA C200H. (Move the data from Acc to C200H).

Suppose in Acc the data is 10H.


A=10H, C200=20H C200=10H , A=10H


Addressing mode: Direct.

Total No. of Instruction: 1


DATA TRANSFER GROUP

8. LDA address.(Store Address data to Acc).

Example:

LDA C200H. (Move the data from C200H to Acc).

Suppose in C200 the data is 20H.


A=10H, C200=20H C200=20H , A=20H





DATA TRANSFER GROUP

9. LHLD address.(Load HL pair with data from address).

Example:

LHLD C200H. (Move the data from C200 to HL pair).

Suppose at C200 the data is 20H,30H .


H=10H,L=20H H=30H,L=20H.

C200H=20H,C201H=30H C200H=20H,C201H=30H





DATA TRANSFER GROUP

10. SHLD address.(Store the data to Address from HL pair).

Example:

SHLD C200H. (Store the data to C200 from HL pair).


H=30H,L=60H H=30H,L=60H.

C200H=20H, C201H=40H C200H=60H,C201H=30H





DATA TRANSFER GROUP

11. XCHG (Exchange the data from HL pair to DE pair)

Example : XCHG


H=20H,L=30H, H=40H,L=70H.

D=40H,E=70H. D=20H,E=30H.


Addressing mode: Implied.



DATA TRANSFER GROUP

12. STAX Rp (Copies the contents of Acc into Memory location whose address is specified by the register pair)

Example : STAX B


BC=1020H. A=50H.

A=50H. 1020H=50H.

1020H=10H





DATA TRANSFER GROUP

13. LDAX Rp (Copies the contents of Memory location whose address is specified by the register pair into Acc)

Example : LDAX D


DE=2020H. A=30H.

A=10H. 2020H=30H.

2020H=30H





DATA TRANSFER GROUP

Example: Write a program to exchange contents of memory location D000H to D001H

LDA D000H Load Acc with data from D000

MOV B,A Move the data to B

LDA D001H Load Acc with data from D001

STA D000H Store Acc data at D000

MOV A,B Move B’s data to A STA D001H Store data from D000 to D001

RST Stop.


ARITHMETIC GROUP

INSTRUCTIONS


ARITHMETIC GROUP

1. ADD R (ADD register content with Acc and result in A ).

Example:

ADD C. (ADD the content of C with A).

Suppose the Data at C register is 10H.


C= 10H, A=10H A=20H, C=10H.

Flags Affected :All flags are modified.

Addressing mode: Register


ARITHMEIC GROUP 2. ADD M

(ADD H or L Reg content with Acc and result in A ).

Example:

ADD M. (ADD the content of HL with A).

Suppose the Data at memory pointed by HL register 1020H is 10H.


. H= 10H ,L=20H . H=10H,L=20H.

A=20H,C=10H. A=30H.




ARITHMETIC GROUP

3. ADI Data

(ADD immediate data with Acc and result in A ).

Example:

ADI 30H. (ADD 30H with A).


A=20H, A=50H.




ARITHMETIC GROUP

4. ADC R (ADD register content with Acc and carry and result in A ).

Example:

ADC C. (ADD the content of C with A with carry).

Suppose the Data at C register is 10H and carry is 01H.


. C= 10H ,A=10H A=21H,C=10H.




ARITHMETIC GROUP

5. ACI Data (the data in the instruction and the carry flag are added to the content of Acc result is stored in Acc).

Example:

ACI 10H. (ADD the data 10H and carry with A).


. A=10H A=21H.


Addressing mode: Immediate


ARITHMETIC GROUP

6. ADC M (ADD register content with Acc and carry and result in A ).

Example:

(A) (A)+(M)+CY

Or

(A) (A)+((HL))+CY


Addressing mode: Register Indirect


ARITHMETIC GROUP

7. DAD Rp (Add specified register pair with HL pair) Example:DAD D.(Add the content of E with L and that

of D with H register and result in HL pair) Suppose the content of HL pair is H=20H ,L=40H

and DE pair is D=30H, E=10H. Initially After execution H=20H ,L=40H H=50H ,L=50H D=30H, E=10H D=30H, E=10H Flags Affected :Only carry flag is modified. Addressing mode: Register.


ARITHMETIC GROUP

8. SUB R (Subtract register content from Acc and result in A ).

Example:

SUB B. (Subtract the content of B from A ).

Suppose the Data at B register is 10H .


. B= 10H ,A=20H A=10H,B=10H.




ARITHMETIC GROUP

9. SUI Data

(Subtract immediate data from Acc and result in A ).

Example:

SUI 30H. (Subtract 30H from A).


A=80H, A=50H.


Addressing mode: Immediate


ARITHMETIC GROUP

10. SUB M (Content of memory addressed by HL pair is subtracted from Acc. Result stored in Acc ).

Example:

(A) (A)-(M)

Or

(A) (A)-((HL))


Addressing mode: Register Indirect


ARITHMETIC GROUP

11. SBI Data (Subtract 8bit data in the instruction with carry and result in A ).

Example:

(A) (A)-(Data)-CY




ARITHMETIC GROUP

12. SBB R (Subtract register content from Acc with borrow and result in A ).

Example:

(A) (A)-(register)-CY




ARITHMETIC GROUP

13. SBB M (Subtract register content from memory with borrow and result in A ).

Example:

(A) (A)-(M)-CY


Addressing mode: Register indirect


ARITHMETIC GROUP

14. DAA (Decimal Adjust Accumulator) Example: MVI A,12H ADI 39H DAA .

This instruction is used to store result in BCD form. If lower nibble is greater than 9 ,6 is added while if upper nibble is greater than 9,6 is added to it to get BCD result.

Initially After execution 12+39=4B 12+39=51 in BCD form. Flags Affected :All flags are modified. Addressing mode: Register


ARITHMETIC GROUP

15. INR R (Increment register content by 1 ).

Example:

INR C. (Increment the content of C by 1).



C= 10H C=11H.

Flags Affected :All flags are modified except carry flag.



ARITHMETIC GROUP

16. INR M (Increment memory content by 1 ).

Example:

INR M. (Increment the content of memory by 1).

(M) (M)+1

Initially After Execution

HL=2010 2010=FA HL=2010 2010=FB




ARITHMETIC GROUP

17. INX Rp (Increment register pair content by 1 ).

Example:

INX SP (Increment the content of Stack pointer pair by 1).

INX B. (Increment the content of BC pair by 1).

Suppose the Data at BC register is 1010H and SP is C200H


BC= 1010H BC=1011H.

SP=C200H SP=C201H.

Flags Affected :No flags are modified.



ARITHMETIC GROUP

18. DCR R (Decrement register content by 1 ).

Example:

DCR C. (Decrement the content of C by 1).



C= 10H C=0FH.




ARITHMETIC GROUP

19. DCR M (Decrement memory content by 1 ).

Example:

INR M. (decrement the content of memory by 1).

(M) (M)-1


HL=2010 2010=FA HL=2010 2010=F9




ARITHMETIC GROUP 20. DCX Rp (Decrement register pair content by 1 ).

Example:

DCX SP (Decrement the content of Stack pointer pair by 1).

DCX B. (Decrement the content of BC pair by 1).

Suppose the Data at BC register is 1012H and SP is C202H


BC= 1012H BC=1011H.

SP=C202H SP=C201H.

Flags Affected :No flags are modified.



ARITHMETIC GROUP

Example:

Subtract data of C800 H from C200H.Store the result at 2C00.

LDA C800H

MOV B,A

LDA C200H

SUB B

STA 2C00H

RST1


ARITHMETIC GROUP Example: Write a program to perform 16 bit addition of

2134H & 4312H. Store answer at H & L registers.

MVI B,21H B=21H

MVI A,34H A=34H

MVI C,43H C=43H

MVI D,12H D=12H

ADD B A=34+21H

MOV L,A L=55H

MOV A,C A=43H

ADC D A=43+12H

MOV H,A H=55H

RST1 STOP.


LOGICAL GROUP INSTRUCTIONS


LOGICAL GROUP

1. ANA R (Logically ANDs the register content with Acc and result in Acc ).

Example:

ANA C (AND the content of C with Acc).



C= AAH ,A=0FH A=0AH,C=0FH.

Flags Affected :S,Z,P are modified Cy=reset, AC=set.

Addressing mode:Register.


LOGICAL GROUP

2. ANA M (Logically ANDs the content of memory location pointed by HL register pair with the contents of Acc and result in Acc ).

Example:

ANA M (AND the content of memory with Acc).

Suppose the Data at HL register (2050H) is B3H.


2050H= B3H 2050H= B3H

A=55H A=11H




LOGICAL GROUP

3. ANI Data (Logically ANDs immediate data with Acc and result in Acc ).

Example:

ANI 3FH (AND 3FH with Acc).


A=B3H A=33H




LOGICAL GROUP

4. XRA R (Logically XOR register content with Acc and result stored in Acc ).

Example:

XRA C (XOR the content of C with Acc).



C= 2DH ,A=AAH A=87H

Flags Affected :S,Z,P are modified Cy=reset, AC=reset.



LOGICAL GROUP

5. XRA M (Logically XOR memory content with Acc and result stored in Acc ).

Example:

XRA M (XOR the content of memory with A).

Initially HL=2050H, 2050H=B3H, A=55H

After execution A=E6H




LOGICAL GROUP

6. XRI Data (Logically XOR 8bit data with Acc and result stored in Acc ).

Example:

XRI 39H (XOR 39H with Acc).

Initially A=B3H

After execution A=8AH


Addressing mode:Immediate.


LOGICAL GROUP

7. ORA R (Logically OR register content with Acc and result stored in Acc ).

Example:

ORA B (OR the B register contents with Acc).


B=12H B=12H

A=AAH A=BAH

Flags Affected :S,Z,P are modified Cy=reset,AC=reset.



LOGICAL GROUP

8. ORA M (Logically OR memory content with Acc and result stored in Acc ).

Example:

ORA M (OR the memory content with Acc).


HL=2050H HL=2050H

2050H= B3H 2050H= B3H

A=55H A=F7H


Addressing mode:Register indirect.


LOGICAL GROUP

9. ORI Data (Logically OR immediate data with Acc and result stored in Acc ).

Example:

ORI 08H (OR 08H with Acc).


A=B3H A=BBH




LOGICAL GROUP

10. CMP R (Compare register content with Acc and result in Acc ).

Example:

CMP C (Compare the content of C with A).

A=B8H C=B9H

(A)=(A)-(R)

Here A<C so carry flag will set after the execution

Flags Affected :all flags affected.



LOGICAL GROUP

11. CMP M (Compare contents of memory location and the contents

of Acc and result in Acc ).

Example:

CMP C (Compare the content of C with A).

A=B8H HL=2050H 2050H=B8H

(A)=(A)-(M)

Here A=M so zero flag will set after the execution

Flags Affected :all flags are affected.

Addressing mode:Register indirect.


LOGICAL GROUP

12. CPI Data (Compare immediate data with Acc ).

Example:

CPI 30H (Compare the content of C with A).

Initially A=BAH

(A)=(A)-(data)

Here A>data so zero and carry flags will reset after the execution of the instruction

Flags Affected : all flags are affected..



LOGICAL GROUP

13. STC (it sets the carry flag=1).

Example:

Initially if carry flag =0

After executing this instruction it will set CY=1

Flags Affected : only carry flag



LOGICAL GROUP

14. CMC (it complements the carry flag=1).

Example:

Initially if carry flag =0 or 1

After executing this instruction it will set CY=1 or 0

Flags Affected : only carry flag



LOGICAL GROUP

15. CMA (it complements each bit of the accumulator).

Example:

Initially if A=88H

After executing this instruction it will be

A=77H

Flags Affected : no



ROTATE GROUP INSTRUCTIONS


ROTATE GROUP

1. RLC (this instruction rotates the contents of acc left by one position. B7 is placed in B0 and also in CY).

Example:

MOV A,57H.

RLC (Rotate accumulator left).


A=57H and CY=1 A=AEH and CY=0

Flags Affected :Only carry flag is affected.



ROTATE GROUP

2. RRC (this instruction rotates the contents of acc right by one position. B0 is placed in B7 and also in CY).

Example:

MOV A,9AH.

RRC (Rotate accumulator right).


A=9AH , CY=1 A=4DH, CY=0.


Addressing mode:Implied.


ROTATE GROUP

3. RAL (Rotate accumulator left with carry. B7 is placed in CY and CY is placed in B0).

Example:

MOV A,ADH.

RAL (Rotate accumulator left with carry).


A=ADH , CY=0 A=5AH, CY=1.




ROTATE GROUP

4. RAR (Rotate accumulator right with carry, B0 is placed in CY and CY is placed in B7 ).

Example:

MOV A,A3H.

RAL (Rotate accumulator left with carry).


A=A3H , CY=0 A=51H, CTY=1.




BRANCH GROUP INSTRUCTIONS


UNCONDITIONAL JUMP INSTRUCTIONS. JMP address

After execution, the address given in the instruction is moved to Program counter. Now the processor starts executing the instructions stored in this address

Example:

JMP C200H.

Processor starts executes from address C200H..

Flags Affected :No Flags are affected.


BRANCH GROUP


BRANCH GROUP CONDITIONAL JUMP INSTRUCTIONS. It checks a flag condition. If the flag condition is true then the

address given in the instruction is moved to program counter. Thus the program control is branched to jump address. If the flag condition is false, then the next instruction is executed.

There are 8 types of conditional jump instructions

1. JC – jump on carry (Jump if Carry flag is set)

2. JNC – jump on no carry (Jump if Carry flag is reset)

3. JZ – jump on zero (Jump if zero flag set)

4. JNZ – jump on no zero (Jump if zero flag is reset)

5. JPE – jump on parity even (Jump if parity flag is set)

6. JPO – jump on parity odd (Jump if parity flag is reset)

7. JP – jump on positive (Jump if sign flag reset )

8. JM – jump on minus (Jump if sign flag is set)



BRANCH GROUP UNCONDITIONAL CALL FROM ADDRESS

CALL address.

After this instruction the Program Counter is loaded with this location and starts executing and the contents of PC are loaded on Stack.

Example:

CALL 4200H.


Addressing mode: Immediate/Register


BRANCH GROUP

CONDITIONAL CALL FROM ADDRESS It checks for a flag condition. If the flag condition is true, then

the address of the next instruction is pushed to stack and the call address is loaded in program counter.

There are 8 conditional CALL instructions

1. CC – call on carry (Call if Carry flag is set)

2. CNC – call on no carry (Call if Carry flag is reset)

3. CZ – call on zero (Call if zero flag set)

4. CNZ – call on no zero (Call if zero flag is reset)

5. CPE – call on parity even (Call if parity flag is set)

6. CPO – call on parity odd (Call if parity flag is reset )

7. CP – call on positive (Call if sign flag reset )

8. CM – call on minus (Call if sign flag is set)

Addressing mode: Immediate/Register


BRANCH GROUP

UNCONDITIONAL RETURN

RET (Return to main program)

After this instruction the Program Counter POPs the PUSHED contents from stack pointer and starts executing from that address.

Example:

MOV A,C

RET


Addressing mode: Register Indirect .


BRANCH GROUP

CONDITIONAL RETURN It checks for a flag condition. If the flag condition is true, then

the program control returns to main program by poping the top of stack to program counter. If the condition is false then the next instruction is executed

There are 8 conditional RETURN instructions

1. RC – Return on carry (Return if Carry flag is set)

2. RNC – Return on no carry (Return if Carry flag is reset)

3. RZ – Return on zero (Return if zero flag set)

4. RNZ – Return on no zero (Return if zero flag is reset)

5. RPE – Return on parity even (Return if parity flag is set)

6. RPO – Return on parity odd (Return if parity flag is reset )

7. RP – Return on positive (Return if sign flag reset )

8. RM – Return on minus (Return if sign flag is set)

Addressing mode: Register indirect


BRANCH GROUP

RST (Restart instruction)

After this instruction the Program Counter goes to vector address and starts executing from that address .

It is also called as software interrupts.

There are 8 restart instructions

Example:

MOV A,C

RST 1. After this instruction the Program Counter goes to address 0008H

and starts executing from that address


Addressing mode: Register indirect.


BRANCH GROUP The addresses of the respective RST commands are:

RESTART

INSTRUCTION

VECTOR

ADDRESS

RST 0 0000H

RST 1 0008H

RST 2 0010H

RST 3 0018H

RST 4 0020H

RST 5 0028H

RST 6

RST 7

0030H

0038H


BRANCH GROUP

PCHL (Load program counter with HL contents)

(PC) (HL)

The contents of H and L are transferred in to the PC.

The contents of H are placed as the higher order byte of PC.

The contents of L are placed as the lower order byte of PC




STACK OPERATIONS


STACK OPERATIONS

1. PUSH Rp: (Content of register pair is pushed to SP.)

Register pairs can be BC,DE,HL and PSW.

Program Status Word=Flag register (High order register) and Acc (Low order register) together.

Example : PUSH B

Content in B to ((SP)-01) Content in C to ((SP)-02)

Initially B=1AH C=2BH SP=4053H

4053=30H 4052=40H 4051=50H

After Execution B=1AH C=2BH SP=4051H

4053=30H 4052=1AH 4051=2BH





STACK OPERATIONS

2. POP Rp (content of top of stack is moved to Reg. pair)

Example : POP D

Content in (SP) to E

Content in ((SP)+01) to D

((SP)+2) to SP

Initially D=1AH E=2BH SP=4051H

4053=30H 4052=40H 4051=50H

After Execution D=40H E=50H SP=4053H

4053=30H 4052=40H 4051=50H





STACK OPERATIONS

3. PUSH PSW: (Content of PSW is pushed to SP.)

Program Status Word=Flag register (High order register) and Acc (Low order register) together.

Example : PUSH PSW

Initially A=20H FLAG=80H SP=4053H

4053=AAH 4052=BBH 4051=CCH

After Execution A=20H FLAG=80H SP=4051H

4053=AAH 4052=20H 4051=80H





STACK OPERATIONS

4. POP PSW (content of top of stack is moved to PSW)

Example :

POP PSW

Initially A=1AH FLAG=2BH SP=4051H

4053=AAH 4052=BBH 4051=CCH

After Execution A=BBH FLAG=CCH SP=4053H

4053=AAH 4052=BBH 4051=CCH





STACK OPERATIONS

5. SPHL (Content of HL pair is moved to Stack Pointer)

Example : SPHL


SP=1050H SP=1324H

H=13H H=13H

L=24H L=24H





STACK OPERATIONS

6. XTHL (Exchange the contents between HL pair and Memory or Stack pointer)

Example : XTHL


SP=2000 (Memory Address) SP=2000

H=20H H=25H

L=30H L=15H

Memory Memory

2000=15H 2001=25H 2000=30H 2001=20H



Total No. of Instruction: 1 M. M. Arun Prasath., AP/ECE 94

INPUT/OUTPUT INSTRUCTIONS


I/O GROUP

1. IN 8 bit address (Move the data from address to Acc)

Example: IN 80H

Move the data from 80H port address to Accumulator.

Suppose data at 80H is 39H.


A=20H. A=39H




I/O GROUP

2. OUT 8 bit address (Move the data from Acc to address)

Example: OUT 80H

Move the data from Acc to port address 80H.

Suppose data at Acc is 39H.


A=39H. 80=10H. A=39H,80=39H.




MACHINE CONTROL INSTRUCTIONS



1. DI – Disable Interrupts.

The interrupt enable flip-flop is reset and all the interrupts except the TRAP are disabled. No flags are affected.

Example: DI

2. EI – Enable Interrupts.

The interrupt enable flip-flop is set and all interrupts are enabled. No flags are affected. This instruction is necessary to re-enable the interrupts (except TRAP).

Example: EI



3. HLT – Halt program execution

The CPU finishes executing the current instruction and halts any further execution.

An interrupt or reset is necessary to exit from the halt state.

Example: HLT

4. NOP – No Operation

No operation is performed. The instruction is fetched and decoded. However no operation is executed.

Example: NOP



5. SIM – Set Interrupt Mask

This is a multipurpose instruction and used to implement the 8085 interrupts RST7.5, 6.5, 5.5, and SOD (serial data output). The instruction interprets the accumulator contents as follows.

Example: SIM



6. RIM – Read Interrupt Mask

This is a multipurpose instruction used to read the status of interrupts 7.5, 6.5, 5.5 and read serial data input bit. The instruction loads eight bits in the accumulator with the following interpretations.

Example: RIM


INTERRUPTS IN 8085


INTERRUPTS IN 8085

Interrupt is a process where an external device can get the attention of the microprocessor.

Interrupts can be classified into two types:

1. Maskable Interrupts (Can be delayed or Rejected)

2. Non-Maskable Interrupts (Can not be delayed or Rejected)

Interrupts can also be classified into:

1. Vectored (the address of the service routine is hard-wired)

2. Non-vectored (the address of the service routine needs to be supplied externally by the device)


INTERRUPTS IN 8085

The 8085 has 5 interrupt inputs.

The INTR input The INTR input is the only non-vectored interrupt.

INTR is mask-able using the EI/DI instruction pair.

RST 5.5, RST 6.5, RST 7.5 are all automatically vectored. RST 5.5, RST 6.5, and RST 7.5 are all maskable.

TRAP is the only non-mask-able interrupt in the 8085 TRAP is also automatically vectored.


ADDRESSING MODES OF 8085



1. Immediate addressing:

Immediate data is transferred to address or register.

Example:

MVI A,20H: Transfer immediate data 20H to accumulator.

Number of bytes:

Either 2 or 3 bytes long.

1st byte is opcode.

2nd byte 8 bit data .

3rd byte higher byte data of 16 bytes.



2. Register addressing:

Data is transferred from one register to other.

Example:

MOV A, C: Transfer data from C register to accumulator.

Number of bytes:

Only 1 byte long.

One byte is opcode.



3. Direct addressing: Data is transferred from direct address to other register

or vice-versa.

Example:

LDA C200H: Transfer contents from C200H to Acc.

Number of bytes:

These are 3 bytes long.

1st byte is opcode.

2nd byte lower address.

3rd byte higher address.



4. Indirect addressing: Data is transferred from address pointed by the data in

a register to other register or vice-versa.

Example:

MOV A, M: Move contents from address pointed by M to Acc.

Number of bytes:

These are 3 bytes long.

1st byte is opcode.

2nd byte lower address.

3rd byte higher address.



5. Implied addressing:

These doesn’t require any operand. The data is specified in Opcode itself.

Example:

RAL: Rotate left with carry.

No. of Bytes: These are single byte instruction or Opcode only.


PROGRAMMING OF 8085


MVI C,00H LHLD 5300 XCHG LHLD 5302 DAD D JNC Loop INR C Loop: SHLD 5500 MOV A, C STA 5502 HLT

PROGRAM

• To perform 16 bit Addition


PROGRAM Write a program to transfer a block of data from one

location (4050H to 405FH) and Store the data in another location (4170H to 417FH).

LXI H,4050H

LXI B,4170H

MVI D,0FH

UP MOV A,M

STAX B

INX H

INX B

DCR D

JNZ UP

HLT


PROGRAM

Write a program to add 10 data bytes. Data is stored from locations 4200. Store result at 4300H.

LXI H,4200 H MVI C, 0A H MVI A,00 H UP MOV B,M ADD B INX H DCR C JNZ UP STA 4300H HLT


COMPUTER AND ITS ORGANIZATION

Different units of the computer are shown in the block diagram To execute a particular instruction, mp has to perform the following

steps Read from memory Read from input device Write to memory Write to output device


CLOCK SIGNALS

All operations are controlled by clock signals. It provides basic timing signal for computer operations Clock period may vary from a few nanoseconds to a few microseconds Two edges (Leading edge and Trailing edge) and two states (Level 1

and Level 0) per clock period


PROGRAMMING SYSTEM

MACHINE LANGUAGE: lowest level programming language, instructions are described by binary patterns.

ASSEMBLY LANGUAGE: binary patterns are assigned mnemonics (short abbreviated names).

HIGH LEVEL LANGUAGE: machine independent language like C, PASCAL and FORTRAN.

ULTRA HIGH LEVEL LANGUAGE: it includes C++ and JAVA.

ASSEMBLER: it translates assembly language program to machine language program.

COMPILERS : it translates high level language program to machine language program.

OPERATING SYSTEM: interaction between the hardware and software is managed by a set of programs called operating system.


ADDRESS BUS, DATA BUS & CONTROL BUS

These buses are used to transfer information internally and externally to the microprocessor.

ADDRESS bus is UNIDIRECTIONAL. MP sends an address code to the memory or I/O.

DATA bus is BIDIRECTIONAL. Data or instruction codes are transferred between the MP and memory or I/O

CONTROL bus used to send or receive timing and control signals to communicate with other devices


TRISTATE BUS

Only one transmit at any particular instant.

Three-state, tri-state, or 3-state logic allows an output port to assume a high impedance state in addition to the 0 and 1 logic levels, effectively removing the output from the circuit. This allows multiple circuits to share the same output line or lines (such as a bus).


http://en.wikipedia.org/wiki/High_impedance

http://en.wikipedia.org/wiki/Logic_level

http://en.wikipedia.org/wiki/Computer_bus

CLOCK GENERATION A clock generator is a circuit that

produces a timing signal (known as a CLOCK SIGNAL) for use in synchronizing a circuit's operation. The signal can range from a simple symmetrical SQUARE WAVE to more complex arrangements. The basic parts that all clock generators share are a resonant circuit and an amplifier.


CONNECTING MICROPROCESSOR TO I/O DEVICES

I/O devices such as keyboards and displays are the very important communication channels to the outside world.

An I/O device can be interfaced with the MP either as I/O Mapped I/O (also called Isolated I/O [or] Port

Mapped I/O)

or

Memory Mapped I/O (MMIO)


CONNECTING MICROPROCESSOR TO I/O DEVICES I/O MAPPED I/O:

I/O devices are identified by port numbers, and memory locations are identified by addresses.

Separate memory and I/O signals, there is no confusion between device address and memory address.

I/O port to ACC then ACC to REG it wastes one instruction


CONNECTING MICROPROCESSOR TO I/O DEVICES

MEMORY MAPPED I/O: It uses the same address bus to address both memory and I/O devices

More compact and more efficient handling of I/O devices can be achieved if they are interfaced to MP in this way.

The I/O device is treated as memory location this interface is called MMIO


DATA TRANSFER SCHEMES

Synchronous Data Transfer:

Synchronous means “at the same time”. In this format of data transfer transmitter and receiver device are synchronized with the same clock pulse.

This type of data transfer format is used in between the devices that match in speed.

This method is invariably used in between memory and microprocessor as they are compatible.

Asynchronous Data Transfer: -

Asynchronous means “at a regular interval”. In this method data transfer is not based on predetermined timing pattern in this technique the status of the IO device is checked by the microprocessor before the data is transferred.

This method is invariably used in between microprocessor and IO devices



MODES OF DATA TRANSFER

THE MICROPROCESSOR receives or transmits binary data in either of two mode:-

1. PARALLEL MODE

In a parallel mode , the entire word is transferred at one time .the device commonly used for data transfer are keyboards, seven segment LEDs, data converters and memory.

2. SERIAL MODE

In the serial mode , data are transferred one bit at a time over a single line between the microprocessors and a peripheral. It is commonly used with peripherals such as CRT terminals , printers, cassette tapes and modems for telephone.



PARALLEL MODE

1. PROGRAMMED I/O:

Data transfer is controlled by the user program being executed. Depending on the type of device, data transfer may be synchronous or asynchronous.

Synchronous takes place when I/O device matches speed with the processor.

Asynchronous takes place when speed do not match.

2. INTERRUPT I/O:

The MP initiates the device, when the device is ready to transmit or receive the data, it sends an interrupt request signal. Depending upon the interrupt the data transfer will take place.

3. DMA:

Direct Memory Access (DMA) is a method of allowing data to be moved from one location to another in a computer without intervention from the central processor (CPU).




Direct Memory Access (DMA): • MP checks for DMA request signal once in each machine cycle. •I/O device sends the signal (DMA request). •MP tristates the Address, Data &Control Buses. •MP sends the acknowledge signal to the I/O device (DMA Acknowledge). •I/O device uses the bus system to perform the data transfer operation on memory after completion it withdraws the DMA request signal. •MP regains the control of buses and resumes normal operation

ARCHITECTURAL ADVANCEMENTS IN MP

1. PIPELINING:

Overlap the execution of several instruction in the single-cycle design, starting the next instruction before the previous one has run to completion, this leads to pipelined organization



2. CACHE MEMORY:

Improvements in memory access time by using one or more fast buffers named cache b/w the processor and the main memory.



CACHE MEMORY: Multilevel Cache system



3. MEMORY MANAGEMENT:

8086 is organized as segmented memory.

There are 4 segments available in 8086.

Code Segment, Data Segment, Extra Segment and Stack Segment

4. VIRTUAL MEMORY SYSTEM:

The complete program was divided in to fixed/variable size images and stored

in hard disk. The main memory was also divided into pages called frames of

the same size.


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8086 Microprocessor

.M.M. Arun Prasath., AP/ECE

135

Introduction to 8086 Microprocessor

Features:

1. Intel 8086 was launched in 1978.

2. It was the first 16-bit microprocessor.

3. It is available as 40-pin Dual-Inline-Package (DIP).

4 It requires +5 V power supply.

5. It consists of 29,000 transistors.

6. It operates in two modes Minimum and Maximum.

7. 8086 has a 20 bit address bus can access up to 220 Memory locations (1 MB).

8. It provides fourteen 16 -bit registers.

9. It has multiplexed address and data bus AD0- AD15 and A16 – A19.


8086 PIN DIAGRAM

136 .M.M. Arun Prasath., AP/ECE

137

Pin Description

1. AD15 ± AD0: ADDRESS DATA BUS - These lines constitute the time multiplexed memory/IO address and data bus.

2. NMI: NON-MASKABLE INTERRUPT: an edge triggered input which causes an interrupt request to the MP. NMI is not maskable internally by software.

3. INTR: INTERRUPT REQUEST

4. VCC & VSS: Power supply VCC=+5 V & VSS=GND reference.

5. RESET: causes the processor to immediately terminate its present activity. It restarts execution.

6. READY: is the acknowledgement from the addressed memory or I/O device that it will complete the data transfer.

7. TEST‾ : This input is examined by a ‘WAIT’ instruction. If the TEST pin goes low, execution will continue, else the processor remains in an idle state.


8. RD ‾ : READ - This signal on low indicates that the processor is performing memory or I/O read operation.

9. MN/MX ‾ :

• MINIMUM MODE - The 8086 processor works in a single processor environment. All control signals for memory and I/O are generated by the μp. • MAXIMUM MODE - is designed to be used when a coprocessor exists in the system. 8086 works in a multiprocessor environment. Control signals for memory and I/O are generated by an external BUS Controller

10. BHE ‾/S7 : BUS HIGH ENABLE - used to indicate the transfer of data over

the higher order ( D15-D8 ) data bus .

11. A19/S6,A18/S5,A17/S4,A16/S3 : 20 -bit Address Bus These are the time multiplexed address and status lines.

Pin Description


MINIMUM MODE: 1. INTA: INTERRUPT ACKNOWLEDGE

2. ALE: ADDRESS LATCH ENABLE – when HIGH µP is using AD0-

AD7,A19/S6,A18/S5,A17/S4,A16/S3 as address lines

3. DEN: DATA ENABLE. It is LOW when processor wants to receive data or processor is giving out data

4. DT/R‾: DATA TRANSMIT/RECEIVE. When High, data from µP to memory, When Low, data is from memory to µP.

5. M/IO‾: If High µP access Memory Device, If Low µP access I/O Device.

6. WR‾: WRITE data on memory or an I/O device.

7. HLDA: HOLD Acknowledge signal

8. HOLD: HOLD signal

Pin Description


MAXIMUM MODE 1. QS1, QS0: QUEUE STATES QS1 QS0 Indication 0 0 No operation 0 1 First byte of opcode from the Queue 1 0 Empty queue 1 1 Subsequent byte from the queue

2. S2‾, S1‾, S0‾: STATUS signals S2 S1 S0 Indication 0 0 0 Interrupt Acknowledge 0 0 1 Read I/O port 0 1 0 Write I/O port 0 1 1 Halt 1 0 0 Code Access 1 0 1 Read memory 1 1 0 Write memory 1 1 1 Passive

3. LOCK ‾: Other system bus master will be prevented from gaining the system bus 4. RQ‾/GT1‾: REQUEST/GRANT1 5. RQ‾/GT0‾: REQUEST/GRANT0

Pin Description


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8086 ARCHITECTURE


8086 ARCHITECTURE


8086 has two blocks Bus Interfacing Unit (BIU) and Execution Unit (EU).

The BIU performs all bus operations such as instruction fetching, reading and

writing operands for memory and calculating the addresses of the memory

operands.

BIU contains Instruction queue, Segment registers, Instruction pointer,

Address adder.

The EU executes instructions from the instruction system byte queue.

EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index

register, Flag register.

8086 Architecture


BUS INTERFACE UNIT (BIU) The function of BIU is to

Fetch the instruction or data from memory.

Write the data to memory.

Write the data to the port.

Read data from the port.

Instruction Queue:

1. To increase the execution speed, BIU fetches as many as six instruction bytes

ahead to time from memory.

2. All six bytes are then held in FIFO 6 byte register called instruction queue.

3. Then all bytes have to be given to EU one by one.

4. This pre fetching operation of BIU may be in parallel with execution operation

of EU, which improves the speed execution of the instruction.


EXECUTION UNIT (EU)

The functions of EU are

To tell BIU where to fetch the instructions or data from.

To decode the instructions.

To execute the instructions.

The EU contains the control circuitry to perform various internal operations.

A decoder in EU decodes the instruction fetched memory to generate different

internal or external control signals required to perform the operation.

EU has 16-bit ALU, which can perform arithmetic and logical operations on 8-

bit as well as 16-bit.

Both units operate asynchronously to give the 8086 an overlapping instruction

fetch and execution mechanism which is called as Pipelining. This results in

efficient use of the system bus and system performance.


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8086 REGISTERS

The 8086 microprocessor has a total of fourteen registers that are

accessible to the programmer. It is divided into four groups.

They are:

4 General purpose registers

4 Index/Pointer registers

4 Segment registers

2 Other registers


General Purpose Registers of 8086

• It can be used as 8 bit registers individually or can be used as 16 bit in pair.

1. AX Register: AX register is also known as accumulator register that stores

operands for arithmetic operations.

2. BX Register: This register is mainly used as a base register. It holds the starting

base location of a memory region within a data segment.

3. CX Register: It is defined as a counter. It is primarily used in loop instruction to

store loop counter.

4.DX Register: Data register is used to hold 16 bit data result


Index & Pointer Registers

• The 8086 has four other general purpose registers, two pointer registers Stack Pointer and Base Pointer and two index registers Source Index and Destination Index. Used to store the offset addresses

• An offset address Refers to a value added to a base address to produce a second address.


http://www.8085projects.info/image.asp?picture=Pointer and Index registers_2.gif

• Segment register is used to hold the upper 16 bits of the starting address for each of the segments.

• The four segment registers are:

1. Code segment (CS) : The CS register is used for addressing a memory

location in the Code Segment of the memory, where the executable program is

stored.

2. Data Segment (DS): The DS contains most data used by program. Data are

accessed in the Data Segment by an offset address or the content of other register

that holds the offset address.

3. Stack Segment (SS): SS defined the area of memory used for the stack.

4. Extra Segment (ES): used to hold the starting address of Extra segment.

Extra segment is provided for programs that need to access a second data

segment. Segment registers cannot be used in arithmetic operations.

Segment Register


Segment Register


1. Instruction Pointer (IP) is a 16-bit register. This is a important register which is used to control which instruction the CPU executes. The IP or program counter, is used to store the memory location of the next instruction to be executed.

Other Register

2. Flag Register contains a group of status bits called flags that indicate the status of the CPU or the result of arithmetic operations. There are two types of flags:

1. The status flags which reflect the result of executing an instruction. The

programmer cannot set/reset these flags directly.

2. The control flags enable or disable certain CPU operations. The programmer

can set/reset these bits to control the CPU's operation.


Status Flags: There are six status flags 1. The Carry Flag (C): 2. The Overflow Flag (O):This flag is set when the result of a signed arithmetic operation is too large to fit in the destination register. A value of 1 = overflow and 0 = no overflow. 3. The Sign Flag (S): 4. The Zero Flag (Z): 5. The Auxiliary Carry Flag (A): 6. The Parity Flag (P):


Control Flags: There are three control flags

1. The Direction Flag (D): Affects the direction of moving data blocks by such

instructions as MOVS, CMPS and SCAS. The flag values are 0 = up and 1 = down and can

be set/reset by the STD (set D) and CLD (clear D) instructions.

2. The Interrupt Flag (I): Dictates whether or not system interrupts can occur. The flag

values are 0 = disable interrupts or 1 = enable interrupts and can be manipulated by the

CLI (clear I) and STI (set I) instructions.

3. The Trap Flag (T): Determines whether or not the CPU is halted after the execution of

each instruction. When this flag is set (i.e. = 1), the programmer can single step through his

program to debug any errors. When this flag = 0 this feature is off. This flag can be set by

the INT 3 instruction.


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EXTERNAL MEMORY

ADDRESSING


155

EXTERNAL MEMORY ADDRESSING


156

EXTERNAL MEMORY ADDRESSING


• In 8086 the 1MB memory is physically organized as odd band and even

bank each of 512KB addressed in parallel by the processor.

• Byte data with even address is transferred on D7-D0 bus lines.

• Byte data with odd address is transferred on D15-D8 bus lines.

• The processor provides 2 enable single signals BHE¯ and A0 for

selection of odd and even memory banks.

• In 8-bit read from address, in even address BHE¯ remains high & in odd address BHE¯

pulsed low.

• In 16-bit read from address, (lower byte at even address) BHE¯ pulsed low in the first

cycle in this case, since A0=0, both the low and high order memory banks will be selected.

• In 16-bit read from address, (lower byte at odd address) BHE¯ is pulsed low, since A0=1,

only the high order memory banks will be selected, then BHE¯ remains high and A0=0, low

order memory bank will be selected. (More time taken for operation)

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BUS CYCLES


158

BUS CYCLES MEMORY or I/O READ FOR MINIMUM MODE



BUS CYCLES MEMORY or I/O WRITE FOR MINIMUM MODE

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SOME IMPORTANT COMPANION

CHIPS IN 8086


161

IMPORTANT COMPANION CHIPS


The following chips are used for the design of 8086 based system

Clock Generator Intel 8284

Bidirectional Bus Transceiver Intel 8286/8287

8 Bit Input Output Port Intel 8282/8283

Bus Controller Intel 8288 (only in MAXIMUM

mode system)

162



Clock Generator Intel 8284:

Provides a stable clock

Facility to synchronize clock signals of other 8086 MP in case of the

multiprocessor environment.

Reset signal in synchronization with clock as required by the 8086.

Wait state logic


IMPORTANT COMPANION CHIPS: Clock Generator Intel 8284



CYSYNC: Synchronization of signals in multiprocessor environment where all processors receive clock at EF1.

PCLK: Clock signal output for supporting circuits.

AEN1¯ & AEN2¯: To attribute bus priorities when both RDY1 and RDY2 are active. 8284 responds to RDY1 when AEN1 is low , similarly RDY2 when AEN2 is low

RDY1: Clock frequency

READY: Clock frequency

RDY2: Clock frequency

CLK: Connected to 8086/8088 CLK pin.

RESET: Generates the Reset output as required by 8086

RES¯: Reset logic input. External device can reset the 8086.

OSC: Oscillator output running at crystal or EF1 frequency. Used in multiprocessor system

F/C¯: If high clock at EF1 is taken, If low X1,X2 is taken

EF1: Alternate clock input

ASYNC¯: It selects either one or two stages of synchronization for RDY1 and RDY2 inputs. If low one level is selected. If high two levels are selected.

X1,X2: Clock frequency

GND & VCC: Connects to Ground & Power

166




167




A0-A7 are connected to MP address/data bus.

B0-B7 are connected to system bus of system.

When T (Direction Select) is Low: data at B pins is output via A pins

When T (Direction Select) is High: data at A pins is output via B pins

8286 transfer the data unaltered while the 8287 inverts the data at the time of transfer.

T pin is usually connected to DT/R¯ and OE¯ connected to DEN¯ of 8086.

OE¯ must be held low for actual data transfer to take place.

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169




8282 and 8283 are Unidirectional latch buffers

8282 does not alter the data but 8283 inverts the input data.

DI0-DI7 are data inputs and DO0-DO7 are data outputs.

When STB (input data strobe) is high, data on output pins track the data on input pins.

When STB is low the data is latched and remains unchanged.

When OE¯ is low the data is put on output lines

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Bus Controller Intel 8288

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It is used in maximum mode configuration of 8086.

Its main function is to decode the status line signals S0¯, S1¯, S2¯ and

to generate system bus control signals.

It has 2 modes of operation I/O Bus mode and System Bus mode.

When IOB = high 8288 goes to I/O bus mode.

When IOB = low 8288 goes to System Bus mode

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Effect of AEN1¯, IOB and CEN on control signals

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MAXIMUM MODE BUS CYCLE


174

8086 SYSTEM CONFIGURATION


175

MEMORY INTERFACING


Interfacing of 8086 MP to memory is the main step in the design of a MP

based system

The number of memory chips and the address space used will depend

on the application needs.

Its not necessary that the address space of any MP system should start

only from zeros, it may start at any boundary of 1KB

The diagram describes the memory address decoding using one

74LS138 decoder

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MEMORY INTERFACING: MEMORY ADDRESS DECODING


177

MINIMUM MODE SYSTEM

CONFIGURATION


178

MINIMUM MODE SYSTEM CONFIGURATION


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MINIMUM MODE SYSTEM CONFIGURATION


In a minimum mode 8086 system, the MP 8086 is operated in minimum mode by its MN/MX¯ pin to logic 1.

In this all the control signals are given out by the microprocessor itself.

There is a single processor in the minimum mode system. Remaining components are 8282 latches, 8286 bus transceivers and 8284 clock generator.

The 8282 latch is used to demultiplex the address/data bus lines to two separate address and data buses using ALE pin.

The 8284 clock generator provides CLK, READY and RESET signals to the 8086.

The data bus D0-D15 is bidirectional, in order to create a separate data bus from address/data bus, two 8286 bidirectional bus transceivers are used. DT/R¯ and DEN¯ output of 8086 are connected to 8286 as T and OE¯ respectively

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MAXIMUM MODE SYSTEM

CONFIGURATION


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MAXIMUM MODE SYSTEM CONFIGURATION


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MAXIMUM MODE SYSTEM CONFIGURATION


In a maximum mode 8086 system, the MP 8086 is operated in maximum mode by its MN/MX¯ pin to GND.

In this mode there may be more than 1MP in system configuration.

ALE and DEN are generated by 8288 controller.

The 8282 latch is used to demultiplex the address/data bus lines to two separate address and data buses using ALE pin.

The 8284 clock generator provides CLK, READY and RESET signals to the 8086.

The data bus D0-D15 is bidirectional, in order to create a separate data bus from address/data bus, two 8286 bidirectional bus transceivers are used. DT/R¯ and DEN¯ output of 8086 are connected to 8286 as T and OE¯ respectively

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INTERRUPT PROCESSING


INTERRUPT SERVICE ROUTINE (ISR)

While the CPU is executing a program, an interrupt breaks the normal

sequence of execution of instructions, diverts its execution to some other

program. After executed ISR, the control is transferred back again to the main

program which was being executed at the time of interruption.

The 8086 has 4 sources of interrupts:

Software or within-program logic

Single step condition

External logic as a non-maskable interrupt

External logic as a maskable interrupt

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DIRECT MEMORY ACCESS (DMA)


DMA in Minimum Mode (MN/MX¯=5v):

Two signals HOLD and HLDA are dedicated for DMA operation

When the external logic wishes to access the memory directly, it makes a request through high signal at HOLD pin, the 8086 samples the HOLD input at low-to-high transition and acknowledges the HOLD request through high-level at HLDA pin at the end of the cycle.

DMA in Minimum Mode (MN/MX¯=GND):

Two signals RQ¯/GT0¯ and RQ¯/GT1¯ are dedicated for DMA operation. (RQ¯/GT0¯ has the Highest Priority)

When the external logic wishes to access the memory directly, it makes a request through low signal at RQ¯/GT¯ pin, the 8086 samples the RQ¯/GT¯ input at low-to-high transition and acknowledges the DMA request at the end of the cycle.

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