mosfet paper

NOISE IN DEVICES AND CIRCUITS

Effects of body biasing on the low frequency noise ofMOSFETs from a 130 nm CMOS technology

M. Marin, M.J. Deen, M. de Murcia, P. Llinares and J.C. Vildeuil

Abstract: The impact of body biasing on the low frequency noise (LFN) performances of MOStransistors from a 130nm CMOS technology was investigated. The body-to-source voltage VBSwas varied from 0.5V to +0.5V for reverse and forward mode substrate biasing. Detailedelectrical characterisation was performed and the benets of the body bias analysed in terms ofcurrent and maximum transconductance variations. Noise measurements were rst performed atlow drain bias VDS=725mV and VBS=0V in order to discuss the noise origin in the devices.Results are in agreement with the carrier number uctuation theory DN for NMOS and with thecorrelated carrier numbermobility DNDm model for PMOS. Bulk bias dependence of the LFNwas investigated at VDS=VDD=71.2V. Signicant noise reduction of about 50% in both N andPMOSFETS was observed in the weak inversion regime when applying a forward body bias. Instrong inversion, the noise level was found to be approximately independent of the substrate biasVBS. An explanation of the main noise results based on McWhorters number uctuation theory isproposed.

1 Introduction

The demand for low-voltage, low-power electronics hasgrown rapidly due to the development of portableelectronics such as cell phones with single battery operationand laptops. If the dynamic power consumption of CMOScircuits can be directly reduced by scaling the supply voltageVDD (PdynpVDD

2 ), then the threshold voltage must bescaled accordingly (VTBVDD/3) so as not to degrade circuitspeed or operating logic noise margins. On the other hand,VT scaling is limited by the off-state current and staticpower consumption constraints. To circumvent this issue,new schemes such as the dynamic threshold voltageMOSFET [1, 2] (DTMOS) or the gated lateral bipolarjunction transistors (G-LBJTs) [3] using the bulk terminal asan active electrode, have been introduced for low-voltageapplications. A constant substrate biasing technique canalso be used with a standard CMOS architecture to improveMOSFET performance. Indeed, forward body biasingreduces the threshold voltage VT and thus increases thedevice speed, whereas reverse body biasing can be used tocontrol the off-state leakage current for low powerapplications where static power dissipation is a majorconcern [4].The body bias is also used in analogue integrated circuits

such as current mirrors or VCOs to ne-tune transistorcharacteristics. For example, forward and reverse substratebiasing has recently been used to control oscillation

frequency, power dissipation and phase noise in a CMOSoscillator [57]. An important feature of the oscillator wasthat it had two control voltages for the oscillationfrequency, the supply voltage which was used as a coarsecontrol and the substrate voltage as a ne control for theoscillation frequency.Concerning the low frequency noise performance, the

impact of biasing the substrate has not been widely studied[8, 9]. In this contribution, we rst present the currentvoltage and transconductance characteristics at various VBSto illustrate the benets of body biasing. Two importantconsequences of body biasing are the ability to change thethreshold voltage and transconductance [4, 10]. Bothparameters have a profound impact on the dc, noise andac performance of the MOSFET and MOS-based circuits.In this paper, we extend the work of [11].

2 Experiments

2.1 Devices studiedThe devices used in this study were isolated N andPMOSFETs fabricated using a standard 130nm CMOSprocess. The MOS transistors used dual polysilicon gates.The gate oxide thickness tox 1.7nm and shallow trenchisolation was used. These devices were designed foroperation at a nominal supply voltage VDD71.2V. Aconstant gate width W 10mm, and various mask gatelengths Lm 10, 0.8 and 0.2mm were available. The deviceswere provided by STMicroelectronics-Crolles, France.

2.2 Experimental set-upThe DC characteristics were measured using the HP4142Asemiconductor parameter analyser. Noise measurementswere performed on-wafer in a shielded probe station. TheDUT was biased using batteries and the drain current noiseamplied with an ultralow noise current amplier (trans-resistance amplier) EG&G 5182 or a low-noise voltageamplier EG&G 5003, depending on the operating regimeof the transistor. Both congurations are schematically

M. Marin, P. Llinares and J.C. Vildeuil are with STMicroelectronics, 38926Crolles cedex, France. M. Marin is also with CEM2, Universite Montpellier II

M.J. Deen and M. de Murcia are with CEM2, Universit!e Montpellier II, 34095Monptellier cedex 5, France. M.J. Deen is also with the Electrical andComputer Engineering Dept., McMaster University, Hamilton, Ontario,Canada

r IEE, 2004

IEE Proceedings online no. 20040509

doi:10.1049/ip-cds:20040509

Paper rst received 20th June and in revised form 24th September 2003

IEE Proc.-Circuits Devices Syst., Vol. 151, No. 2, April 2004 95

shown in Figs. 1 and 2 respectively. Drain current noisepower spectral density (PSD) was measured using anHP3562A dynamic signal analyser in the frequency range1Hz100kHz. The experimental setup is controlled by aHP workstation. For the range of biasing currents studied,both setups gave almost identical results.

3 DC characterisation

3.1 IV characteristicsTypical measured IDS(VGS) and gm(VGS) characteristics areshown in Figs. 3 and 4, respectively. The body-to-sourcevoltage VBS was varied from +0.5V to 0.5V in steps of0.25V. These characteristics are plotted for a W/L 10mm/10mm transistor in the linear regime of operation atVDS725mV. Figure 3 illustrates the subthresholdcharacteristics and threshold voltage variations due to thebody bias effect [4, 9]. Reverse substrate biasing increasesthe threshold voltage and produces a signicant reductionin the off-state current at VGS 0V. Inversely, a forwardbody bias results in a decrease in VT and an increase in theon-state current.Variation of the transconductance gm as a function of

VBS is shown in Fig. 4. One can observe that thetransconductance peak value is dependent on VBS.Figure 4 also shows that most of the transconductanceimprovement occurs at VGSB70.2 to 0.3V, which is closeto the threshold voltage value. This improvement in gm hassignicant implications for low-voltage, low-power analo-gue circuits where VBS biasing close to VT is activelyresearched.

To illustrate one of these implications, we look at theresults in Fig 4. For example, at VGSB70.28V,gm(NMOS) changes from B0.8mS (VBS0.5V) toB10.4mS (VBS+0.5V) while gm(PMOS) changes fromB0.4mS (VBS+0.5V) to B2.7mS (VBS0.5V). Thatis, for a change in VBS of 1V, gm (NMOS) changes by 12times and gm(PMOS) changes by 7 times for these two setsof transistors. These large changes in gm at low VGS havesignicant implications for operating parameters such asswitching speed, unity current gain frequency and noise inlow-voltage, low-power integrated circuits.Figure 5 shows the variations of the maximum

transconductance change Dgm.max as a function of thesubstrate bias VBS and gate length Lm at VDS725mV.Dgm.max is dened as

Dgm;maxVBS gm;maxVBS gm;maxVBS 0V gm;maxVBS 0V 1

For the two longest devices (Lm 10 and 0.8mm), themaximum transconductance is enhanced when applying aforward substrate bias VBS, while it is degraded in the caseof a reverse body bias. This behaviour can be explained byconsidering that the effective mobility of the carriers isdegraded by enhancement of the effective transverse electric

VD

VGHP3562A

DUT

LN currentamplifier

biasing system

Fig. 1 Noise measurement setup using a low-noise currentamplifier (EG&G 5182)

HP3562A

DUT

Rp

AV

VD

VG

LN voltageamplifier

biasing system

Fig. 2 Noise measurement setup using a low-noise voltageamplifier (EG&G 5003)

NMOS

VGS, V0 0.2 0.4 0.6 0.8 1.0 1.2 1.4

I DS,

A

1012

1011

1010

109

108

107

106

105

104

VBS = + 0.5 V

VBS = 0.5 V

at VDS = 25 mV

a

VGS, V0 0.2 0.4 0.6 0.8 1.0 1.2 1.4

I DS,

A

1012

1011

1010

109

108

107

106

105

b

PMOS

VBS = 0.5 V

VBS = +0.5 V

at VDS = 25 mV

Fig. 3 Drain current IDS against gate voltage VGS characteristicsas a function of substrate bias VBS from +0.5 V to 0.5 V in steps of0.25 V(W/L 10/10)a NMOSb PMOS

96 IEE Proc.-Circuits Devices Syst., Vol. 151, No. 2, April 2004

eld. Depending on the body bias polarity, the magnitudeof the transverse eld is increased or decreased, thuschanging the mobility and hence the transconductance. Themaximum transconductance of the shortest transistor(Lm 0.2mm) shows a weaker VBS dependence. Thisbehaviour has previously been explained with the help ofnumerical simulations [12, 13]. In fact, for short channeldevices, one has to consider the dependence of the quasi-Fermi level gradient on the substrate bias. This phenom-enon compensates the mobility variations and takes over ata critical gate length that depends on the substrate dopinglevel.

3.2 Conduction parametersThe main conduction parameters were extracted in thelinear region from a set of IDSVGS transfer characteristicsand gm(VGS) transconductance curves at VDS725mVand VBS 0V, using the method in [14]. These parametersinclude the channel length reduction DL, the parasiticresistances Racc in series with the intrinsic channel of thetransistor, the threshold voltage VT, the low eld mobilitymo, the mobility degradation factor y and the subthresholdswing S. The values for N and PMOS devices are reportedin Table 1. The threshold voltage VT was found to increasewith reduction of the gate length Leff. This well-known VTroll-up is attributed to pocket implants which induced anon-uniform lateral doped channel. The large value of the

mobility degradation factor is consistent with the very thinoxide tox 1.7nm used for these transistors. The subthres-hold swing S values were extracted at VDS71.2V fromthe IDSVGS characteristics. The data are shown in Fig. 6as a function of VBS and gate length Lm.The subthreshold swing S is observed to increase from

reverse to forward body biasing. The swing factorexpression is given by

S kTqln 10 1 CD Cit

Cox

2

where CD is the depletion charge capacitance (that dependson the depletion width xd) and Cit the interface charge

NMOS

0 0.2 0.4 0.6 0.8 1.0 1.2 1.40

2

4

6

8

10

12

14

VBS = +0.5 V

VBS = 0.5 V

at VDS = 25 mV

PMOS

VGS, V1.41.21.00.80.60.40.20

g m, S

g m, S

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5VBS = 0.5 V

VBS = + 0.5 V

at VDS = 25mV

b

VGS, Va

Fig. 4 Transconductance gm against gate voltage VGS character-istics as a function of the substrate bias VBS from +0.5 V to 0.5 Vin steps of 0.25 V(W/L 10/10)a NMOSb PMOS

NMOSNMOS

a

b

102101100101

102101100101

15

10

5

0

5

10

15

VBS = 0.5 V (reverse)VBS = + 0.5 V (forward)

Lmask, m

Lmask, m

gm

,max/g

m,m

ax

(VBS

= 0),

%g

m,m

ax/g

m,m

ax

(VBS

= 0),

%

20

10

0

10

20

VBS = 0.5 V (forward)VBS = 0.5 V (reverse)

PMOS PMOS

Fig. 5 Variations of the maximum transconductance gm,max withsubstrate bias VBS and gate length Lm at VDS725 mVa NMOSb PMOS

Table 1: Conduction parameters NMOS/PMOS (CMOS130nm technology)

W/L (mm) 10/10 10/0.8 10/0.2

VT (V) 0.26/0.27 0.34/0.29 0.45/0.33mo (cm

2/Vs) 298/70

y (V1) 0.47/0.74

DL (mm) 0.06/0.036

Racc (O.mm) 110/420

S (mV/dec) atVDS725mV

75/71 74/71 78/74


capacitance. As body bias is varied from reverse to forwardmode, the depletion width xd is reduced, resulting in anincrease in CD and hence an increase of S.

4 Noise characterisation

Low-frequency noise measurements were performed in the1Hz to 100kHz frequency range. Figure 7 illustrates typicalspectra obtained at various drain currents IDS from weak tostrong inversion modes of operation, for an NMOSFETwith 0.8mm gate length.The low-frequency spectra are predominantly 1/f like for

almost all devices. It is noticed that at low IDS values andhigher frequencies, the noise spectra variation withfrequency deviates from 1/f due to the cut-off frequencyof the device-preamplier equivalent circuit. Moreover, itshould be mentioned that when drain current noise spectraldensity SiD includes additional pronounced Lorentzianspectra in the subthreshold regime or for small gatearea devices, the 1/f noise component was extractedassuming that SiDf is a superposition of 1/f noise andg-r or RTS noise (Lorentzian behaviour). The resultspresented and discussed later are only for the 1/f noisemeasured or extracted. All data are plotted at a frequencyf 1Hz.

4.1 Noise results in linear regime atVBS 0VNoise measurements were rst performed at low drain biasVDS725mV and at VBS 0V in order to investigate thephysical origin of the uctuations. Figure 8 shows thevariations of the normalised drain current noise Si/IDS

2 as afunction of IDS from weak to strong inversion and in thelinear region for the different gate lengths. These plots areusually made when studying the noise origin in MOSFETs[13].For the NMOS devices, the normalised noise level is

found to level off in weak inversion and decrease as IDS2 in

strong inversion. Moreover, good correlation is obtainedwhen comparing Si/IDS

2 variations with the ratio (gm/IDS)2.

This is in agreement with the carrier number uctuationtheory [13] DN since:

SiI2DS

SVfb gmIDS

23

where SVfb is the at-band voltage spectral density given by

SVfb q2kTlNtEFWLfC2ox

4

with l the attenuation coefcient of the electron/holewavefunction in the oxide (lE0.1nm). The oxide trapdensity Nt(EF) value has been extracted as6 1017 eV1 cm3 from experiments.Considering the PMOS transistor results, the relative

noise Si/IDS2 saturates in weak inversion and then decreases

as IDS1 in strong inversion. Si/IDS

2 is not correlated with the(gm/IDS)

2 variations, and moreover, the input-referred noisevoltage gives rise to a parabolic dependence with gatevoltage VGS. In this case, it is shown [15] that thenormalised noise Si/IDS

2 variations with IDS agree with thecorrelated carrier numbermobility uctuation DNDmmodel given by:

SiI2DS

1 asmefCoxIDSgm

2 gmIDS

2SVfb 5

where as is the Coulomb scattering coefcient. Its value isfound to be 2 105Vs/C. It is noticed that the oxide trapdensity NT(EF) value is similar to the previous one obtainedfor the NMOSFETs. The average plateau value of Si/IDS

2 inweak inversion at xed IDS current are reported in Fig. 9 asa function of the effective gate length Leff. Correct scaling of

VBS, V

0.6 0.4 0.2 0 0.2 0.4 0.6

S, m

V/de

c

70

75

80

85

90

95

100

reverse forward

NMOSNMOS

PMOS

S, m

V/de

c

65

70

75

80

85

90

95

a

VBS, V

0.6 0.4 0.2 0 0.2 0.4 0.6reverseforward

b

Fig. 6 Variations of subthreshold slope S as a function of VBS atVDS71.2 V for various gate lengthsLm 10 (), 0.8 (m) and 0.2 (~) mma NMOSb PMOS

f, Hz100 101 102 103 104 105

S i (f

), A2 /H

z

1013

1015

1017

1019

1021

1023

1025

1027

1/f IDS

Fig. 7 Drain current noise spectral density Si(f) as a function ofthe frequency at various drain current IDS for an NMOS deviceW/L 10/0.8 biased at VDS 1.2V and VBS 0V


the normalised noise magnitude is obtained when comparedwith the theoretical variation, that is, Si/IDS

2 pLeff1

(see (4)).

4.2 Noise results in nonlinear regime as afunction of VBSIn order to study the effect of substrate biasing in the usualoperating regime of the transistor, noise measurements wereperformed from weak to strong inversion in a deepsaturation regime at VDS71.2V. The body bias VBSwas varied from VBS0.5V to VBS+0.5V. The upperVBS limit value in the forward mode of operation waschosen because at this substrate bias, the sourcesubstrateISB diode current as well as the drain current IDS at zeroVGS is still low, that is ISBo0.2nA and IDSo10nA.However, further increases in VBS forward bias result insignicant increases in IDS, making the static powerdissipation unacceptably high. Considering the weakinversion region, the noise level for both N and PMOS-FETs followed a quadratic variation with the drain currentIDS. Figure 10 shows the average plateau value of thenormalised noise level /Si/IDS

2 S at constant currentIDSE1mA as a function of the substrate bias VBS and gatelength Leff.A signicant noise level reduction of about 50% for all

devices is observed in this operating region when applying aforward body bias whereas the noise is weakly impactedwith a reverse substrate bias. The noise expression [15] in

weak inversion is given by

SiI2DS

q4lNtEF

kTWLf Cox CD Cit2

q2lkTNtEF ln102

WLfC2oxS2/ 1S2 6

Following (6), the normalised drain current noise Si/IDS2

should be correlated with the variations of the swing factorS with VBS. We have plotted in Fig. 11 the variations of thenormaliszed noise level Si/IDS

2 and the variations of 1/S2

with VBS for the longest (Lm 10mm) and the shortest(Lm 0.2mm) devices. As shown, Si/IDS2 and 1/S2 followsimilar trends with the substrate bias VBS and qualitativeagreement is observed. Nevertheless, it is noticed that thenoise level in the forward mode decreases faster than 1/S2

for the shortest gate length device, pointing out thatdepletion charge capacitance variations with VBS cannotfully account for the noise reduction experimentallyobserved in this operating region.Considering now the strong inversion regime, the LFN

results are plotted as a function of the drain current IDS andbody bias VBS for Lm 10, 0.8 and Lm 0.2mm in Fig. 12for NMOS and PMOS transistors, respectively. The noiselevel is found to be clearly independent of the body bias atxed IDS current. Moreover for the longest gate lengthNMOSFET, SiDpIDS as it is predicted in deep saturation

IDS, A

1012109

1011

108

1010

107

109

108

106

107

1010

109

108

107

105

106

103104

(g m/I D

S)2, a

.u(g m

/I DS)2

, a

.u

a

IDS, A109 108 107 106 105 103104

b

NMOS

SiD

/I DS2

, 1/

HzSi

D/I D

S2, 1/

Hz

~ ~ IDSDS1

IDSDS2

Fig. 8 Variations of normalised drain current noise Si/IDS2 against

drain current IDS at VDS725 mVLm 10 (), 0.8 (m) and 0.2 (~) mm gate length devicesa NMOSb PMOS

Leff, m101 100 101 102

Si D

/I DS2,

1/

Hz

1010

109

108

107

Leff1

Leff1

NMOS

PMOS

a

Leff, m101 100 101 102

Si D

/I DS2,

H

z1

1010

109

108

107

b

Fig. 9 Normalised drain current noise Si /IDS2 in the subthreshold

regime against effective gate length Leff at IDSE1mA andVDS725 mVLm 10 (), 0.8 (m) and 0.2 (~) mma NMOSb PMOS


by DN model. For the longest PMOS device we ndSiDpIDS

3/2 at VDS4VGSVT.Indeed, to understand physically the dependence ob-

served of the LFN with VBS, we have to consider theMcWhorter approach where the noise source is suppose tobe due to the carrier number uctuation in our N andPMOS devices. Considering the charge conservationprinciple [16], a variation of the oxide charge dQox inducesa variation of the inversion charge dQinv given by:

dQinv CinvCox CD Cit Cinv dQox 7

where Cox, CD, Cit, Cinv are the oxide, depletion charge,interface traps and inversion charge capacitance per unitarea respectively. In the weak inversion regime, assumingthat Cox+CD+Cit4Cinv, the uctuation in the amount oftrapped oxide charges dQox induced inversion carrieructuation dQinv, which shows a strong dependence onVBS, as expected from (7).In the strong inversion regime, the previous capacitance

ratio becomes almost unity (CinvcCox+CD+Cit). Thismeans that the uctuation in the oxide trapped charge isfully correlated with uctuations in the inversion charge,that is, dQinvEdQox. As the charge exchange with thedepletion layer becomes negligible in this region, the noiselevel should not be affected by the substrate biasing VBS.Some scattering with VBS is observed for the shortestNMOS device Lm 0.2mm. Extra noise measurements

have been performed at VBS0.25V and +0.25V inorder to discriminate between dispersion and some shortchannel effects. As they show a similar level, the observedvariations are attributed to dispersion of the data and arenot interpreted as a body bias effect.Other possibilities for explaining the improved low-

frequency noise characteristics in MOS devices withforward body bias are now discussed. Forward body biasincreases the effective gate or lateral electric eld which inturn lowers the semiconductor oxide barrier. This loweredbarrier result in a decreased attenuation coefcient l of thecarrier wave function in the oxide, thus decreasing SVfb (see(4)) and Si/IDS

2 (see (3) and (5)). Another factor to beconsidered is the number of carriers in the channel and howthis is affected by body bias. Since a forward body-sourcebias decreases the threshold voltage in NMOS transistors,then for the same gate voltage, the number of electrons inthe channel increases, resulting in reduced Coulombicscattering due to the diminished scattering coefcient. Withdiminished Coulombic scattering, the low-frequency noisealso decreases. Finally, in these thin oxide or short channeldevices, quantisation of the inversion layer and a peakcarrier density some distance (Bnm) from the inversionlayer most be considered. Both of these are dependent onthe effective gate bias that must include the body bias.More details on these effects can be found in [17]and [18].

5 Conclusions

The impact of forward and reverse substrate biasing onlow-frequency noise performances of N and PMOS

VBS = 0.5 V (reverse)VBS = 0 V VBS = + 0.5 V (forward)

VBS = 0.5 V (forward)VBS = 0 V VBS = + 0.5 V (reverse)

(1)NMOS

(1)PMOS

Leff, m101 100 101 102

Si/I

DS2,

1/

Hz

1010

109

108

107

a

Leff, m101 100 101 102

Si/I

DS2,

1/

Hz

1010

109

108

107

b

Fig. 10 Average plateau values of the normalised drain currentnoise Si /IDS

2 in the subthreshold regime at VDS71.2 V as afunction of the substrate bias VBS and gate length Leffa NMOSb PMOS

VBS, V

0.8 0.6 0.4 0.2 0 0.2 0.4 0.6 0.8

1/

S2, a

.u 1/

S2, a

.u

forwardreverse

reverse

Lm = 0.2 m

Lm = 10 m

NMOS

Lm = 0.2 m

Lm = 10 m

PMOS

a

VBS, V

0.8 0.6 0.4 0.2 0 0.2 0.4 0.6 0.8forward

b

Si/I

DS2,

H

z1

1010

109

108

107

Si D

/I DS2,

H

z1

1010

109

108

107

Fig. 11 Variations of Si /IDS2 and 1/S2 with the substrate bias VBS

for Lm 10 and 0.2mma NMOSb PMOS


transistors in a 130nm CMOS technology has beeninvestigated from weak to strong inversion modes ofoperation. A detailed electrical characterisation was rstperformed and the main conduction parameters deter-mined. Maximum transconductance gm,max were found tobe a complicated function of the substrate bias, and itsvariation was interpreted considering the effective transverseelectric eld dependence of carrier mobility for long channeldevices. Noise measurements were performed at low drainbias VDS725mV and VBS 0V in order to investigatethe physical origin of the uctuations.Noise level variations agree with the carrier number

uctuation theory DN for NMOS devices and with the DNDmmodel for PMOS devices. The oxide trap density Nt(EF)was found to be 6 1017 eV1 cm3. Body bias effect hasbeen investigated at VDSVDD71.2V. A signicantnoise reduction of about 50% was observed in thesubthreshold regime when applying a forward body bias,in agreement with depletion capacitance variations andReimbold theory based on theMcWhorter model. In stronginversion, the noise level was found to be independent of thesubstrate bias VBS. In addition the measurements performed

on p-type surface channel devices illustrate that thecorrelated DNDm model is more suitable in all operatingregime to predict the 1/f noise behaviour. Possibilities forexplaining the low-frequency noise behaviour with bodybias were also discussed.

6 Acknowledgments

The authors thank STMicroelectronics-Crolles, France, forproviding the samples. M. Marin thanks STMicroelectro-nics for funding and Dr V. Le-Goascoz for interest andsupport. M.J. Deen thanks CNRS, France; Micronet,Canada; and NSERC, Canada for support.

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17 Taur, Y., and Ning, T.H.: Fundamentals of Modern VLSI Devices(Cambridge University Press, Cambridge, 1998)

18 Nicollian, E.H., and Brews, J.R.: MOS (metal oxide semiconductor)physics and technology (John Wiley & Sons, New York, 1982)

IDS, A107 106 105 104 103 102

S iD, A2

/Hz

S iD, A2

/Hz

10221021102010191018101710161015101410131012

Lm = 10 m

Lm = 0.8 m

Lm = 0.2 m

IDS

NMOS

Lm = 10 m

Lm = 0.8 m

Lm = 0.2 m

IDS3/2

PMOS

a

IDS, A107 106 105 104 103 102

10221021102010191018101710161015101410131012

b

Fig. 12 Current noise spectral density Si versus drain current IDSin strong inversion at VDS71.2 VVBS0.5V (m), 0V (), + 0.5V (,) for Lm 10, 0.8 and 0.2mma NMOSb PMOS


Index:

CCC: 0-7803-5957-7/00/$10.00 2000 IEEE

ccc: 0-7803-5957-7/00/$10.00 2000 IEEE

cce: 0-7803-5957-7/00/$10.00 2000 IEEE

index:

INDEX:

ind:

footer1: 0-7803-8367-2/04/$20.00 2004 IEEE

01: 3

02: 4

03: 5

04: 6

05: 7

06: 8

07: 9

08: 10

09: 11

10: 47

mosfet paper

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