MOSFET Logic

Circuits

➢ Active semiconductor devices (with three terminals)

➢ Operating principle: using a voltage between two terminals (command) to control the current through the third terminal.

➢ Transistors: voltage-controlled current sources

TRANSISTORS

Discrete transistors

TRANSISTORS

Transistors: essential components of every electronic circuit

Integrated transistors - digital integrated circuit

MOS transistor (T) count (processor)

• Intel 4004 (4-bit), 1971, 10µ, 12mm2, 2,250 T

• Pentium 4 Prescott (32-bit) 2004, 90nm, 110mm2 112,000,000 T

• Core i7 Broadwell-E (64-bit), 2016, 14nm, 246mm2, 3,200,000,000 T

• Apple A12 (hexa-core ARM64), 2018, 7nm, 83.27mm2, 6,900,000,000 T

• AMD Epyc Rome (64-bit), 2019, 7&12nm, 1088 mm2, 39,540,000,000 T

• Apple M1 Max (10-core, 64-bit), 2021, 5nm, 57,000,000,000 T

[https://en.wikipedia.org/wiki/Transistor_count]

Transistor typesMetal-Oxide-Semiconductor Field-Effect Transistors

MOSFET

Bipolar Junction Transistors

Symbols of MOSFET

G - gate or grid D - drainS - source

n - type p - type

n -channel enhancement-type

MOSFET

p -channel enhancement-type

MOSFET

6 /22

vGS

iD

0

VThn

off on

iD iD

vGS

iD

0

VThp

offon

n -channel enhancement-type MOSFET

p -channel enhancement-type MOSFET

Tn Tp

Operation of MOSFET

vGS

iD

0

VThn

off on

vI

R

VPS

vO

vGS

Tn

A

Y

vI vGS Tn vO

0 0(< vThn)

off(open-circuit)

VPS

VPS VPS

(>> vThn)

on(short-circuit)

0

Logic circuit

with Tn

0V → logic 0

VPS → logic 1

Operating table Truth table

NOT

A Y

0 1

1 0

vI vGS Tn vO

0 -VPS

(<< vThp)

on(short-circuit)

VPS

VPS 0(> vThn)

off(open-circuit)

0

Logic circuit

with Tp

0V → logic 0

VPS → logic 1

A Y

0 1

1 0

Operating table Truth table

NOT

vGS

iD

0

VThp

offon

vI R

VPS

vO

vGS

TpAY

Critical analysis of the NOT logic circuit

with Tn and R

vI=0

R

VPS

vO

vGS

Tn

RL

Disadvantage elimination:

R as small as possible, ideal R→0

Critical analysis of the NOT logic circuit

with Tn and R

vI=0

R

VPS

vO

vGS

Tn

RL

Disadvantage elimination:

R as small as possible, ideal R→0

vI=VPS

R

VPS

vO

vGS

Tn

RL

R as large as possible, ideal R→∞

Solution?

CMOS Logic Inverter

vO

CMOS – Complementary MOSFET

A Y

0 1

1 0

R

VDD

A

Y

B

Tn1

Tn2

NAND

R

VDD

A

Y

BTn1

Tn2

NOR

How can we

eliminate the

disadvantages

due to the

presence of R ?

CMOS NAND

CMOS NOR CMOS AND

Logic Gates

0 1

1 0

NOT AB

0 0 0

0 1 0

1 0 0

1 1 1

AND

0 0 0

0 1 1

1 0 1

1 1 1

OR

A+B

Logic Gates – cont.

0 0 1

0 1 1

1 0 1

1 1 0

0 0 1

0 1 0

1 0 0

1 1 0

NORNAND

0 0 0

0 1 1

1 0 1

1 1 0

XOR

Problem

Transfer characteristicof the CMOS inverter

Noise margins

Logic circuit 1

Logic circuit 2

out in

Noise margins - cont.

maxmax

minmin

OLILL

IHOHH

VVNM

VVNM

−=

−=

Voltage levels and

noise margins for

CMOS logic family

supplied at +5V

V1V5.0V5.1 =−=LNM

V1V5.3V5.4 =−=HNM

5V 5V

4.5V

0.5V

0V 0V

1.5V

3.5V