6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 10-1

Lecture 10 - MOSFET (II)

MOSFET I-V Characteristics (cont. )

March 11, 2003

Contents:

1. The saturation regime

2. Backgate characteristics

Reading assignment:

Howe and So dini, Ch. 4, §4.4

Announcements: Quiz #1, March 12, 7:30-9:30 PM, Walker Memorial; covers Lectures #1-9; op en b o ok; must have calculator.

No recitations on March 12 (instructors available for con­sultation at their offices)

6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 10-2

Key questions

• How do es the MOSFET work in saturation?

• Do es the pinch-off p oint represent a blo ck to current flow?

• How come the MOSFET current still increases a bit with V in saturation? DS

• How do es the application of a back bias affect the MOSFET I-V characteristics?

6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 10-3

1. The saturation regime

Geometry of problem: VDS

depletion region inversion layer

n+

p

n+

VGS>VT

DG

S

B

0 L y

ID

VBS=0

Regimes of op eration so far (V = 0): BS

• Cut-off : V GS < V T , VGD < V T :no inversion layer anywhere underneath gate

I = 0 D

• Linear: V GS > V T , VGD > V T (with V DS > 0): inversion layer everywhere underneath gate

ID =W

Lµn Cox (V GS − V DS

2− VT )V DS

6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 10-4

Output characteristics:

ID

0 0 VDS

VGS

VGS=VT

VDS=VGS-VT

6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 10-5

2 Review of Q , E , and V in linear regime as V n y c DS

increases:

|Qn|

0 0 L y

VDS

VDS=0

|Ey|

0 0 L y

VDS

VDS=0

Vc

0 0 L y

VDS

VDS=0

Ohmic drop along channel debiases inversion layer ⇒ current saturation

µ

6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 10-6

2 Drain current saturation

As V approaches: DS

V = V − V D S sat GS T

increase in |E | comp ensated by decrease in |Q | y n

⇒ I saturates to: D

I = I (V = V = V − V ) D sat Dli n DS D S sat GS T

Then:

W 2 I = C (V − V ) D sat n ox GS T 2L

VDSsat=VGS-VT ID

VGS

VGS=VT

linear saturation

0 0 cutoff VDS

µ

6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 10-7

W 2I = C (V − V ) D sat n ox GS T 2L

Transfer characteristics in saturation:

ID

0 0 VT VGS

VDS>VDSsat=VGS-VT

��

6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 10-8

2 What happ ens when V = V − V ? DS GS T

Charge control relation at drain-end of channel:

Q (L) = −C (V − V − V ) = 0 n ox GS DS T

No inversion layer at end of channel??!! ⇒ Pinch-off

At pinch-off:

• charge control equation inaccurate around V T

• electron concentration small but not zero

• electrons move fast b ecause electric field is very high

• dominant electrostatic feature: acceptor charge

• there is no barrier to electron flow (on the contrary!)

G

inversion layer p

D

+ ++ ++++++++ -

--

- -- - - ---

----- n+ drain

depletion regions

L y

��

6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 10-9

2 Key dep endencies of I D sat

2 • I ∝ (V − V ) D sat GS T

Voltage at pinch-off p oint (V = 0 at source): c

G

p

D

+++++++++++ -

--

--- - - ---

----- n+

Vc(L)=VDSsat=VGS-VT

Drain current at pinch-off:

∝ lateral electric field ∝ V D S sat = VGS − VT

∝ electron concentration ∝ V GS − VT

2⇒ ID sat ∝ (VGS − VT )

∝ 1 L • ID sat

L ↓ → |E y | ↑

6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 10-10

1.5 × 46.5 NMOSFET

Output characteristics (V = 0 − 3 V, ΔV = 0.5 V ): GS GS

Transfer characteristics in saturation (V = 3 V ): DS

��

µ

�

6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 10-11

2 What happ ens if V > V − V ? DS GS T

Depletion region separating pinch-off p oint and drain widens (just like in reverse-biased pn junction)

G

p

D

+++++++++++ -

- ---- - - ---

----- n+

Vc(L-ΔL)=VDSsat=VGS-VT

L-ΔL L y

To first order, I D do es not increase past pinchoff:

=W 2L n�Cox (V GS − VT )

2ID = ID sat

To second order, electrical channel length affected (”channel-length modulation”): V ↑⇒ Lchannel ↓⇒DS�

D� ↑

1 1

LΔL L

)ID ∝ (1 + L − ΔL

I

µ

λ

6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 10-12

Exp erimental finding:

ΔL ∝ V − V DS D S sat

Hence:

ΔL = λ(V − V ) DS D S sat

L

Improved mo del in saturation:

W 2 I = C (V − V ) [1 + λ(V − V )] D sat n ox GS T DS D S sat 2L

VDSsat ID

VGS

VGS=Vth

0 0 VDS

Also, exp erimental finding:

1 ∝L

6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 10-13

2. Backgate characteristics

There is a fourth terminal in a MOSFET: the body.

What do es the b o dy do?

VDS

depletion region inversion layer

n+

p

n+

VGS>VT

DG

S

B

0 L y

ID

VBS

Bo dy contact allows application of bias to b o dy with re­sp ect to inversion layer, V .BS

Only interested in V < 0 (pn dio de in reverse bias). BS

Interested in effect on inversion layer ⇒ examine for V > V (keep V constant). GS T GS

6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 10-14

Application of V < 0 increases p otential build-up across BS�

semiconductor:

−2φ ⇒ −2φ − V p p BS

Depletion region must widen to pro duce required extra field:

0

ρ

-qNa

0 -tox

Qn

xdmax(VBS)

x

VBS=0

VBS<0

0 0

E

Eox

Es

x -tox xdmax(VBS)

x

φ

0 0

-tox

VGS+φB

VBS

-φp

Vox

VB=-2φp VB=-2φp-VBS

6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 10-15

Consequences of application of V < 0: BS�

• −2φ ⇒ −2φ − V p p BS

• |Q | ↑⇒ x ↑ B dmax

• since V constant, V unchanged GS ox

⇒ E unchanged ox

⇒ |Q | = |Q | unchanged s G

• |Q | = |Q | + |Q | unchanged, but |Q | ↑ ⇒ |Q | ↓ s n B B n

⇒ inversion layer charge is reduced!

Application of V < 0 with constant V reduces elec-BS GS

tron concentration in inversion layer ⇒ V ↑ T

γ

γ

6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 10-16

How do es V change with V ? T BS

In V formula change −2φ to −2φ − V : T p p BS

√ GB V (V ) = V − 2φ − V + (−2φ − V ) BS FB p BS p BS T

In MOSFETs, interested in V b etween gate and source : T

GB GS V = V − V ⇒ V = V − V GB GS BS BS T T

Then:

GS GB V = V + V BS T T

And:

√ GS (V ) = V − 2φ + (−2φ − V ) ≡ V (V ) BS FB p p BS T BS T

In the context of the MOSFET, V is always defined in T

terms of gate-to-source voltage .

V

γ

6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 10-17

Define:

V = V (V = 0) To T BS

Then:

√ √ V (V ) = V + ( −2φ − V − −2φ ) T BS To p BS p

ID

cut-off

saturation

VBS

0 0 VT VGS

6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 10-18

Backate characteristics (V = 0, −1, −2, −3 V, V = BS DS

3 V ):

µ

6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 10-19

Key conclusions

• MOSFET in saturation (V ≥ V ): pinch-off DS D S sat

p oint at drain-end of channel

– electron concentration small, but

– electrons move very fast;

– pinch-off p oint do es not represent a barrier to elec­tron flow

• In saturation, I saturates: D

W 2 I = C (V − V ) D sat n ox GS T 2L

• But..., due to channel-length modulation , I in-D sat

creases slightly with V DS

• Application of back bias shifts V (back-gate effect) T