10/28/2019

Electronics I1

MOSFET → Chapter 5

Cross Section Diagram

• MOS – Metal Oxide Semiconductor• FET – Field-Effect Transistor• 4 terminal device

Advantages:- Small area; comparatively- Less power- Relatively simple manufacturing process

• nMOS Transistor

* If the bulk terminal is omitted, it is presumed is connected to the source

• pMOS Transistor

Symbol

10/28/2019

Electronics I2

Modern CMOS TechnologyIC

–C

ross

-Sec

tio

n

Twin-Well Process

10/28/2019

Electronics I3

CMOS Transistors

p+-substrate

n-well

p+n+ p+ n+ n+ p+

nMOSpMOS

bulk source drain

gate

substratesource drain

gate

Single-Well Process

Complementary MOS

10/28/2019

Electronics I4

Operation Regions

p+-substrate

Vd

Vg

p+

Vd

Vg

Vtn

Id

1) Cut-Off2) Strong - Inversion3) Weak - Inversion

0 V

ID = f(vGS2)ID = f(eVGS)

n+n+

Id

depletion layer

inversion layer

`

-- ----- ---

10/28/2019

Electronics I5

nMOS Strong Inversion → Saturation

iD ≈ f(vGS2)• vGS > vtn

• vDS > vGS - vtn

• iG = 0

𝐼𝐷 =1

2𝑘𝑛

′𝑊

𝐿𝑉𝐺𝑆 − 𝑉𝑡𝑛

2 1 + 𝜆𝑉𝐷𝑆

𝒌𝒏′ = 𝝁𝒏𝑪𝒐𝒙

nMOS Transconductance Parameter [A/V2]

Channel Length ModulationParameter [1/V]

𝑲𝒏

≈1

2𝑘𝑛

′𝑊

𝐿𝑉𝐺𝑆 − 𝑉𝑡𝑛

2

𝑽𝒐𝒗 = 𝑽𝑮𝑺 − 𝑽𝒕𝒏Over-drive Voltage

10/28/2019

Electronics I6

nMOS Strong Inversion → Ohmic

iD = f(vGS, vDS)• vGS > vtn

• vDS < vGS - vtn

• iG = 0

𝐼𝐷 = 𝑘𝑛′𝑊

𝐿𝑉𝐺𝑆 − 𝑉𝑡𝑛 𝑉𝐷𝑆 −

1

2𝑉𝐷𝑆

2

≈ 𝑘𝑛′𝑊

𝐿𝑉𝐺𝑆 − 𝑉𝑡𝑛 ∙ 𝑉𝐷𝑆

𝒓𝒅𝒔 =𝟏

𝒌𝒏′𝑾𝑳

𝑽𝑮𝑺 − 𝑽𝒕𝒏

𝑽𝒐𝒗 = 𝑽𝑮𝑺 − 𝑽𝒕𝒏

10/28/2019

Electronics I7

Overdrive VoltageAdditional voltage required at VGS to be

able to conduct a given current ID

𝐕𝐆𝐒 > 𝐕𝐭𝐧 → 𝐒𝐭𝐫𝐨𝐧𝐠 𝐈𝐧𝐯𝐞𝐫𝐬𝐢𝐨𝐧

• 𝐕𝐃𝐒 > 𝐕𝐨𝐯 → 𝐒𝐚𝐭𝐮𝐫𝐚𝐭𝐢𝐨𝐧• 𝐕𝐃𝐒 < 𝐕𝐨𝐯 → 𝐎𝐡𝐦𝐢𝐜

𝐕𝐨𝐯 = 𝐕𝐆𝐒 − 𝐕𝐭𝐧 =𝟐𝑰𝑫𝑲𝒏

10/28/2019

Electronics I8

nMOS Weak Inversion → Saturation

• vGS < vtn

• vDS > 0.1 V

𝐼𝐷 = 𝐼0𝑒𝑉𝐺𝑆 − 𝑉𝑡𝑛

𝑛∙𝑈𝑡

𝑼𝒕 ∝ 𝑻𝑼𝒕 ≈ 𝟐𝟓𝒎𝑽@ 𝟐𝟓𝒐𝑪

Thermal Voltage [V]Slope Factor

𝒏 = [1 : 2]

Linear Behavior in Log-IDS

∴ Exponential IDS vs VGS Behavior

𝑽𝒕𝒏 − 𝟓 ∙ 𝑼𝒕 < 𝑽𝑮𝑺 < 𝑽𝒕𝒏 − 𝟐 ∙ 𝑼𝒕

10/28/2019

Electronics I9

nMOS Large Signal Model

Condition

𝑰𝑫 =𝝁𝑪𝒐𝒙𝟐

𝑾

𝑳𝑽𝑮𝑺 − 𝑽𝒕𝒉

𝟐 𝟏 + 𝝀𝑽𝑫𝑺

𝑰𝑫 = 𝝁𝑪𝒐𝒙𝑾

𝑳𝑽𝑮𝑺 − 𝑽𝒕𝒉 𝑽𝑫𝑺 −

𝑽𝑫𝑺𝟐

𝟐

• Strong Inversion – Ohmic

• Strong Inversion - Saturation

• Weak Inversion - Saturation

𝑰𝑫 = 𝑰𝟎∙𝒆𝑽𝑮𝑺−𝑽𝒕𝒉𝒏𝑼𝑻

VGS > Vth

VDS < VOV

VGS > Vth

VDS > VOV

Vth-5UT < VGS < Vth-2 UT

INEL 5265 – Review 10/28/2019

10

Weak Inversion Strong Inversion

Saturation current is exponential in VGS Saturation current is square law in VGS

VDSAT is constant at approximately 100mV VDSAT varies linearly with gate voltage

Current flows by diffusion Current flows mainly by drift

Charge concentrations are small Charge concentrations are large

Currents are small Current are large

Good for ultra-low-power operation Good for high-power operation

Power efficiency is constant with current Power efficiency is lower

High noise and offset Low noise and offset

Can work on low power supply voltage Needs higher power supply voltages

Linearity is hard to achieve Linearity is easy to achieve

Suited for slow-and-parallel architectures Suited for fast-and-serial architectures

Weak Inversion vs Strong Inversion?

10/28/2019

Electronics I11

pMOS Large Signal Model

Saturation Mode• vSG > |vtp|• vSD > vSG - |vtp|• iG = 0

𝐼𝐷 =1

2𝑘𝑝

′𝑊

𝐿𝑉𝑆𝐺 − 𝑉𝑡𝑝

21 + 𝜆𝑉𝑆𝐷

Ohmic Mode• vSG > |vtp|• vSD < vSG - |vtp|• iG = 0

𝐼𝐷 = 𝑘𝑝′𝑊

𝐿𝑉𝑆𝐺 − 𝑉𝑡𝑝 𝑉𝑆𝐷 −

1

2𝑉𝑆𝐷

2

≈ 𝑘𝑃′𝑊

𝐿𝑉𝑆𝐺 − 𝑉𝑡𝑝 ∙ 𝑉𝑆𝐷

≈1

2𝑘𝑝

′𝑊

𝐿𝑉𝑆𝐺 − 𝑉𝑡𝑝

2

𝒌𝒑′ = 𝝁𝒑𝑪𝒐𝒙

pMOS Transconductance Parameter [A/V2]

𝑽𝒐𝒗 = 𝑽𝑺𝑮 − |𝑽𝒕𝒑|

INEL 5265 – Review 10/28/2019

12

MOSFET Model ParametersUt = kT/q → thermal voltage (~25mV @ room temp.)

µ → electron/hole mobility𝛋s = 1/n → subthreshold slope coefficient (unit-less)Cox = ɛox/tox → gate oxide capacitance per unit area (F/cm2)Ɛox → dielectric permittivity of SiO2

tox → oxide thickness

Kn = kn’· W/L → transconductance parameter(A/V2)

kn’ = µCox

γ → body effect coefficient (V1/2)λ → channel-length modulation parameter (V-1)

VT0 → threshold voltage at VSB=0 (V)VT → threshold voltage (V)φ0 → ≈ surface potential (V)

INEL 5265 – Review 10/28/2019

13

The required voltage to produce and inversion layer.

voltage required to sustain the depletion layer

work-function difference between the gate metal and

the silicon

Fermi level

𝑽𝑻 = 𝑽𝑻𝟎 + 𝜸 𝝓𝟎 + 𝑽𝑺𝑩 − 𝝓𝟎

Threshold Voltage

𝑽𝑻𝟎 = 𝝓𝒎𝒔 + 𝟐𝝓𝑭 +𝑸𝒅𝒆𝒑

𝑪𝒐𝒙

surface potentialbody effect coefficient

The threshold voltage is a function of VSB!!!

10/28/2019

Electronics I14

Example 5.2

Consider an nMOS transistor fabricated in a 0.18μm process with L=0.18μm and W=2um. The processtechnology is specified to have Cox=8.6fF/μm2, μn=450cm2/V·s, and Vth=0.5V.

a) Find VGS and VDS that result in the MOSFET operating at the edge of saturation with ID=100 μ A.b) If VGS is kept constant, find VDS that results in ID=50μA.c) To investigate the use of the MOSFET as a linear amplifier, let it be operating in saturation with

VDS=0.3V. Find the change in iD resulting from vGS changing from 0.7V by +0.01V and by -0.01V.

10/28/2019

Electronics I15

Example 5.5

An n-channel MOSFET operating with Vov=0.5V exhibits a linear resistance rDS=1kΩ when vDS is very small.a) What is the value of the device trans-conductance parameter Kn?b) Assuming λ = 0, what is the value of the current ID obtained when vDS is increased to 0.5V? And to 1V?c) Assuming an λ = 0.1V-1, what is the value of the current ID obtained when vDS is increased to 0.5V?

And to 1V?

10/28/2019

Electronics I16

Example 5.3

Assuming λ=0, design the circuit below, that is, determine the values of RD and RS, so that the transistoroperates at ID=0.4mA and VD=0.5V. The NMOS transistor has Vth=0.7V, μnCox=100μA/V2, and W/L=32.

10/28/2019

Electronics I17

Example 5.7

Assuming λ=0, design the circuit below, so that the transistor operates in saturation with ID=0.5mA andVD=3V. The PMOS transistor has Vth=-1V, Kp=1mA/V2. What is the largest value that RD can have whilemaintaining saturation-region operation?

10/28/2019

Electronics I18

MOS Behavior → Intuitively

Choose the plot that best represents each

circuit behavior!

Circuit (a) ______ Circuit (b) ______

vI

v0

vI

v0

vI

v0

10/28/2019

Electronics I19

Example 5.8

Assuming matched NMOS and PMOS transistors with Vthn=-Vthp=1V, Kn=Kp=1mA/V2 and λ=0, find the draincurrents IDn and IDp, as well as the voltage vo, for vI=0V, +2.5V, and -2.5V.

INEL 4201 – PN Junction 10/28/2019

Electronics I20

p+-substrate

`

n+

Vd

Vg

n+ p+

Vd

Vg

-- ----- --

-- ----- ---

Vg

Vth

Id

Id

depletion layer

inversion layer

Last Lecture → MOS • Two external voltage sources are

required for biasing• Three operation modes:

1) Cut-Off2) Ohmic3) Saturation

used for switching!

used for amplification!

0 V

iD = f(vGS2)

INEL 4201 – PN Junction 10/28/2019

Electronics I21

Last Lecture → MOS DC Analysis

Triode• vGS > vth

• vDS < vGS - vth = vov

• iG = 0

𝐼𝐷 = 𝑘𝑛′𝑊

𝐿𝑉𝐺𝑆 − 𝑉𝑡ℎ 𝑉𝐷𝑆 −

1

2𝑉𝐷𝑆

2

≈ 𝑘𝑛′𝑊

𝐿𝑉𝐺𝑆 − 𝑉𝑡ℎ ∙ 𝑉𝐷𝑆

Saturation• vGS > vth

• vDS > vGS - vth = vov

• iG = 0

𝐼𝐷 =1

2𝑘𝑛

′𝑊

𝐿𝑉𝐺𝑆 − 𝑉𝑡ℎ

2 1 + 𝜆𝑉𝐷𝑆

𝒌𝒏′ = 𝝁𝒏𝑪𝒐𝒙

Transconductance Parameter [A/V2] Channel Length ModulationParameter [1/V]

𝑲𝒏

≈1

2𝑘𝑛

′𝑊

𝐿𝑉𝐺𝑆 − 𝑉𝑡ℎ

2

INEL 4201 – PN Junction 10/28/2019

Electronics I22

Exercise 5.5

An n-channel MOSFET operating with Vov=0.5V exhibits a linear resistance rDS=1kΩ when vDS is very small.a) What is the value of the device trans-conductance parameter Kn?b) Assuming λ = 0, what is the value of the current ID obtained when vDS is increased to 0.5V? And to 1V?c) Assuming an λ = 0.1V-1, what is the value of the current ID obtained when vDS is increased to 0.5V?

And to 1V?