HW #4 Chapter 4 (MOSFET Circuits)analog.postech.ac.kr/3.Class/1.Classes/14_331/CH04A.pdf · 2002....

Electronic Circuit 1 Ch-4

due 6/19(Thr)

Discussion session: 6/19(Thr), tentative

Quiz 4: 6/20(Friday) 10am~12pm, tentative

Late penalty: -20% / 24 hours(HW portion in total grading: 30%)

EECE331 Electronic Circuits 1, Spring Semester, 2014

HW #4: Chapter 4 (MOSFET Circuits)


347

MOSFETMetal Oxide Semiconductor Field Effect Transistor


348

http://www.computerhistory.org/semiconductor/timeline/1960-MOS.html


349

Cross section of NMOS capacitor

oxide(SiO2)

p type silicon substrate

Al

B

VGB

G


350

MOSFET : voltage controlled resistor, VCCS


351

MOSFET operation

substrate(bulk)

p+ p+Inversion carrier

oxide

Source

Drain

L

n type silicon substrate

Depletion region

(free hole)

n+ poly

Gate

(b)0BSV

cross section of PMOSFET


352

Comparison of MOSFET depletion region with PN junction


353

NMOS capacitor : accumulation, depletion, inversion


354

MOSFET operation

n+

Drain

Depletion region

n+ Inversion carrier

oxide

Source

L

P type silicon substrate

substrate(bulk)

(free electron)

n+ poly

Gate

(a) 0BSV

cross section of NMOSFET


355

Channel inversion(逆轉, 反轉) of NMOSFET


356

Inversion state of NMOS capacitor ? (compared to PN junction)

A state in which the inversion carriers at silicon surface near oxide can stay at surface without dispersing toward the silicon substrate.

Inversion carrier: free electrons in P-substrate, free holes in N-substrate

The voltage drop across silicon (Vsi.max = 2 phi F + VCB)


357

NMOSFET : accumulation, depletion, inversion


358

Difference between MOSFET & MOS capacitor

• Channel inversion carriers are supplied from _____&______

• Bias can be applied to an ________ channel through the source & draincontacts

n+ n+

Inversion carrier (free electron))

n+ poly gate

oxide

p type silicon substrate

Depletion region

CBVGBV

CBV


359

Electron fills in all hole positions: No free carriers

B--

--

-

- -

Si

Si

Si

--

-

Depletion state Inversion state

Free electrons are added in the Depletion region.

FsiV 2Similar to the built-in potential of PN junction


360

Inversion state

FsiV 2 Similar to the built-in potential of PN junction

No free carriers can cross the junction

N-type region(channel) can be maintained at the surface


361

)(arg THGCoxN VVCqdensityechInversion

Gq

F

ox

SSFBGCox C

QVVC 2

CBFoxD VCq 2

FCBFFBTH VVV 22

MOSFET operation


362

CBFFox

impFBTH V

Cq

VNMOSV 22)(

CBFFox

impFBTH V

Cq

VPMOSV 22)(

real

(NMOS) versus

CBF V2

CBF V2THV

THV

oxSSsiGFB CQV

2 distinct slopes Due to Channel doping to adjust

threshold voltage

Threshold voltage equation

MOSFET operation


363

MOS level 1 mode: current equation

SBFFFBTHTHVVVyV × 22)0()(

SPICE level 1 model: two assumptions for simple derivation of ID

(Assumption 1) VTH(y) = VTH(0) for all y ( )Ly 0

(Assumption 2) Channel carrier mobility is constant independent of

bias voltages (VGS, VDS, VBS)

MOS level 1 model: current equation


364

SBFFFBTHTH VVVyV 22)0()(

SBFsisi VVyV 2)0()(

))()(()( yVyVCyq THGCoxN

))(()( yVVVCyq THGSoxN



365

DD IyI )( )cdiffusion ()cdrift( urrenturrent

dy

ydqD

dyydVyqW N

nNn)()()(

)())((0

ydVyVVVCWLI DSVTHGSoxnD ))0()(( NNn qLqDW

Integrate the above equation from source(y=0) to drain(y=L)



366



367

DSDSTHGSoxnD VVVVLWCI

21 DSoxn V

LWCD

DSDSTHGSoxn VVVVL

WC

21 DSToxn VV

LWC

DSGSoxnD VVLWCI __________



368



369

0)())(()( DSTHGSoxTHGSoxN VVVCLyVVVCLyq

Pinchoff Voltage VDSAT

VDS value where the inversion charge density at the drain end ofchannel becomes 0

THGSDSAT VVV

Saturation region: VDS > VGS – VTH VD > VG - VTH



370

LL V

THGSoxnD ydVyVVVCWdyI DSAT

0 0)())((

)(

)0()(

LLq

q NnN

NydqDW

2)(21)( THGSoxnD VVCWLLI )0(Nn qDW

2)(21

THGSoxnD VVCLL

WI

)( THGSToxn VVVCLL

W

2)(21

THGSoxnD VVCLL

WI

Saturation region current equation



371

)(2DSATDS

A

si VVqN

L

DSVLL

)1(111

1

111DSV

LLL

LLLLLL

Channel Length Modulation

Channel length modulation factorSUBNL

1

For smaller channel length(L), the larger lambdadecreases the small-signal output resistance & voltage gain



372

)1(21)( DSDSDSTHGSoxnDDSATDSTHGS VVVVV

LWCIVVandVVif

)1()(21)( 2

DSTHGSoxnDDSATDSTHGS VVVLWCIVVandVVif

0)( DTHGS IVVif




373

)(2

DSATDSA

si VVqN

L

DSVLL

)1(111

1

111DSV

LLL

LLLLLL

Channel Length Modulation

Channel length modulation factorSUBNL

1


For smaller channel length(L), the larger lambda decreases the small-signal output resistance & voltage gain


374

)1(21)( DSDSDSTHGSoxnDDSATDSTHGS VVVVV

LWCIVVandVVif

)1()(21)( 2

DSTHGSoxnDDSATDSTHGS VVVLWCIVVandVVif

0)( DTHGS IVVif

MOS level 1 model: current equationUsed for hand analysis

복습 MOS level 1 model: current equation


375

SPICE MOSFET (Large signal model)

(a)

CGD

D

CBD

VGD

G VDS

VBD

VBS

CBS

CGB

BID

VGS

+ _

++

rs

rd

S

+

__

_

_+

CGS


376

S

CBD

gbd

gbs

CBSrs

gdsgmbvbs

gmvgs

CGD

CGS

rd

G

D

B

CGB

(b)

SPICE MOSFET (Small signal model)


377

SPICE level 1 parameters

-11LEVEL

0.80.8PHI

TOX

LD

LAMBDA

0.4370.822GAMMA

128335UO

-0.9380.672VTO

단위PMOSFETNMOSFET모델 파라미터

21002.4 21025.7

71075.1 91032.8

81025.2 81025.2

V

sec/2 Vcm

V

V/1

m

m

V

mLW 2.1/20/ mLW 2/20/

SPICE MOSFET model


378

0.0E+0

1.0E-5

2.0E-5

3.0E-5

4.0E-5

5.0E-5

6.0E-5

0.0 1.0 2.0 3.0 4.0 5.0

-ID(A)

-VDS(V)

VGS=-1.2, -1.4, -1.6VVBS=0

0.0E+0

5.0E-5

1.0E-4

1.5E-4

2.0E-4

2.5E-4

3.0E-4

3.5E-4

4.0E-4

4.5E-4

0.0 1.0 2.0 3.0 4.0 5.0

ID(A)

VDS(V)

VGS=1, 1.2, 1.4VVBS=0

(a)

(b)

SPICE level 1 Dot: SPICE simulation, Solid: measurement (a) NMOSFET; W/L=20/1.2um (b)PMOSFET; W/L=20/2um

SPICE MOSFET model


379

DSTHGSoxnD VVVLWCI 1

21 2

MOSFET as an amplifier

Operate MOSFET in saturation region in an amplifier circuit(∵ both gm & ro are maximized in the saturation region )


380

DSTHGSoxnD VVVLWCI 1

21 2

_________2 D

oxnGS

Dm

ILWC

VIg

mBS

THm

BS

Dmb g

VVg

VIg

3.0~1.0:22 BSF V

______1

1

DS

Do V

Ir

___________ FBTH VV

◦ Small-signal model in Saturation region


381

◦ Small-signal equivalent circuit of NMOSFET

gsmg

D

G B

S

CGD

CGS

CGB

CSB

CDB

or1

bsmbg

the same small-signal equivalent circuit: the same in both PMOSFET & NMOSFET


382

◦ Small-signal equivalent circuit(等價回路) of MOSFET

gsmg

D

G BS

CGD

CGS

CGB

CSB

CDB

or1

bsmbg

◦ Junction capacitance

MJSWBD

MJBD

DB

PBV

PDCJSW

PBV

ADCJC

11

MJSWBS

MJBS

SB

PBV

PSCJSW

PBV

ASCJC

11

◦ Small-signal equivalent circuit of MOSFET


383

◦ gmb neglected⇒ T equivalent circuit

G B

gsmg

D

S

or1

bsmbg

gsmg

D

S

D

S

igG(ig=0)

ig=0G

The same terminal current

D

S

ig=0

D

S

G

T equivalent circuit

or1

gsmg

or1

gsmg

gsmg

or1

mg

si

or1

mg

CGD

si

◦ T equivalent circuit


384

HW #4 Chapter 4 (MOSFET Circuits)analog.postech.ac.kr/3.Class/1.Classes/14_331/CH04A.pdf · 2002....

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Transcript of HW #4 Chapter 4 (MOSFET Circuits)analog.postech.ac.kr/3.Class/1.Classes/14_331/CH04A.pdf · 2002....