Montpellier, France, April 10, 2008 - - TU Kaiserslautern · [email protected] 24 April 2008...

[email protected]

24 April 2008

The 3rd Workshop on Reconfigurable Computing Education (RC education), April 10, 2008, Montpellier, France 1

Reiner Hartenstein, TU Kaiserslautern, Germanyhttp://hartenstein.de

Reconfigurable Computing to solve the CS Education Dilemma

(keynote address)

Reiner Hartenstein

TU Kaiserslautern

Montpellier, France, April 10, 2008

RC education 2008

© 2008, [email protected] http://hartenstein.de

TU Kaiserslautern

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Demonstrating the intensive Impact

(FPGA-based speed up and power saving)

DES breaking [T. Elghazawi et al.: IEEE COMPUTER, Febr. 2008]

Platform (compared to Beowulf cluster)

Speed-up factor

Power saving factor

SDC-6 6757 856

Cray XD-1 12162 608

SGI Atix 4700 with RC 100 RASC 28514 3439

encryption on von Neumann getting unaffordable

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The clash of Paradigms (a simplified view)

Computation in time (procedural-only von Neumann mind set)

Computing in space (structural mind set)

Reconfigurable Computing model: supersystolic mind set -

data-stream-based

… you can teach programming to a hardware guy

… you can teach programming to a hardware guy

you can’t teach hardware to a programmer, although …

you can’t teach hardware to a programmer, although …

This is the fault of our CS curriculaThis is the fault of our CS curricula

traditional CS model : Software-only mindset -instruction-stream-based

sequential mindset parallel pipelining mindset

procedural structural


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Tear down this Wall !

… to achieve a far-ranging paradigm shift, away from the monopoly-like dominance of the instruction-stream-based vN mind set,

… to clear away the wreckage of CS foundations having survived the mainfrage age, and, having collapsedunder the weight of its own absurdity.

over to a dichotomic dual paradigm basic model including the Reconfigurable Computing mind set.

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24 April 2008




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>> Outline <<

• Inefficient Microprocessors

• The von Neumann Syndrome

• The twin paradigm approach is needed

• The CS education dilemma

• Conclusions

http://www.uni-kl.de


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Microprocessor Industry (1)

We are o.k. ? You are o.k. ?

go multi-threading? - transactional memory? – MPI? … ?

“… we have a tool package for manycore programmers…”

Leadership in the Future

We are witnessing a radical change of the entire industry

away from single-processor chips to new generations ofmulti-processor chips called manycores,

“intel has thrown a hail mary pass …”

[Dave Patterson]

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24 April 2008




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Climate Change in Computing

Wawrzynek missing

(my birthday)


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What Climate change ?

Now intel goes toward 1024 chickens

intel„s strong oxen under Andy Grove and Craig Barret: up to 5 GHz clock speed [til 2005]

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24 April 2008




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Microprocessor Industry (2)

Gordon Moore indicating performance? (corrected twice)

Stop at >100 Watts per core

More performance by more transistors? -> imagination! -> phantasy!

-> la raison

La raison, c'est l'intelligence en exercice; … [Victor Hugo]

… seamless improvement of performance …… from generation to generation?

Leadership in the past

-> raison?


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Rapid Decline of Computational Density

[BWRC, UC Berkeley, 2004]

1990 1995 2000 2005

200

100

0

50

150

75

25

125

175

SP

EC

fp2

00

0/M

Hz/B

illio

n T

ran

sis

tors

HP

alph

a: d

own

by

100

x in

6 y

rsIB

M:

dow

n by

20

x in

6 y

rs

stolen from Bob Colwell

memory wall, caches, ...

[Wawrzynek; Sep 8, 2005, GSRC Symposium (GSRC‟05) ]

architecture overhead

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24 April 2008




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Victor Hugo

La raison, c'est l'intelligence en exercice; …

…l'imagination c'est l'intelligence en érection. [Victor Hugo]


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Justin Rattner‟s DAC keynote

Rattner predicts the impact of the industry's move toward the ubiquitous use of wireless communications and the challenges that this very high level of integration will have on design automation, from architecture to manufacturing.

… and, how design techniques will evolve, by necessity, to satisfy the demands of reconfigurable hardware and software programmability.

He will address how the combination of new radio architectures and mostly digital implementations will drive a new generation of design tools, and …

“EDA for Digital, Programmable, Multi-Radios.”

the demand elsewhere (outside intel) ???

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24 April 2008




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The biggest problem in CS history

Manycore requires a fundamental change in programming:drastically more complex than uniprocessor programming.

This requires to understand new computational principles,algorithms, and programming tools.

We need new directions in R&D

The Manycore Programing Crisis

Reconfigurable Computing is an inevitable ingredient of the crisis’s solution


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>> Outline <<



• The twin paradigm approach is needed


• Conclusions


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24 April 2008




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A List of Massive Overhead Phenomena

overheadvon Neumann

machine

instruction fetch instruction stream

state address computation instruction stream

data address computation instruction stream

data meet PU + other overh. instruction stream

i/o to/from off-chip RAM instruction stream

Dijkstra 1968: The Goto considered harmful

R.H. & Koch 1975: The universal Bus considered harmful

Backus, 1978: Can programming be liberated from the von Neumann style?Arvind et al., 1983: A critique of Multiprocessing the von Neumann Style

all this overhead piling up to code sizes of astronomic dimensions

von Neumann Syndrome[C.V. “RAM” Ramamoorthy]

von Neumann Syndrome[C.V. “RAM” Ramamoorthy]

CPUCPU single CPU

von Neumann


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Data meeting the Processing Unit (PU)

by Software

inefficiently

routing the data by memory-cycle-hungry instruction streams thru shared memory

the pianist is the „PU“

This is just one of many von Neumann overhead phenomena

Moving data

data

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manycore von Neumann: arrays

of massive overhead phenomena

overheadvon Neumann

machine





i / o to / from off-chip RAM instruction stream

proportionate to the number of processors

CPUCPU single CPU

von Neumann

17

Inter PU communication instruction stream

message passing overhead instruction stream

transactional memory overh. instruction stream

multithreading overhead etc. instruction stream

disproportionate to the number of processors

CPUCPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

or, 16 core SoCexample: 16 CPUs running in parallel


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Code sizes of astronomic dimensions

Fast on-chip memory cannot store such huge instruction code sizes

… no way around von Neumann bottlenecks

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24 April 2008




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Reconfigurable Computing

overheadvon Neumann

machinehardwired

anti machinereconfigurableanti machine

instruction fetch instruction stream none*

state address computation instruction stream none*

data address computation instruction stream none*

data meet PU + other overh. instruction stream none*

i / o to / from off-chip RAM instruction stream none*

Inter PU communication instruction stream none*

message passing overhead instruction stream none*

transactional memory overh. instruction stream none*

multithreading overhead etc. instruction stream none*

rDPUrDPU

rDPUrDPU

rDPUrDPU

rDPUrDPU

rDPUrDPU

rDPUrDPU

rDPUrDPU

rDPUrDPU

rDPUrDPU

rDPUrDPU

rDPUrDPU

rDPUrDPU

rDPUrDPU

rDPUrDPU

rDPUrDPU

rDPUrDPU

rDPA: reconfigurable datapath arrayrDPA: reconfigurable datapath array

(coa

rse-

grai

ned

rec.

)(c

oars

e-gr

aine

d re

c.)


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von Neumann overhead: just one example

overheadvon Neumann

machine





i / o to / from off-chip RAM instruction stream

CPUCPU single CPU

reconfigurable address generator (GAG): ~20x speed-uprDPUrDPU

rDPUrDPU

rDPUrDPU

rDPUrDPU

PISA DRC accelerator [ICCAD 1984]

(entire project: 15000x speed-up)

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24 April 2008




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Declining Programmer Productivity

At particular HPC application domains

massive parallelism requires 10 – 30

professionalists in multi-disciplinary

multi-insitutional teams for 5 - 10 years

[Douglass Post, DoD HPCMP, panelist at SC07]

The Law of More: programmer

productivity declines disproportionately

with increasing parallelism

Software done: machine obsolete


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Dead Supercomputer Society

•ACRI •Alliant •American Supercomputer

•Ametek •Applied Dynamics •Astronautics •BBN •CDC•Convex•Cray Computer •Cray Research •Culler-Harris •Culler Scientific •Cydrome •Dana/Ardent/ Stellar/Stardent

•DAPP •Denelcor •Elexsi •ETA Systems •Evans and Sutherland•Computer•Floating Point Systems •Galaxy YH-1 •Goodyear Aerospace MPP •Gould NPL •Guiltech •ICL •Intel Scientific Computers •International Parallel Machines

•Kendall Square Research •Key Computer Laboratories

a wave of bankruptcies, consolidations, and, changing business objectives

•MasPar•Meiko •Multiflow •Myrias •Numerix •Prisma •Tera •Thinking Machines •Saxpy •Scientific Computer•Systems (SCS) •Soviet Supercomputers •Supertek •Supercomputer Systems •Suprenum •Vitesse Electronics

[Gordon Bell]

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24 April 2008




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>> Outline <<



• We need the twin paradigm approach


• Conclusions



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The von-Neumann-only model

algorithms variable

resources fixed

instruction-stream-based computing:

µprocessorµprocessor

Software

instruction-stream

programmable

algorithms variable

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algorithms variable

resources fixed


algorithms variable

resources variable

data-stream-based reconfigurable computing:

Software

instruction-stream

acceleratorsacceleratorsµprocessorµprocessor

Configware

resources variable

programmable

algorithms variable

Nick Tredennick‟s view

algorithms variable

Flowware


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algorithms variable

resources fixed


algorithms variable

resources variable


instruction-stream

resources variable

algorithms variable

Twin paradigm manycore model

algorithms variable

Configware

Flowware

rDPUrDPU

rDPUrDPU

rDPUrDPU

rDPUrDPU

rDPUrDPU

rDPUrDPU

rDPUrDPU

rDPUrDPU

rDPUrDPU

rDPUrDPU

rDPUrDPU

rDPUrDPU

rDPUrDPU

rDPUrDPU

rDPUrDPU

rDPUrDPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

Software

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algorithms variable

resources fixed


algorithms variable

resources variable


instruction-stream

resources variable

algorithms variable

Software/Configware Co-Compilation

algorithms variable

Configware

Flowware

rDPUrDPU

rDPUrDPU

rDPUrDPU

rDPUrDPU

rDPUrDPU

rDPUrDPU

rDPUrDPU

rDPUrDPU

rDPUrDPU

rDPUrDPU

rDPUrDPU

rDPUrDPU

rDPUrDPU

rDPUrDPU

rDPUrDPU

rDPUrDPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

Software

software/configwareco-compiler

C language source

Academic Academic demodemoimplementationimplementation ofof such a such a compilercompiler in in thethe midmid„ 90ies„ 90ies

Academic Academic demodemoimplementationimplementation ofof such a such a compilercompiler in in thethe midmid„ 90ies„ 90ies


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The time has come …

Twin paradigm CS education is inevitable

All, even early, undergrad courses should include

reconfigurability and both kinds of parallelism

[email protected]

24 April 2008




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Terminology clean-up

Software: for scheduling instruction streams

Flowware: for scheduling data streams

Configware: for configuring morphware

Programming sources:

vonNeumann

non-vonNeumann

Morphware: „soft hardware“, reconfigurable platforms


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>> Outline <<




• The anti machine


• Conclusionshttp://www.uni-kl.de

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24 April 2008




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The 2nd

paradigm: ready to go

the urgently need

datastream-based

machine paradigm:

pepared almost

30 years ago …

the urgently need

datastream-based

machine paradigm:

pepared almost

30 years ago …

xxx

xxx

xxx

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||

x xx

x

xx

x x

x

- -

-xxxx

xx

xxx

---

---

---

---

xxx

xxx

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| data streams

… with systolic arrays… with systolic arrays


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DPA

xxx

xxx

xxx

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x x

x

x

x

x

x x

x

- -

-

input data streams

xx

x

x

x

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x

--

-

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-

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-

-

-

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xxx

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|output data streams

time

port #

time

time

port #time

port #

Flowware defines: ... which data item at which time at which port

Data streams

(flowware)

(pipe network)

systolic array research: throughout the 80ies:

Mathematicians‘ hobby

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Data streams

The clearest and common elementary definition !

datastream ≠ dataflow

… be careful: a lot more definitions are around, derived from local perspectives

(the old “dataflow machine” is indeterministic! )


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Early Systolic Synthesis

Mathematicians like to wax rhapsodic about the elegance, beauty and depth of their proofs.

John Horgan: „The Endof Science Revisited“

Mathematicians liked thebeauty and elegance of Systolic Arrays.

Due to a lack of depth in reasoning, their efforts yielded poor synthesis algorithms.

R. H.

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24 April 2008




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Algebraic Synthesis Method

algebraic tunnel view:

array[history] mapping

uniform only

shape resources

systolic [1979]

algebraiclinear only

uniform only

mathematicians‟ paradigm trap


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uniform only suitable for what

applicationsshape resources

systolic [1979]


uniform only

strictly regular data dependencies

only

Algebraic synthesis methodes: usable

only for a small minority of applications!

Algebraic: what applications?

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24 April 2008




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Pipe Networks


uniform only Suitable for what

applicationsshape resources

systolic [1979]


uniform only

strictly regular data dependencies

only

rDPA: super-systolic

[1995]

simulated annealing no restrictions at all


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Who generates the Data Streams?

xxx

xxx

xxx

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x x

x

x

x

x

x x

x

- -

-

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x

x

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xxx

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Without

a sequencer

it is not

a machine !

[email protected]

24 April 2008




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Mathematics: Winner of the

“Not My Job” Award

„it„s not our job“


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But there are Asymmetries

von Neumann paradigm Antimachine paradigm

Software EngineeringSoftware Engineering

Configware EngineeringConfigware Engineering

ASM

CPU

location of the

sequencer

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The counterpart of the

von Neumann machine

xxx

xxx

xxx

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x x

x

x

x

x

x x

x

- -

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x

x

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-

-

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xxx

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(r)DPA

ASM

ASM

ASM

ASM

ASM

ASM

AS

M

AS

M

AS

M

AS

M

AS

M

AS

M

datacounter

GAG RAM

ASM: Auto-Sequencing

Memory

data counters instead of a program counter

data counters: located at memory(not at data path)

coarse-grained


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Data meeting the Processing Unit

byConfigware

placement of the execution locality ...

… pipe network generated by configware compilation

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24 April 2008




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Toward hetero manycore chips

Each standard core should have a mode bit to select:•Running in CPU mode, or,•Running in DPU mode*

CPUCPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

also CPU clusters routable

CPUCPU

DPUDPU

*) program sequencer switched off

DPUDPU

DPUDPU

DPUDPU

DPUDPU

DPUDPU

DPUDPU

DPUDPU

DPUDPU

DPUDPU

DPUDPU

DPUDPU

DPUDPU

DPUDPU

DPUDPU

DPUDPU

DPUDPU

DPUDPU

DPUDPU

DPUDPU

DPUDPUDPUDPU

DPUDPU

DPUDPU

DPUDPU

DPUDPU

DPUDPU

DPUDPUDPUDPU

DPUDPUDPUDPUDPUDPUDPUDPU

•4 (or, 6) nearest neighbor connect

additional backplane interconnect fabrics

for legacy software and supervisory tasks


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The twin paradigm approach

CPUCPU

CPUCPU

CPUCPU

CPUCPU

rDPUrDPU

rDPUrDPU

rDPUrDPU

rDPUrDPU

rDPUrDPU

rDPUrDPU

rDPUrDPU

rDPUrDPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

heterogenousmanycore system

Software/ Configware

Co-compilation

DPUDPU

DPUDPU

DPUDPU

DPUDPU

DPUDPU

DPUDPU

DPUDPU

DPUDPU

DPUDPU

DPUDPU

DPUDPU

DPUDPU

DPUDPU

DPUDPU

DPUDPU

DPUDPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

CPUCPU

[email protected]

24 April 2008




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>> Outline <<





• Conclusions



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The CS education dilemma

On the way between hardware mind set and software mind set we find a major roadblock.

Removing this brick wall is very simple by using very old straight-forward wisdom.

This is due to a reductionist tunnel view, a paradigm trap, partly driven by arrogance.

Educators and curriculum task forces caused this brick wall by decades of ignorance.

[email protected]

24 April 2008




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Software to Configware Migration

SNN filter on supersystolic array

rDPU not used used for routing only operator and routing port location markerLegend: backbus connect

rout thru only

not usedbackbus connect

example: brick wall in the brain


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Brick wall in the Brain

After this talk* a VIP jumps up from the floor: „But you can„t implement decisions!“

This statement has been highly embarrassing since it came from a top level IT R&D manager, of a large electronics/computer industry group

*) RAW workshop, late 90ies at Orlando, Florida

We immediately see the brick wall in his brain

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24 April 2008




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„But you can„t implement decisions!“

S = R + (if C then A else B endif);

=1

+

ABR C

section of a very large pipe network:

C. G. Bell et al: IEEE Trans-C21/5, May 1972

W. A. Clark: 1967 SJCC, AFIPS Conf. Proc.

decision box turns

into a multiplexer*

Software to

Configware

Migration:

“That’s so simple! why did it take 30

years to find out?”

in the year 1971**:

**) the hardware description

languages community


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>> Outline <<





• Conclusions


[email protected]

24 April 2008




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[Kornecki (& R.H.)]

CS curricula must represent today’s computing reality by focusing on parallel, reconfigurable, and distributed computing, not only introducing the loop in CS I

We need to change the Computer Architecture courses for introducing parallel, reconfigurable, and distributed computing in early undergraduate CS courses without involving complicated problems and in-depth analysis.

What matters most is that, from the start, we expect students to consider the world of computing as filled with hetero multiprocessor machines.


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We need a dual paradigm approach

structural procedural

instruction-stream-based

conducted by

a program counter

data-stream-

based

conducted

by data counters

CPUCPU

progra

m

counter

DPUrDPUrDPU

DPUDPU(hardwired)(hardwired)

ASMASMdata

counter

[email protected]

24 April 2008




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RC and parallelism

Nothing is more powerful than an idea whose time has come.

Rien n'est plus puissant qu'une idée dont le temps est venu.

Victor Hugo1802-1885

The time has come for parallelism and RC to be introduced in undergraduate CS and ECE courses


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thank you for your patience

[email protected]

24 April 2008




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END

Montpellier, France, April 10, 2008 - - TU Kaiserslautern · [email protected] 24 April 2008...

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