Module18:SoC Platform Prototypes

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송태훈

2Copyright 2003ⓒ

( 모듈 18) 목차 SoC Platform Prototype 5 Design Step for SoC Prototype Processor-based Prototyping Development Tools ARM Device Overview Verification Tools Configuration Method

3Copyright 2003ⓒ

Products are needed To increase performance, reduce costs and enhance

features The use of newer, faster and cheaper technologies More functions and features to be placed on a single piece

of silicon Integrated in a system-on-chip with new functions added.

Peripheral Devices are needed

These include timers, DMA engines, interrupt controllers and memory controllers

In many cost-sensitive applications, a shared memory structure is utilized to reduce memory component costs

SoC Platform Prototype

4Copyright 2003ⓒ

Embedded Processor ARM : ARM922T, ARM926EJ-S, ARM1136 Altera : Excalibur (ARM922T, FPGA) Motorola : PowerPC XilinX : Virtex II Pro (IBM405GP, FPGA) MIPS : MIPS4K

Re configurable FPGA XilinX Virtex II, Spartan Altera Stratix, Cyclone, APEX, Excalibur

Memory Block SDRAM, DDRRAM Flash Memory

SoC Platform Prototype

5Copyright 2003ⓒ

All the peripheral functions required for a basic SOC UART, Ethernet 10/100M, 1394, USB2.0 PCI, PC104, PCMCIA, CF+, Cardbus DMA, Interrupt Request, TFT LCD, Text LCD, FND Key PAD, LED, PB Switch

IP MP3, MPEG4, H.264, MJPEG, JPEG, Memory Controller, PCI USB Controller, UART Controller etc

Bus Architecture AMBA Spec. 2.0

Operating System Linux, Nucleus RTOS, Vxworks, Qplus

SoC Platform Prototype

6Copyright 2003ⓒ

SoC Platform Prototype Example

GeneralCPU

DSP

ActuatorController

PL

Ls

SensorController

DisplayController

Configure FPGA/CPLD

ADC/DAC

NetworkInterface

USB/UART표준

Interface

Network기능 지원

AnalogInterface

ReconfigurableH/W

S/W

구동 / 통신기능 지원

RTOS

7Copyright 2003ⓒ

5 Design Step for SoC

8Copyright 2003ⓒ

HW DevelopmentSW Development

SW IntegrationHW RTL Model

Real Prototype : Validation/Qualification

SWDev.

EDATools

HWDev.

Software Hardware

Real HW

SW Design HW Design

System Specifications

Traditional Design Step for SoC

9Copyright 2003ⓒ

Architectural Design

PlatformSpecification

SW Generation

Virtual Prototype

SW IntegrationHW RTL Model

Real Prototype : Verification

SWDev.

Architectures

EDATools

Boards

HWDev.

Functional DesignIdeal Architecture

Virtual Architecture

SystemDesignEnvironment

Co-Simulation

Software Hardware

Real HW

DetailedCo-Simulation

SystemDesign

System Specifications

Design Step for SoC

SoC Platform PrototypeProcessor-based Prototyping

11Copyright 2003ⓒ

SoC Platform Prototype

12Copyright 2003ⓒ

Spec Hardware

Excalibur  ARM922T (1020pin )

FPGA Gates  100 만 게이트 동작 속도  AHB1 : 200MHz, AHB2 : 100MHz

내부 메모리  SRAM : 256K, DPRAM : 128K

Flash 16MB

SDRAM  128MB 기본 , 최대 512MB 설치EPC2  16MB (2M × 8EA)

Multi ICE   에뮬레이터 포트JTAG   파일 다운로드 , 디버깅 포트ETM  ARM9 Embedded Trace Macrocell

COM Port 통신 포트 2EA

Camera Port  CMOS Image Sensor

SoC Platform - Hardware

13Copyright 2003ⓒ

Spec. Hardware

USB  Universal Serial Port

Ethernet  10/100M bps 이더넷 포트

IDE  HDD 인터페이스 40 pin 포트TFT LCD  3.5 인치 칼라 TFT LCD

7 Segment  1EA

Text LCD  2 × 20 Text LCD

Keypad  1,2,3,4,5,6,7,8,9,0 Key

Expansion Port  100  핀 외부카드 , AD/DA Port

SoC-LiNUX  SoC-LiNUX Ver 2.4.19

IP 및 리눅스BSP

 Ethernet, USB, Text LCD, TFT LCD, IDE, 7-Segment, Keypad

SoC Platform - Hardware

14Copyright 2003ⓒ

Spec Software

Linux Kernel

 Kernel

 Kernel based on Linux 2.4.19

 Power management support

 JFFS2 Flash Memory File System

 Bootloader  BLOB

 Device Driver

 7-Segment device driver

 Text LCD device driver TFT LCD device driver

 LED device driver

SDRAM device driver

 3.5” Color TFT LCD device driver

 UART device driver

 USB device driver

10/100M bps Ethernet device driver

SoC Platform - Software

15Copyright 2003ⓒ

Quartus II

설계사양 정의

( 기능 , 타이밍 )

Hardware Software

Debugger+Trace Analyzer

Multi ICE, Multi Trace

Verilog / VHDL 코딩ModelSIM

ADS Compiler/Linker/Relocator

하드웨어 소프트웨어

SoC PlatformARM922T+FPGA

LiNUX 운영체제Nucleus OS

User Code

Libraries

SoC-LiNUXEthernet, TFT LCD, USB, IDE, Camera Interface

C Header files

Peripheral drivers

SoC Platform Design Flow

C 코딩

16Copyright 2003ⓒ

5 wire JTAG

Trace Debug Tools running

on hostData

Address

Control

BREAKPTEmbeddedICE

Execution Unit

SoC

ARM CPU Macrocell

ETM

Trace Port

Multi-ICE

MultiTRACE

TAPJTAGPort

Debugging – Multi-ICE

17Copyright 2003ⓒ

Block Diagram

18Copyright 2003ⓒ

Co-Simulation Hardware/Software Co-Simulation

ModelSIM ADS

SoC Platform PrototypeDevelopment Tools

20Copyright 2003ⓒ

• 회로 설계및 시뮬레이션 , 에뮬레이션 환경 (1) Altera Quartus – EDA Software Tools(2) ARM Developer Suite 1.2 – C Compiler

ARMasm(Assembler), Compilers (ARM C/C++ Compiler)ARMlink (ARM linker), AXD – ARM debugger, Adwu – ARM debugger for windows/UnixFromelf – Format Changer (ELF to other formats)

(3) ModelSIM - Simulator(4) ARM Multi ICE - Emulator

• 리눅스 운영체제 (1)SoC-LiNUX O.S. 2.4.x Kernel (2)SoC-GNU Cross Compiler Tool Kit (3)SoC-LiNUX Bootloader

Development Tools

21Copyright 2003ⓒ

S/W Requirements - Quartus

22Copyright 2003ⓒ

S/W Requirements – Verilog HDL, VHDL

23Copyright 2003ⓒ

S/W Requirements - ModelSIM

24Copyright 2003ⓒ

ADS C Compiler

SoC Platform PrototypeARM Device Overview

26Copyright 2003ⓒ

ARM922T Features 32 Bit RISC Processor

200MHz ARM922T™

High Performance .18 µm Process AMBA™ Bus Architecture

Industry Standard Bus Architecture 내부 Memory

Single Port and Dual Port 외부 Memory

SDRAM, DDRSRAM, FLASH, SRAM

27Copyright 2003ⓒ

ARM922T Processor ARM922™ 기반 (ARM920™ Derivative)

고속 Cache (8KB Instruction + 8KB Data)

SRAM and DPRAM 내장 MMU 기능 (RTOS 지원 ) 200MHz on Altera® , 0.18u Process

향상된 system Debug 기능 내장 Based on ARM9TDMI core

Five stage pipeline Harvard bus architecture

ARM9 - T - Thumb Architecture ExtensionD - Core has Debug ExtensionsM - Core has an enhanced MultiplierI - Core has EmbeddedICE Logic Extension

28Copyright 2003ⓒ

ARM + FPGA 구조

PLL

Timer

UART

InterruptControllerWatchdog

Timer

JTAG

256 Kbytes SRAM128 Kbytes DPRAM

EmbeddedProcessorStripe

PLD

100 만 게이트 FPGA

TraceModule

ARM922T

SRAM

DPRAM

ExternalMemory

InterfacesProcessor & Interfaces

I-CACHE D-CACHE

ARM 8K Bytes 8K Bytes

LEs 38400

ESB Bytes 40K

Excalibur – ARM922T

29Copyright 2003ⓒ

AMBA High Performance Bus (AHB) AMBA - Advanced Micro-controller Bus Architecture Embedded Stripe and PLD Devices 연결 200MHz Maximum Clock Rate 32 Bit Wide Pipelined Bus

Burst transfers - one cycle per data word Multi-master With Distributed Address Decoding

Single-cycle bus master handover Split Transactions Extensions

multi-master bus 에서 bus Bandwith 이용 극대화 가능

30Copyright 2003ⓒ

PLL’s PLL’s Provide Clock Boost Multiplication Only

Default power-up operation is bypass Program control registers through configuration logic or the embedded pro

cessor State machine control to put PLL in bypass mode if lock is lost Can change PLL frequency with proper software control

PLL1 Clock for processor and peripheral bus Up to 400 MHz operation divided by 2 or 4

PLL2 Clock for the SDRAM controller Up to 266 MHz operation

31Copyright 2003ⓒ

Memory HierarchyHard Logic PLD

AHB 1-2Bridge

SDRAMController

PLD Application Interfaces

Single Port SRAM #1

Processor+

MMU+

Cache

AHB1 AHB2

Memory Mapped Peripherals

SDRAMSRAM Flash

PLD - AHB2 Bridge

PLDMaster(s)

BusExpansion

Single Port SRAM #2

Arbiter #1 Arbiter #2

Dual Port SRAM #1

Dual Port SRAM #2

Depth / Width Muxing

PLD Master Bus Clk is application dependent

Secondary Bus(AHB2) <= 100MHzProcessor Local Bus

(AHB1) <= 200MHz

AHB2

Arbiter #1 Arbiter #2

AHB1

32Copyright 2003ⓒ

SDRAM Controller Stripe 에 SDRAM External Memory controller Runs Asynchronously to AHB1 or AHB2 Byte, Half-word, and Word Transfers 2 Blocks and up to 512 Mbytes PC100/133 SDR SDRAMs

SDRAM must be initialized through software control

33Copyright 2003ⓒ

Expansion Bus Interface (EBI) External Memory Mapped Devices 에 인터페이스 기능 제공 Flash Memories or Memory Mapped Peripherals 와

AHB2 Bus Masters 사이에 속도 조절 기능 Four Chip Select Outputs

각 Address Space 는 8- or 16-Bit Mode 로 동작 가능 .

Split Bus Transactions 지원 다른 AHB2 Bus Masters 의 stalling 방지

Support both synchronous & asynchronous mode

34Copyright 2003ⓒ

UART 5 to 8 data bits 1 or 2 stop bits Even, odd, stick, or no parity 75 to 230,400 baud rate 16-byte transmit FIFO 16-byte receive FIFO. Programmable baud generator Internal diagnostic capabilities Modem communication support

35Copyright 2003ⓒ

Interrupt

Interrupt Controller

ARM 922T

Verification Tools

37Copyright 2003ⓒ

Bus Functional Model Verifies the ability of PLD Peripherals to AHB

Protocol AMBA AHB Masters and Slaves

Models AHB Transactions Includes Master Port and Slave Port Bus Transactors Models AHB Master and AHB Slave - Accepts and

Transmits AHB Protocol Signals

38Copyright 2003ⓒ

Embedded Stripe Model Verification

ROM Model

SDRAM Model

Excalibur Stripe

PLD Logic

Stripe-to-PLD (Master Port)

EBI Port

SDRAM Port

Master

Slave

PLD-to-Stripe (Slave Port)

Bus Functional Model Verification

Full Stripe Model Verification

39Copyright 2003ⓒ

Stripe Model Processor Timer Interrupt Controller UART EBI DPRAM, SRAM

SDRAM Controller AHB1-2 Bridge Stripe-to-PLD Bridge PLD-to-Stripe Bridge PLLs (limited model of behavior) PLD Configuration Not Modeled

WatchdogTimer

PLL

AHB 1-2Bridge

Dual Port SRAM

SDRAMController

Single Port SRAM

32 bit RISC Processor

Interrupt Controller

AHB1

AHB2

APEX 20KE

PLD - Stripe Bridge

PLDMaster

ConfigurationLogic Master

Reset Module

Timer

PLD Slave

UARTBus

Expansion (EBI)

Stripe - PLD Bridge

PLD Slave

PLDModule

PLDModule

40Copyright 2003ⓒ

Full Stripe Model

Verification Tool Flow

Netlist Output

Quartus II

Gate-Level / Timing

Excalibur MegaWizard

Configured Stripe

Instance

Top Level Design

User SelectionsPLD Logic

3rd Party Synthesis

Test bench

ROM model

SDRAM Model

C / Assembly

Code

ModelSim/VCS

BehavioralRTL

BFM

41Copyright 2003ⓒ

EBI Signals AHB Signals ALU Outputs Registers

Simulation Results

Configuration Methods

43Copyright 2003ⓒ

Configuration Methods Processor Centric

Boot From Flash PLD Centric

Passive Serial Passive Parallel JTAG

44Copyright 2003ⓒ

Configuration File in Flash

The intel .HEX programming file is generated by a combined effort of Quartus II and external softwares The .HEX component is made by Quartus II in Software Mode or by

external software tool The .SBI component is made by Quartus II in Hardware mode The .SBD component is made by the Excalibur MegaWizard

8-bit/16-bit FLASH

EBI

Excalibur ARM Processor

Quartus II User H/W Design Other IP

Quartus IIOR

Industry StandardCompiler/Linker/

Relocator

User S/WDesign Libraries RTOS

intel .HEX

.HEX

.SBI

=

+

.SBD+

45Copyright 2003ⓒ

Configuration Files in PLD-centric Mode

Serial / ParallelPLD

Configurator

Dowload Cable Excalibur ARM Processor

ConfigPort

OR

Quartus II User H/W Design Other IP

Quartus IIOR

Industry StandardCompiler/Linker/

Relocator

User S/WDesign Libraries RTOS

.SOF

.POF/

.RBF/

.TTF/

.HEXOUT

.SOF

.POF/

.RBF/

.TTF/

.HEXOUT

.HEX

.PSOF

=

+

.SBD

+

46Copyright 2003ⓒ

( 모듈 18) 참고문헌

www.altera.com www.arm.com www.cofluent.com