Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks...
Transcript of Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks...
![Page 1: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/1.jpg)
Modular Performance Analysis withReal-Time Calculus
Wolfgang Haid, Simon Perathoner, Nikolay Stoimenov, Lothar Thiele
ARTIST2 PhD Course on Automated Formal Methods for Embedded SystemsDTU - Lyngby, Denmark - June 11, 2007
![Page 2: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/2.jpg)
Computer Engineering and Networks Laboratory (TIK) 2
Presentation overviewIntroduction toSystem Level
Performance Analysis(Simon Perathoner)
ModularPerformance Analysis
(MPA)(Nikolay Stoimenov)
Real-Time Calculus(RTC)
(Wolfgang Haid)
Extensions to basic model(Wolfgang Haid)
Real-Time Interfaces(RTI)
(Nikolay Stoimenov)
Comparison withother approaches
(Simon Perathoner)
![Page 3: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/3.jpg)
Modular Performance Analysis withReal-Time Calculus
Simon Perathoner
1. Introduction to System Level Performance Analysis
ARTIST2 PhD Course on Automated Formal Methods for Embedded SystemsDTU - Lyngby, Denmark - June 11, 2007
![Page 4: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/4.jpg)
Computer Engineering and Networks Laboratory (TIK) 2
Embedded Real-Time Systems
Design & Analysis
Special-purpose information processing systems Embedded into larger productsMust meet real-time constraints
![Page 5: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/5.jpg)
Computer Engineering and Networks Laboratory (TIK) 3
Trends in Embedded System Design
parallel
distributed
heterogeneous
Architectures are increasingly:
Analysis and prediction ofsystem behavior is complex!
![Page 6: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/6.jpg)
Computer Engineering and Networks Laboratory (TIK) 4
System Level Performance Analysis
EmbeddedReal-Time System
InputStream
InputStream
![Page 7: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/7.jpg)
Computer Engineering and Networks Laboratory (TIK) 5
System level performance Analysis
Computational Resources ...
InputStream
InputStream
DSP I/O
μPCPU
![Page 8: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/8.jpg)
Computer Engineering and Networks Laboratory (TIK) 6
System Level Performance Analysis
... Communication Resources ...
Computational Resources ...
InputStream
InputStream
DSP I/O
μPCPU
![Page 9: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/9.jpg)
Computer Engineering and Networks Laboratory (TIK) 7
System Level Performance Analysis
Computational Resources ...
... Communication Resources ...
... Tasks (HW/SW Components)
InputStream
InputStream
I/O
μP
T4 T6
T3
T5
T2T1
![Page 10: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/10.jpg)
Computer Engineering and Networks Laboratory (TIK) 8
System Level Performance Analysis
InputStream
InputStream
I/O
μP
T4 T6
T3
T5
T2T1
Memory Requirements?
Processor Speeds?
Timing Properties?
Bus Utilization?
Bottleneck?
![Page 11: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/11.jpg)
Computer Engineering and Networks Laboratory (TIK) 9
Role in the design process
Application Architecture
AllocationMapping
Scheduling
Performance Analysis
Design SpaceExploration
![Page 12: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/12.jpg)
Computer Engineering and Networks Laboratory (TIK) 10
Challenges of Performance Analysis
InputStream
Complex Input:- Timing (jitter, bursts, ...)- Different Event Types
Task CommunicationResource sharing (Scheduling)
ab acc b
![Page 13: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/13.jpg)
Computer Engineering and Networks Laboratory (TIK) 11
Processor
Task
BufferInputStream
Task CommunicationResource sharing (Scheduling)
ab acc b
Complex Input:- Timing (jitter, bursts, ...)- Different Event Types
Variable Resource AvailabilityVariable Execution Demand- Input (different event types)- Internal State (Program, Cache, ...)
Challenges of Performance Analysis
![Page 14: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/14.jpg)
Computer Engineering and Networks Laboratory (TIK) 12
Formal Analysis vs. Simulation e.g. delay
Real System Simulation Formal analysis
Best-Case
Worst-Case
upper bound
lower bound
![Page 15: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/15.jpg)
Computer Engineering and Networks Laboratory (TIK) 13
Requirements for a formal PA method
Correctness
Accuracy
Embedding into the design process
Modularity
Short analysis time
![Page 16: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/16.jpg)
5-1Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
Modular Performance Analysis- Models, Methods and Scenarios -
© Nikolay Stoimenov
ETH Zurich, Switzerland
![Page 17: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/17.jpg)
5-2Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
Outline
• Modular Performance Analysis
• MPA Case Study
![Page 18: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/18.jpg)
5-3Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
Analysis and Design
Embedded System =
Computation + Resource Interaction
Analysis: Infer system properties from subsystem properties.
Design: Build a system from subsystems while meeting requirements.
![Page 19: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/19.jpg)
5-4Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
Challenges
Make Analysis and Synthesis Compositional
Stepwise Refinement: a. compose subsystemsb. refine subsystems
Adaptivity: a. changes in environmentb. changes of requirements
![Page 20: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/20.jpg)
5-5Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
Modular Performance Analysis
Service Model(Resources)
Load Model(Environment)
PerformanceModel
Processing Model(HW/SW)
Analysis
Analysis Results
Input traces
Formalspecification
System Model
Application Architecture
MappingScheduling
UML sequencediagrams Task graphs UML/SysML
diagrams
Formalspecification
Componentsimulation
Measure-ments
Data sheets
![Page 21: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/21.jpg)
5-6Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
Abstract Models for Performance Analysis
ProcessorTask
InputStream
ServiceModel
LoadModel
Concrete InstanceAbstract Representation
ProcessingModel
![Page 22: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/22.jpg)
5-7Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
Load Model (Environment)
t [ms]
eventsEvent Stream
maximum / minimumarriving demand in anyinterval of length 2.5 ms
2.5
Arrival Curve α & Delay ddemand
Δ [ms] 2.5
number of events in in t=[0 .. 2.5] ms
deadline = d
ServiceModel
LoadModel
ProcessingModel
αlαu
![Page 23: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/23.jpg)
5-8Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
Load Model - Examplesperiodic periodic w/ jitter
periodic w/ burst complex
ServiceModel
LoadModel
ProcessingModel
![Page 24: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/24.jpg)
5-9Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
Service Model (Resources)
t [ms]
availabilityResource Availability
maximum/minimumavailable service in anyinterval of length 2.5 ms
available service in t=[0 .. 2.5] ms
2.5
βu
βl
Service Curves [βl, βu]service
Δ [ms] 2.5
ServiceModel
LoadModel
ProcessingModel
![Page 25: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/25.jpg)
5-10Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
Service Model - Examplesfull resource bounded delay
TDMA resource periodic resource
ServiceModel
LoadModel
ProcessingModel
![Page 26: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/26.jpg)
5-11Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
Processing Model (HW/SW)
HW/SW Components
Abstract Components
ServiceModel
LoadModel
ProcessingModel
αβ
β’
α’
Processing semantics and functionality of hardware
or software tasks
RTC
![Page 27: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/27.jpg)
5-12Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
Processing Model – ExamplesServiceModel
LoadModel
ProcessingModel
• Component is triggered by incoming events.
• A fully preemptable task is instantiated at every event arrival to process the incoming event.
• Active tasks are processed in a greedy fashion in FIFO order.
• Processing is restricted by the availability of resources.
Behavioral DescriptionGreedy Processing Component
![Page 28: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/28.jpg)
5-13Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
Processing Model – ExamplesServiceModel
LoadModel
ProcessingModel
[αl, αu]
[βl, βu]
[βl’, βu’]
[αl’, αu’]
GPC
Greedy Processing Component
Real-Time Calculus
![Page 29: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/29.jpg)
5-14Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
Processing Model – ExamplesServiceModel
LoadModel
ProcessingModel
• Delays incoming events such that the output conforms to a given traffic specification.
• Guarantees that no events get delayed any longer than necessary.
• Works also with bursty traffic specifications.
Greedy Shaper Component
Behavioral Description
![Page 30: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/30.jpg)
5-15Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
Processing Model – ExamplesServiceModel
LoadModel
ProcessingModel
[αl, αu]
[σ]
[αl’, αu’]
GSC
Greedy Shaper ComponentReal-Time Calculus
![Page 31: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/31.jpg)
5-16Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
System CompositionCPU BUS DSP
GPC GPC
GPC GPC
GPC GSC
How to inter-connect service?
RM TDMA
Scheduling!
![Page 32: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/32.jpg)
5-17Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
FP/RM EDF RR
TDMAGPS
Scheduling and Arbitration
GPC
GPC
GPC
GPC
EDF RR
sum
share
GPC
GPC
TDMA
![Page 33: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/33.jpg)
5-18Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
RR
Mixed Hierarchical Scheduling
FP
TDMA
EDF
RR
EDFTDMA FP/RM+
FP
FP/RM EDF+
EDF
FP
RR EDF+
FP/RM RR+
FP/RM GPS+
GPS EDF+
. . .
…and many othercombinations:
![Page 34: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/34.jpg)
5-19Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
Hierarchical Scheduling with ServersStatic Polling Server
SPS
FP
FP
any
Dynamic Polling Server
DPS
any
EDF
![Page 35: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/35.jpg)
5-20Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
Complete System CompositionCPU BUS DSP
RM TDMA
GPC GPC
GPC GPC
GPC GSC
TDMA
![Page 36: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/36.jpg)
5-21Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
Analysis: Delay and Backlog
delay dmax
backlog bmax
βl
αu[αl, αu]
[βl, βu]
[βl’, βu’]
[αl’, αu’]
GPC
![Page 37: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/37.jpg)
5-22Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
Extending the Framework
• New HW behavior• New SW behavior• New scheduling scheme• ...
αβ
β’
α’RTC
• Find new relations:
This is the hard part…!
![Page 38: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/38.jpg)
5-23Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
MPA-RTC
Embedding with other Frameworks
{P, J, D}
{P, J, D}
Lossy Converter
Lossless Converter
MPA-RTC SystemCSimulation
Trace Generator
Trace Analyzer
![Page 39: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/39.jpg)
5-24Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
Outline
• Modular Performance Analysis
• MPA Case Study
![Page 40: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/40.jpg)
5-25Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
Case Study
ECU1
BUS
CC1
ECU2 CC2
ECU3CC3
S1
S2
S3
S4
S5
6 Real-Time Input Streams- with jitter- with bursts- deadline > period
3 ECU’s with own CC’s
13 Tasks & 7 Messages- with different WCED
2 Scheduling Policies- Earliest Deadline First (ECU’s)- Fixed Priority (ECU’s & CC’s)
Hierarchical Scheduling- Static & Dynamic Polling Servers
Bus with TDMA- 4 time slots with different lengths(#1,#3 for CC1, #2 for CC3, #4 for CC3)
Total Utilization:- ECU1 59 %- ECU2 87 %- ECU3 67 %- BUS 56 %
S6
![Page 41: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/41.jpg)
5-26Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
Specification Data
![Page 42: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/42.jpg)
5-27Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
The Distributed Embedded System...ECU1 BUS
(TDMA)
C1.1
C1.2
C2.1
C3.1
C4.1
C5.1
C3.2
T1.1
T1.3T2.1
T3.1
T3.3
PS
FPFP
CC1
ECU2
T4.1
T5.1
FPCC2
ECU3
T1.2
FP FP
CC3
T3.2
FP
EDF
T2.2
PS
T4.2
PS
T5.2
S1
S2
S3
S4
S5
S1
S3
T6.1S6
S6
![Page 43: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/43.jpg)
5-28Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
... and its MPA Model
S5
S4
S1
S2
S3
T1.1
T1.3
C4.1
C5.1
CPU
T2.1
T3.1
CPU
T4.1
T5.1
CPU
PS
T1.2
EDF
PS
T3.2
C1.2
C3.2
C2.1
C3.1
C1.1
T5.2
T4.2
T2.2
PS
ECU1
ECU2
ECU3BUS
CC1
CC2
CC3
T6.1S6
T3.3
TDMA
![Page 44: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/44.jpg)
5-29Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
Buffer & Delay Guarantees
S5
S4
S1
S2
S3
T1.1
T1.3
C4.1
C5.1
CPU
T2.1
T3.1
CPU
T4.1
T5.1
CPU
PS
T1.2
EDF
PS
T3.2
C1.2
C3.2
C2.1
C3.1
C1.1
T5.2
T4.2
T2.2
PS
ECU1
ECU2
ECU3BUS
CC1
CC2
CC3
T6.1S6
T3.3
2
62
2
57 1
313
5
5
1
4
5
6
5
5.30
7.12
3.69
d
b
1.80
0.50
0.70
TDMA
![Page 45: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/45.jpg)
5-30Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
Adding Greedy Shapers
S5
S4
S1
S2
S3
T1.1
T1.3
C4.1
C5.1
CPU
T2.1
T3.1
CPU
T4.1
T5.1
CPU
PS
T1.2
EDF
PS
T3.2
C1.2
C3.2
C2.1
C3.1
C1.1
T5.2
T4.2
T2.2
PS
ECU1
ECU2
ECU3BUS
CC1
CC2
CC3
T6.1S6
T3.3
2
62
2
57 1
313
5
5
1
4
5
6
5
5.30
7.12
3.69
1.80
0.50
0.70
2.704
: - 27%: - 20%
DelayBuffer
TDMA
![Page 46: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/46.jpg)
5-31Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
Input of Stream 3
S5
S4
S1
S2
S3
T1.1
T1.3
C4.1
C5.1
CPU
T2.1
T3.1
CPU
T4.1
T5.1
CPU
PS
T1.2
EDF
PS
T3.2
C1.2
C3.2
C2.1
C3.1
C1.1
T5.2
T4.2
T2.2
PS
ECU1
ECU2
ECU3BUS
CC1
CC2
CC3
T6.1S6
T3.3
TDMA
![Page 47: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/47.jpg)
5-32Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
Output of Stream 3
S5
S4
S1
S2
S3
T1.1
T1.3
C4.1
C5.1
CPU
T2.1
T3.1
CPU
T4.1
T5.1
CPU
PS
T1.2
EDF
PS
T3.2
C1.2
C3.2
C2.1
C3.1
C1.1
T5.2
T4.2
T2.2
PS
ECU1
ECU2
ECU3BUS
CC1
CC2
CC3
T6.1S6
T3.3
TDMA
![Page 48: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/48.jpg)
5-33Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
Output of Stream 3 with Greedy Shapers
S5
S4
S1
S2
S3
T1.1
T1.3
C4.1
C5.1
CPU
T2.1
T3.1
CPU
T4.1
T5.1
CPU
PS
T1.2
EDF
PS
T3.2
C1.2
C3.2
C2.1
C3.1
C1.1
T5.2
T4.2
T2.2
PS
ECU1
ECU2
ECU3BUS
CC1
CC2
CC3
T6.1S6
T3.3
TDMA
![Page 49: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/49.jpg)
5-34Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
System Analysis Time
• 10 seconds – Pentium Mobile 1.6 GHz– Matlab 7 SP2– RTC Toolbox
![Page 50: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/50.jpg)
5-35Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
RTC Toolbox: Version 1.0 Released
www.mpa.ethz.ch/rtctoolbox
![Page 51: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/51.jpg)
5-36Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
RTC Toolbox: Simulink Frontend
Currently under Development
![Page 52: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/52.jpg)
5-37Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
Acknowledgement
• Collaborators:– Ernesto Wandeler– Samarjit Chakraborty– Simon Künzli– Alexander Maxiaguine– Kai Huang
• Funding:– SNF, KTI, MEDEA+/SPEAC, ARTIST2 NoE
![Page 53: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/53.jpg)
Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
Thank you!
www.mpa.ethz.ch/rtctoolbox
Nikolay [email protected]
![Page 54: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/54.jpg)
IntroductionMin-Plus Calculus
Real-Time Calculus
Real-Time Calculus———————————–
A Formal Method for the Analysis ofReal-Time Systems
Wolfgang Haid
DTU, June 11, 2007
Wolfgang Haid Real-Time Calculus
![Page 55: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/55.jpg)
IntroductionMin-Plus Calculus
Real-Time Calculus
OverviewOutlineApplication and Foundation
Overview
Real-Time Calculus (RTC)
Modular Performance Analysis (MPA)
Min-Plus Calculus, Max-Plus Calculus
system view
mathematical view
Wolfgang Haid Real-Time Calculus
1/20
![Page 56: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/56.jpg)
IntroductionMin-Plus Calculus
Real-Time Calculus
OverviewOutlineApplication and Foundation
Outline
Min-Plus Calculus
Basic Abstractions
System Modeling
System Analysis
Wolfgang Haid Real-Time Calculus
2/20
![Page 57: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/57.jpg)
IntroductionMin-Plus Calculus
Real-Time Calculus
OverviewOutlineApplication and Foundation
Application and Foundation
Application of Real-Time Calculus
Real-Time Calculus can be regarded as a worst-case/best-casevariant of classical queuing theory. It is a formal method for theanalysis of real-time embedded systems.
Foundation of Real-Time Calculus
Min-Plus Algebra: F. Baccelli, G. Cohen, G. J. Olster, and J.P. Quadrat, Synchronization and Linearity — An Algebra forDiscrete Event Systems, Wiley, New York, 1992.
Network Calculus: J.-Y. Le Boudec and P. Thiran, NetworkCalculus — A Theory of Deterministic Queuing Systems forthe Internet, Lecture Notes in Computer Science, vol. 2050,Springer Verlag, 2001.
Formal methods for system level performance analysis
Wolfgang Haid Real-Time Calculus
3/20
![Page 58: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/58.jpg)
IntroductionMin-Plus Calculus
Real-Time Calculus
Min-Plus vs. Plus-Times CalculusMin-Plus/Max-Plus Operators
Comparison of Algebraic Structures (I)
Algebraic Structure
set of elements Sone or more operators defined on elements of this set
Algebraic Structures With Two Operators �, �
plus-times: {R, +, ×}min-plus: {R ∪+∞, inf, +}
inf - Reminder
inf(S) is the greatest lower bound of the elements in a set S.
inf{[3, 4]} = 3, inf{(3, 4]} = 3
min{[3, 4]} = 3, min{(3, 4]} not defined
Wolfgang Haid Real-Time Calculus
4/20
![Page 59: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/59.jpg)
IntroductionMin-Plus Calculus
Real-Time Calculus
Min-Plus vs. Plus-Times CalculusMin-Plus/Max-Plus Operators
Comparison of Algebraic Structures (II)
Common Properties: �
Closure of �: a � b ∈ SAssociativity of �: a � (b � c) = (a � b) � c
Commutativity of �: a � b = b � a
Existence of identity element for �: ∃ν : a � ν = a
Existence of negative element for �: ∃a−1 : a � a−1 = ν
Zero element for � absorbing for �: a � ε = ε
Distributivity of � w.r.t. �: a � (b � c) = a� b � b × c
Example: Distributive Law
plus-times: a× (b + c) = a× b + b × c
min-plus: a + inf{b, c} = inf{a + b, a + c}
Wolfgang Haid Real-Time Calculus
5/20
![Page 60: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/60.jpg)
IntroductionMin-Plus Calculus
Real-Time Calculus
Min-Plus vs. Plus-Times CalculusMin-Plus/Max-Plus Operators
Comparison of Algebraic Structures (III)
Common Properties: �Closure of �: a� b ∈ SAssociativity of �: : a� (b � c) = (a� b)� c
Commutativity of �: a� b = b � a
Existence of identity element for �: ∃ε : a� ε = a
Different Properties: �Existence of negative element for �: ∃ − a : a� (−a) = ε
Idempotency of �: a� a = a
Wolfgang Haid Real-Time Calculus
6/20
![Page 61: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/61.jpg)
IntroductionMin-Plus Calculus
Real-Time Calculus
Min-Plus vs. Plus-Times CalculusMin-Plus/Max-Plus Operators
Comparison of System Theories
Plus-Times System Theory h(t) = (f � g)(t) = Z t0 f(t� s) � g(s) dsg(t)f(t)signals
impulse response
convolution
time domain
Min-Plus System TheoryR(�) g(�) R0(�) � (R g)(�) = inf0����ff(�� �) + g(�)gstreams
service/shaping curve
min-plus convolution
time-interval domain
Wolfgang Haid Real-Time Calculus
7/20
![Page 62: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/62.jpg)
IntroductionMin-Plus Calculus
Real-Time Calculus
Min-Plus vs. Plus-Times CalculusMin-Plus/Max-Plus Operators
Min-Plus/Max-Plus Convolution and Deconvolution
Definitions
min-plus convolution:(f ⊗ g)(∆) = inf0≤λ≤∆
{f (∆− λ) + g(λ)}
min-plus deconvolution:(f � g)(∆) = supλ≥0
{f (∆ + λ)− g(λ)}
max-plus convolution:(f⊗g)(∆) = sup0≤λ≤∆
{f (∆− λ) + g(λ)}
max-plus deconvolution:(f�g)(∆) = infλ≥0
{f (∆ + λ)− g(λ)}
Duality between ⊗ and �f ≤ g ⊗ h ⇔ f � h ≤ g
Wolfgang Haid Real-Time Calculus
8/20
![Page 63: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/63.jpg)
IntroductionMin-Plus Calculus
Real-Time Calculus
System ModelSystem AnalysisSummary
From Streams to Cumulative Functions
Cumulative Functions
1 2 3 4 5 6 7 80
5
10
15
20
C(t)R(t)
1 2 3 4 5 6 7 80
1
1 2 3 4 5 6 7 80
1
time t
data streams: R(t) := number of events in [0, t)
resource streams: C (t) := available resources in [0, t)
Wolfgang Haid Real-Time Calculus
9/20
![Page 64: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/64.jpg)
IntroductionMin-Plus Calculus
Real-Time Calculus
System ModelSystem AnalysisSummary
Greedy Processing (I)
R(t) R0(t)C(t)C 0(t)
0 1 2 3 4 5 6 7 80
5
10
15
20
25
30
t
pro
cess
ing
time
dem
and
avai
labl
e pr
oces
sing
tim
e
C(t)C’(t)R(t)R’(t)B(t)C(t) − R(t)
Elementary Relations
C (t) = C ′(t) + R ′(t)
B(t) = R(t)− R ′(t)
Wolfgang Haid Real-Time Calculus
10/20
![Page 65: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/65.jpg)
IntroductionMin-Plus Calculus
Real-Time Calculus
System ModelSystem AnalysisSummary
Greedy Processing (II)
Input/Output Relation
0 1 2 3 4 5 6 7 80
5
10
15
20
25
30
t
pro
cess
ing
time
dem
and
avai
labl
e pr
oces
sing
tim
e
C(t)C’(t)R(t)R’(t)B(t)C(t) − R(t)
R ′(t) = C(t)− C ′(t) = C(t)− sup0≤ s ≤ t
{C(s)− R(s)} |inf{S} = sup−S
= C(t) + inf0≤ s ≤ t
{R(s)− C(s)}
= inf0≤ s ≤ t
{R(s) + C(t)− C(s)} |periodic resource
= inf0≤ s ≤ t
{R(s) + C(t − s)} != (R ⊗ C)(t)
Wolfgang Haid Real-Time Calculus
11/20
![Page 66: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/66.jpg)
IntroductionMin-Plus Calculus
Real-Time Calculus
System ModelSystem AnalysisSummary
From Cumulative Functions To Bounding Curves
R(t) R0(t)C(t)C 0(t) �(�) �0(�)�(�)
� 0(�)Wolfgang Haid Real-Time Calculus
12/20
![Page 67: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/67.jpg)
IntroductionMin-Plus Calculus
Real-Time Calculus
System ModelSystem AnalysisSummary
Arrival and Service Curves
Definition
0 1 2 3 4 5 6 7 80
5
10
15
20
25
time interval ∆
βu
βl
αu
αl
CR
αl(t − s) ≤ R[s, t) ≤ αu(t − s), ∀s < t,
βl(t − s) ≤ C [s, t) ≤ βu(t − s), ∀s < t,
αu(0) = αl(0) = βu(0) = βl(0) = 0.
Wolfgang Haid Real-Time Calculus
13/20
![Page 68: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/68.jpg)
IntroductionMin-Plus Calculus
Real-Time Calculus
System ModelSystem AnalysisSummary
Upper Arrival Curve (I)
Stream Constraint
R(t) ≤ (R ⊗ αu)(t)
= inf0≤s≤t
{R(s) + αu(t − s)}
≤ R(s) + αu(t − s), ∀ 0 ≤ s ≤ t
⇔R(t)− R(s) ≤ αu(t − s), ∀s ≤ t
Wolfgang Haid Real-Time Calculus
14/20
![Page 69: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/69.jpg)
IntroductionMin-Plus Calculus
Real-Time Calculus
System ModelSystem AnalysisSummary
Upper Arrival Curve (II)
Upper Arrival Curve
αu(∆) = (R � R)(∆)
= sups≥0
{R(∆ + s)− R(s)} |∆ = t − s
= sups≥0
{R(t − s + s)− R(s)}
≥ R(t)− R(s), ∀t ≥ s
(R � R): Minimum Upper Arrival Curve
Assume αu is an upper arrival curve for R.
from previous slide: R ≤ R ⊗ αu
from duality property: R � R ≤ αu
Wolfgang Haid Real-Time Calculus
15/20
![Page 70: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/70.jpg)
IntroductionMin-Plus Calculus
Real-Time Calculus
System ModelSystem AnalysisSummary
Greedy Processing Component
Input/Output Relations
h�l; �ui h�l; �ui h�0l; �0uih� 0l; � 0ui0 1 2 3 4 5 6 7 8
0
5
10
15
20
25
time interval ∆
β’u
β’l
α’u
α’l
C’R’
α′u = min{(αu ⊗ βu)� βl , βu}, α′l = min{(αl � βu)⊗ βl , βl}β′u = (βu − αl) � 0, β′l = (βl − αu) ⊗ 0
Wolfgang Haid Real-Time Calculus
16/20
![Page 71: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/71.jpg)
IntroductionMin-Plus Calculus
Real-Time Calculus
System ModelSystem AnalysisSummary
Backlog and Delay (I)
Definition
maximum backlog B
maximum delay D
�l �u�
B = sup0≤λ
{αu(λ)− βl(λ)
}D = sup
∆≤0
{inf
{τ ≤ 0 : αu(∆) ≤ βl(∆ + τ)
}}Wolfgang Haid Real-Time Calculus
17/20
![Page 72: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/72.jpg)
IntroductionMin-Plus Calculus
Real-Time Calculus
System ModelSystem AnalysisSummary
Backlog and Delay (II)
Backlog Bound
B(t) = R(t)− R ′(t) = R(t)− inf0≤u≤t
{R(u) + C (t)− C (u)}
= sup0≤u≤t
{(R(t)− R(u))− (C (t)− C (u))}
≤ sup0≤u≤t
{αu(t − u)− βl(t − u)}
≤ sup0≤λ
{αu(λ)− βl(λ)}
= (αu � βl)(0)
Wolfgang Haid Real-Time Calculus
18/20
![Page 73: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/73.jpg)
IntroductionMin-Plus Calculus
Real-Time Calculus
System ModelSystem AnalysisSummary
Backlog and Delay (III)
D
B
B
D
Wolfgang Haid Real-Time Calculus
19/20
![Page 74: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/74.jpg)
IntroductionMin-Plus Calculus
Real-Time Calculus
System ModelSystem AnalysisSummary
Summary: Fixed-Priority Scheduling
Key Elements of Real-Time Calculus
min-plus calculus as well-definedmathematical basis
abstraction of streams: arrival/servicecurves
abstraction of processing: greedyprocessing
delay and backlog bounds
modularity
�1(�) �01(�)�(�)
� 0(�)�2(�) �02(�)�3(�) �03(�)
Wolfgang Haid Real-Time Calculus
20/20
![Page 75: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/75.jpg)
IntroductionModel and Analysis
Conclusion
Complex Task Activation Schemesin
System Level Performance Analysis
Wolfgang Haid
DTU, June 11, 2007
Wolfgang Haid Complex Task Activation Schemes
![Page 76: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/76.jpg)
IntroductionModel and Analysis
Conclusion
ContextOutlineFormal Methods for System Level Performance Analysis
Context
Keywords
Distributed embedded real-time systems
System level performance analysis
Formal methods for system level performance analysis
Wolfgang Haid Complex Task Activation Schemes
1/13
![Page 77: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/77.jpg)
IntroductionModel and Analysis
Conclusion
ContextOutlineFormal Methods for System Level Performance Analysis
A Glimpse on Formal Methods
Advantages
Hard bounds
Complete coverage of corner cases
Faster than simulation
Drawbacks
Limited modeling capabilities
Bounds potentially not tight
Inaccuracy of results
Thesis
To obtain improved accuracy, we can sacrifice some computationaleffort.
Wolfgang Haid Complex Task Activation Schemes
2/13
![Page 78: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/78.jpg)
IntroductionModel and Analysis
Conclusion
ContextOutlineFormal Methods for System Level Performance Analysis
Outline
Introduction to complex task activation schemes
Task model and analysis
MPEG-2 case study
Conclusion
Wolfgang Haid Complex Task Activation Schemes
3/13
![Page 79: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/79.jpg)
IntroductionModel and Analysis
Conclusion
ContextOutlineFormal Methods for System Level Performance Analysis
Formal Methods
Frameworks
Modular Performance Analysis / Real-Time Calculus(MPA/RTC): Samarjit Chakraborty, Simon Kunzli, and LotharThiele, A General Framework for Analyzing System Propertiesin Platform-Based Embedded System Design, Proc. 6thDesign, Automation and Test in Europe (DATE) (Munich,Germany), March 2003, pp. 190–195.
Symbolic Timing Analysis for Systems (SymTA/S): RafikHenia, Arne Hamann, Marek Jersak, Razvan Racu, KaiRichter, and Rolf Ernst, System Level PerformanceAnalysis — The SymTA/S Approach, IEE ProceedingsComputers and Digital Techniques 152 (2005), no. 2,148–166.
Wolfgang Haid Complex Task Activation Schemes
4/13
![Page 80: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/80.jpg)
IntroductionModel and Analysis
Conclusion
ContextOutlineFormal Methods for System Level Performance Analysis
Formal Methods
Example: MPEG-2 on Multiprocessor Platform
BUS
B C
D R2R1FG
RISC DSP
A
E
H
stre
am
task function
video
A VLD, IQ, ISB data transferC IDCT, MCD data transferE assemble video-frames
audio
F DEC, IMDCT, SYNG data transferH assemble audio-frames
But . . .
Tasks have usually more than one input.
The activation of tasks can depend on complex activationschemes.
Wolfgang Haid Complex Task Activation Schemes
5/13
![Page 81: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/81.jpg)
IntroductionModel and Analysis
Conclusion
ContextOutlineFormal Methods for System Level Performance Analysis
Formal Methods
Example: MPEG-2 on Multiprocessor Platform
BUS
B C
D R2R1FG
RISC DSP
A
E
H
stre
am
task function
video
A VLD, IQ, ISB data transferC IDCT, MCD data transferE assemble video-frames
audio
F DEC, IMDCT, SYNG data transferH assemble audio-frames
But . . .
Tasks have usually more than one input.
The activation of tasks can depend on complex activationschemes.
Wolfgang Haid Complex Task Activation Schemes
5/13
![Page 82: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/82.jpg)
IntroductionModel and Analysis
Conclusion
Task Model, Terms, and NotationAnalysis PrincipleNon-Preemptive Fixed Priority Scheduling
Task Model
1: if test(reconfig) then . execute subtask A2: execute code that reconfigures the task;3: else if test(dataA) or test(dataB) then . execute subtask B4: process first event arrived at dataA or dataB;5: write to outputA;6: else if test(dataC) and test(dataD) then . execute subtask C7: process first event in dataC and in dataD;8: write to outputB;9: end if
reconfig
dataA
dataB
dataC
dataD
outputA
outputB
A
B
C
Wolfgang Haid Complex Task Activation Schemes
6/13
![Page 83: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/83.jpg)
IntroductionModel and Analysis
Conclusion
Task Model, Terms, and NotationAnalysis PrincipleNon-Preemptive Fixed Priority Scheduling
Greedy Processing Component
h�l; �uih�l; �ui
GPCh�0l; �0uih� 0l; � 0ui
0 5 10 15 200
10
20
30
time interval ∆
#(ev
ents
) d
uri
ng
∆
Input Arrival Curves
0 5 10 15 200
10
20
30
40
time interval ∆
#(ev
ents
) d
uri
ng
∆
Input Service Curves
0 5 10 15 200
10
20
30
time interval ∆
#(ev
ents
) d
uri
ng
∆
Output Arrival Curves
0 5 10 15 200
5
10
15
20
25
time interval ∆
#(ev
ents
) d
uri
ng
∆
Output Service Curves
αu
αlβu
βl
α’u
α’lβ’u
β’l
arrival curve α : αl(t − s) ≤ R(t)− R(s) ≤ αu(t − s),
service curve β : βl(t − s) ≤ C (t)− C (s) ≤ βu(t − s), ∀t − s ≥ 0
Wolfgang Haid Complex Task Activation Schemes
7/13
![Page 84: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/84.jpg)
IntroductionModel and Analysis
Conclusion
Task Model, Terms, and NotationAnalysis PrincipleNon-Preemptive Fixed Priority Scheduling
Analysis Principle
A
B
C
A
B
C
non-preemptivefixed priority
scheduler
A
B
C
non-preemptivefixed priority
scheduler
OR
AND
Wolfgang Haid Complex Task Activation Schemes
8/13
![Page 85: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/85.jpg)
IntroductionModel and Analysis
Conclusion
Task Model, Terms, and NotationAnalysis PrincipleNon-Preemptive Fixed Priority Scheduling
Non-Preemptive Fixed Priority Scheduling
Related Work: Priority Queuing in Network Queueing Theory
Jean-Yves Le Boudec and Patrick Thiran, NetworkCalculus — A Theory of Deterministic Queuing Systems forthe Internet, Lecture Notes in Computer Science, vol. 2050,Springer Verlag, 2001.
Jens Schmitt, On Average and Worst Case Behavior inNon-Preemptive Priority Queueing, Proc. 2003 Intl Symp. onPerformance Evaluation of Computer and TelecommunicationSystems, 2003, pp. 197–204.
Wolfgang Haid Complex Task Activation Schemes
9/13
![Page 86: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/86.jpg)
IntroductionModel and Analysis
Conclusion
Task Model, Terms, and NotationAnalysis PrincipleNon-Preemptive Fixed Priority Scheduling
Non-Preemptive Fixed Priority Scheduling
Relations for Preemptive Fixed Priority Scheduling
βui (∆) = inf
λ≥0
βu(∆ + λ)−N∑
j=i+1
αlj(∆ + λ)
βl
i (∆) = sup0≤λ≤∆
βl(∆− λ)−N∑
j=i+1
αuj (∆− λ)
i . . . task priority N . . . number of tasks
Wolfgang Haid Complex Task Activation Schemes
10/13
![Page 87: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/87.jpg)
IntroductionModel and Analysis
Conclusion
Task Model, Terms, and NotationAnalysis PrincipleNon-Preemptive Fixed Priority Scheduling
Non-Preemptive Fixed Priority Scheduling
Relations for Non-Preemptive Fixed Priority Scheduling
βui (∆) = min
{βu(∆), inf
λ≥0
{βu(∆ + λ)−
N∑j=i+1
αlj(∆ + λ)
}+Cmax
i
}
β li (∆) = max
{0, sup
0≤λ≤∆
{β l(∆− λ)−
N∑j=i+1
αuj (∆− λ)
}− max
1≤j<i
{Cmax
j
}}
i . . . task priority N . . . number of tasks
Cmaxi . . .maximum number of resource units to process one event
Wolfgang Haid Complex Task Activation Schemes
11/13
![Page 88: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/88.jpg)
IntroductionModel and Analysis
Conclusion
MPEG-2 Case StudyContributions
MPEG-2 Case Study
BUS
B C
D R2R1
FG
RISC DSP
R3time ref
A
E
H
I
Wolfgang Haid Complex Task Activation Schemes
12/13
![Page 89: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/89.jpg)
IntroductionModel and Analysis
Conclusion
MPEG-2 Case StudyContributions
Contributions
Consideration of complex task activation schemes based onAND/OR semantics
Modeling of tasks with complex activation schemes in MPAusing abstract AND/OR components and non-preemptivefixed priority scheduling
Derivation and proof of input-output relations of abstractAND/OR component
Derivation and proof of relations to model non-preemptivefixed priority scheduling
Application of the results in an MPEG-2 case study
Wolfgang Haid Complex Task Activation Schemes
13/13
![Page 90: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/90.jpg)
5-1Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
Real-Time Interfaces
© Nikolay Stoimenov
ETH Zurich, Switzerland
![Page 91: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/91.jpg)
5-2Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
Outline
• Real-Time Interfaces / Interface-Based Design
• IBD Case Study
![Page 92: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/92.jpg)
5-3Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
Real-Time Interfaces &Interface-Based Design
![Page 93: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/93.jpg)
5-4Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
Component-Based Design
FP
FP
1. Design
2. Analysis– Given: all components, their
interconnections structure and all inputs from environment
– Question: do the components work together properly?
Schedulable?
Constraints:
![Page 94: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/94.jpg)
5-5Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
Interface-Based Design
FP
FPConstraints:
1. Design and Composition– Given: some components,
their interconnection structure and some inputs from environment
– Questions: Is there the chance that the components work together properly? What are the assumptions towards the environment? How can I change the environment such that the components still work together?
?
?
![Page 95: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/95.jpg)
5-6Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
Interface-Based Design
Component Description:
What Does a Component Do?
Component Interface:
How Can a Component Be Used?
vs.
![Page 96: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/96.jpg)
5-7Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
Real-Time Interfaces
Interface-Based Design(Assume/Guarantee Interfaces)
Henzinger, de Alfaro, et al.
Real-Time Calculus
Thiele, et al.
Real-Time Interfaces
![Page 97: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/97.jpg)
5-8Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
From a Simple Component ...
resource supply
remaining resources
resource demand
![Page 98: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/98.jpg)
5-9Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
... to its A/G Interface
resource supply
remaining resources
resource demand
![Page 99: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/99.jpg)
5-10Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
... to its A/G Interface
resource supply
remaining resources
resource demand
Variables & Types
![Page 100: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/100.jpg)
5-11Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
... to its A/G Interface
Input Assumptions, Predicates & Values
![Page 101: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/101.jpg)
5-12Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
... to its A/G Interface
Output Guarantees, Predicates & Values
![Page 102: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/102.jpg)
5-13Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
... to its A/G Interface
Data from Other Component Interfaces
![Page 103: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/103.jpg)
5-14Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
... to its A/G Interface
Internal Interface Relations
![Page 104: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/104.jpg)
5-15Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
Compatibility & Composition
![Page 105: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/105.jpg)
5-16Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
The Weakest Environment
0
0∞∞
0∞
![Page 106: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/106.jpg)
5-17Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
A Simple Example
0
0∞∞
0∞
0
0∞∞
0∞
![Page 107: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/107.jpg)
5-18Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
A Simple Example
0
0∞∞
∞
0
0∞
0∞5
∞
![Page 108: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/108.jpg)
5-19Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
A Simple Example
0
∞∞
∞
∞
0∞5
5
507
![Page 109: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/109.jpg)
5-20Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
A Simple Example
0
05
75
577
2
2
![Page 110: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/110.jpg)
5-21Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
A Simple Example
0
05
75
5
4
∞
7
2
2
7
![Page 111: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/111.jpg)
5-22Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
A Simple Example
0
05
75
5
1
∞
7
2
2
7
![Page 112: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/112.jpg)
5-23Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
A Simple Example
05
7
5
2
1
6
1
66
![Page 113: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/113.jpg)
5-24Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
Foundations of Real-Time Interfaces
Interface-Based Design(Assume/Guarantee Interfaces)
Henzinger, de Alfaro, et al.
Real-Time Calculus
Thiele, et al.
Real-Time Interfaces
![Page 114: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/114.jpg)
5-25Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
Three Steps to Real-Time Interfaces
• Step 1: Abstract Components
• Step 2: Interface Variables and Predicates
• Step 3: Internal Interface Relations
![Page 115: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/115.jpg)
5-26Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
Step 1: Abstract Component
β
β’
α , d
![Page 116: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/116.jpg)
5-27Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
Step 2: Interface Variable & Predicates
![Page 117: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/117.jpg)
5-28Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
Step 2: Interface Variable & Predicates
![Page 118: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/118.jpg)
5-29Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
Step 3: Internal Interface Relations
Fixed Priority Scheduling
![Page 119: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/119.jpg)
5-30Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
Applications
• Interface-Based Design of RT Systems– Find minimum processor speed for complex systems with mixed
hierarchical scheduling.– Find optimal TDMA slot and cycle length allocations.– Specify maximum allowable input stream rates.– …
• Answering of design questions, e.g. resource dimensioning• On-Line Load Adaptation• On-Line Service Adaptation• On-Line Admission Tests• …
![Page 120: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/120.jpg)
5-31Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
A Simple System with FP Scheduling...
L2
L1
CPU
T2
T1Load 1: p = 3, d = 6
Load 2: p = 6, d = 7
CPU: Fully Available
T1: WCET = 1
T2: WCET = 1
![Page 121: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/121.jpg)
5-32Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
... and its Real-Time Interface Model
CPU
T2L2
T1L1
L2
L1
CPU
T2
T1
![Page 122: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/122.jpg)
5-33Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
Schedulability Analysis
CPU
T2L2
T1L1
dA=1dG=6
dA=2dG=7
![Page 123: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/123.jpg)
5-34Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
Applications
• Interface-Based Design of RT Systems– Find minimum processor speed for complex systems with mixed
hierarchical scheduling.– Find optimal TDMA slot and cycle length allocations.– Specify maximum allowable input stream rates.– …
• Answering of design questions, e.g. resource dimensioning• On-Line Load Adaption• On-Line Service Adaption• On-Line Admission Tests• …
![Page 124: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/124.jpg)
5-35Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
T1
Resource Dimensioning
CPU
T2L2
L1
1. Full CPU with min frequency
2. CPU with bounded delay
3. CPU with TDMA, and others
Different options:
![Page 125: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/125.jpg)
5-36Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
Applications
• Interface-Based Design of RT Systems– Find minimum processor speed for complex systems with mixed
hierarchical scheduling.– Find optimal TDMA slot and cycle length allocations.– Specify maximum allowable input stream rates.– …
• Answering of design questions, e.g. resource dimensioning• On-Line Load Adaption• On-Line Service Adaption• On-Line Admission Tests• …
![Page 126: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/126.jpg)
5-37Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
dA=3
On-Line Load Adaption (Burstiness)
CPU
T2L2
T1L1
dA=2dG=7
dA=1dG=6
1. Check2. Admit3. Update
![Page 127: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/127.jpg)
5-38Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
dG=6
On-Line Load Adaption (Delay)
CPU
T2L2
T1L1
dA=3dG=7
dA=1
1. Check2. Admit3. Update
dG=2?
![Page 128: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/128.jpg)
5-39Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
On-Line Service Adaption
CPU
T2L2
T1L1
dG=7
dA=1.25dG=2
1. Check2. Admit3. Update
dA=3
dA=1
![Page 129: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/129.jpg)
5-40Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
Outline
• Real-Time Interfaces / Interface-Based Design
• IBD Case Study
![Page 130: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/130.jpg)
5-41Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
A System with Complex Scheduling...
Full Processor
FP
T3T2
T4T1
EDF
T6T5
RM
T10T9T8T7
EDFSPS
DPS
10 Tasks- with jitter- with bursts- deadline = period- deadline < period- deadline > period
3 Scheduling Policies- Rate Monotonic- Earliest Deadline First- Fixed Priority
Hierarchical SchedulingStatic & Dynamic Polling Servers
Total Utilization: 98.5%
![Page 131: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/131.jpg)
5-42Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
... and its Real-Time Interface Model
Service
FP
EDF
FP
T3
T2
T4
T1
EDFT6
T5
SPS
RMT7-T10
DPS
![Page 132: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/132.jpg)
5-43Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
Schedulability Analysis
Service
FP
EDF
FP
T3
T2
T4
T1
EDFT6
T5
SPS
RMT7-T10
DPS
Implicit by Successful Composition!
![Page 133: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/133.jpg)
5-44Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
Schedulability Analysis
Service
FP
EDF
FP
T3
T2
T4
T1
EDFT6
T5
SPS
RMT7-T10
DPS
![Page 134: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/134.jpg)
5-45Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
System Adaption I: Burstiness of T2
Service
FP
EDF
FP
T3
T2
T4
T1
EDFT6
T5
SPS
RMT7-T10
DPS
![Page 135: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/135.jpg)
5-46Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
System Adaption II: Deadline of T2
Service
FP
EDF
FP
T3
T2
T4
T1
EDFT6
T5
SPS
RMT7-T10
DPS
![Page 136: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/136.jpg)
5-47Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
System Analysis Time
• < 1 second – Pentium Mobile 1.6 GHz– Matlab 7 SP2– RTC Toolbox
![Page 137: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/137.jpg)
Swiss FederalInstitute of Technology
Computer Engineeringand Networks Laboratory
Thank you!
www.mpa.ethz.ch/rtctoolbox
Nikolay [email protected]
![Page 138: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/138.jpg)
Modular Performance Analysis withReal-Time Calculus
Simon Perathoner
6. Comparison with other analysis approaches
ARTIST2 PhD Course on Automated Formal Methods for Embedded SystemsDTU - Lyngby, Denmark - June 11, 2007
![Page 139: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/139.jpg)
Computer Engineering and Networks Laboratory (TIK) 2
Motivation
Abstractions
Benchmarks
Conclusions
Outline
![Page 140: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/140.jpg)
Computer Engineering and Networks Laboratory (TIK) 3
System level performance analysis
T4
T3
T1T5
T2
CPU1
CPU2
CPU3
AND
I1
I2
O2
O1
Max.Bufferspace?
Max.CPU load?
Max.end-to-end
delay?
![Page 141: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/141.jpg)
Computer Engineering and Networks Laboratory (TIK) 4
Formal analysis methods
T4
T3
T1T5
T2
CPU1
CPU2
CPU3
AND
I1
I2
O2
O1 Abstraction
Analysis
Performance values
Distributed system Abstraction 1
Analysis method 1
Abstraction 2
GPC GPC
GPC GPC
GPC GSC
TDMA
Analysis method 2
Abstraction 3
Analysis method 3
![Page 142: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/142.jpg)
Computer Engineering and Networks Laboratory (TIK) 5
Motivating questions
What is the influence of the different models onthe analysis accuracy ?
Evaluation and comparison of abstractions is needed !
Does abstraction matter ?
Which abstraction is best suited for a given system ?
![Page 143: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/143.jpg)
Computer Engineering and Networks Laboratory (TIK) 6
How can we compare different abstractions ?
scope
usability
simpleexact
compositional
easy to use
tool supportstepwise refinement
efficientimplementation
learning curve
scalability
accuracy analysis time
holistic
performance metricsmodeling effort
modular
correctness
Method 1
Method 2
T4
T3
T1T5
T2
CPU1
CPU2
CPU3
AND
I1
I2
O2
O1
![Page 144: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/144.jpg)
Computer Engineering and Networks Laboratory (TIK) 7
What makes a direct comparison difficult? Many aspects can not be quantified
A
B
C
D
Models cover different scenarios:
![Page 145: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/145.jpg)
Computer Engineering and Networks Laboratory (TIK) 8
Intention
Compare models and methods that analyze the timing properties of distributed systems:
SymTA/S [Richter et al.]
MPA-RTC [Thiele et al.]
MAST [González Harbour et al.]
Timed automata based analysis [Yi et al.]
…
![Page 146: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/146.jpg)
Computer Engineering and Networks Laboratory (TIK) 9
Leiden Workshop on Distributed Embedded Systems: http://www.tik.ee.ethz.ch/~leiden05/
Define a set of benchmark examples that cover common area
Define benchmark examples that show the power of each method
SymTA/S
MAST
TA
MPA
Approach
![Page 147: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/147.jpg)
Computer Engineering and Networks Laboratory (TIK) 10
Expected (long term) results
Understand the modeling power of different methods
Understand the relation between models and analysis accuracy
Improve methods by combining ideas and abstractions
![Page 148: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/148.jpg)
Computer Engineering and Networks Laboratory (TIK) 11
Contributions
We define a set of benchmark systems aimed at the evaluation of performance analysis techniques
We apply different analysis methods to the benchmark systems and compare the results obtained in terms of accuracy and analysis times
We point out several analysis difficulties and investigate the causes for deviating results
![Page 149: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/149.jpg)
Computer Engineering and Networks Laboratory (TIK) 12
Motivation
Abstractions
Benchmarks
Conclusions
Outline
![Page 150: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/150.jpg)
Computer Engineering and Networks Laboratory (TIK) 13
Abstraction 1 - Holistic schedulingBasic concept: extend concepts of classical scheduling
theory to distributed systems
Holistic scheduling
FP CPUs + TDMA bus
[Tindell et al.]1994
FP + datadependencies
[Yen et al.]1995
FP + control dependencies
[Pop et al.]2000
CAN[Tindell et al.]
1995
Mixed TT/ETsystems
[Pop et al.]2002
EDF offset based [González et al.]
2003
. . .
![Page 151: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/151.jpg)
Computer Engineering and Networks Laboratory (TIK) 14
Holistic scheduling – MAST tool
MAST - The Modeling and Analysis Suite for Real-Time Applications [González Harbour et al.]
SystemTXT
SystemTXT
ResultsTXT
ResultsTXT
![Page 152: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/152.jpg)
Computer Engineering and Networks Laboratory (TIK) 15
Abstraction 2 – The SymTA/S approach
Basic concept: Application of classical scheduling techniques at resource level and propagation of results to next component
Problem: The local analysis techniques require the input event streams to fit given standard event models
Solution: Use appropriate interfaces: EMIFs & EAFs
EMIF / EAF
![Page 153: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/153.jpg)
Computer Engineering and Networks Laboratory (TIK) 16
SymTA/S – Tool
![Page 154: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/154.jpg)
Computer Engineering and Networks Laboratory (TIK) 17
Abstraction 3 – MPA-RTC
t
events
events
Δ
αlαu
t
availability
βu
βlservice
Δ
Load model Service model
Arrival curves Service curves
![Page 155: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/155.jpg)
Computer Engineering and Networks Laboratory (TIK) 18
Abstraction 3 – MPA-RTC
[αl, αu]
[βl, βu]
[βl’, βu’]
[αl’, αu’]
GPC
![Page 156: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/156.jpg)
Computer Engineering and Networks Laboratory (TIK) 19
Abstraction 4 - TA based performance analysis
Verification of performance properties by model checking (UPPAAL)
fixed priorityscheduling
periodic streamExact performance values
![Page 157: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/157.jpg)
Computer Engineering and Networks Laboratory (TIK) 20
Motivation
Abstractions
Benchmarks
Conclusions
Outline
![Page 158: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/158.jpg)
Computer Engineering and Networks Laboratory (TIK) 21
Benchmarks
Pay burst only once
Complex activation pattern
Variable feedback
Cyclic dependencies
AND/OR task activation
Intra-context information
Workload correlation
Data dependencies
![Page 159: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/159.jpg)
Computer Engineering and Networks Laboratory (TIK) 22
Benchmark 1 – Complex activation pattern
WCRT T3 ?
period
C = 35
C = 2
C = 12
C = 4
(FP)
(FP)
periodicP = 60
periodicP = 5
periodic
![Page 160: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/160.jpg)
Computer Engineering and Networks Laboratory (TIK) 23
Benchmark 1 – Analysis results
![Page 161: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/161.jpg)
Computer Engineering and Networks Laboratory (TIK) 24
Benchmark 1 – Result interpretation PI3 = 65 ms
![Page 162: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/162.jpg)
Computer Engineering and Networks Laboratory (TIK) 25
Benchmark 1 – Worst case Delay I2-O2
![Page 163: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/163.jpg)
Computer Engineering and Networks Laboratory (TIK) 26
Benchmark 2 – Variable feedback
T1
CPU1
T2
T3
T4
CPU2
I1
I2
O1
O2
Maxdelay ?
Exec. time C
C = 2
C = 2
C = 1(FP)
(FP)periodicP = 100
periodicP = 5
![Page 164: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/164.jpg)
Computer Engineering and Networks Laboratory (TIK) 27
Benchmark 2 – Analysis results
T1
CPU1
T2
T3
T4
CPU2
I1
I2
O1
O2
![Page 165: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/165.jpg)
Computer Engineering and Networks Laboratory (TIK) 28
Benchmark 3 – Cyclic dependencies
I1 T1
CPU1
T2
CPU2
O1 T3
Max delay ?
jitter
C = 1
C = 4
C = 4
(FP)
periodicwith burstP = 10
![Page 166: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/166.jpg)
Computer Engineering and Networks Laboratory (TIK) 29
Benchmark 3 – Analysis resultsScenario 1: priority T1 = high
priority T3 = lowI1 T1
CPU1
T2
CPU2
O1 T3
![Page 167: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/167.jpg)
Computer Engineering and Networks Laboratory (TIK) 30
Benchmark 3 – Analysis resultsScenario 2: priority T1 = low
priority T3 = high I1 T1
CPU1
T2
CPU2
O1 T3
![Page 168: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/168.jpg)
Computer Engineering and Networks Laboratory (TIK) 31
Analysis times [s]
< 0.5< 0.5< 0.5
0.50.50.5
0.50.50.5
< 0.5< 0.5< 0.5
1.01.01.0
minmedmax
Simulation
< 0.5< 0.5< 0.5
< 0.5< 0.5
5.5
< 0.51.0
52.0
< 0.5< 0.5< 0.5
18.034.560.5
minmedmax
Timed aut.
< 0.5< 0.5< 0.5
< 0.5< 0.5< 0.5
< 0.5< 0.5< 0.5
< 0.5< 0.5< 0.5
---
minmedmax
MAST
0.060.090.31
0.030.340.80
0.030.060.09
0.030.050.23
0.050.091.50
minmedmax
SymTA/S
0.030.050.20
0.040.150.30
0.010.010.04
0.030.040.08
0.601.06
19.72
minmedmax
MPA-RTC
B4B3 (sc.2)B3 (sc.1)B2B1
![Page 169: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/169.jpg)
Computer Engineering and Networks Laboratory (TIK) 32
Motivation
Abstractions
Benchmarks
Conclusions
Outline
![Page 170: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/170.jpg)
Computer Engineering and Networks Laboratory (TIK) 33
ConclusionsThe analysis accuracy and the analysis time depend highlyon the specific system characteristics
None of the analysis methods performed best in all benchmarks
The analysis results of the different approaches are remarkable different even for apparently basic systems
The choice of an appropriate analysis abstraction matters
The problem to provide accurate performance predictions for general systems is still far from solved
![Page 171: Modular Performance Analysis with Real-Time Calculus · Computer Engineering and Networks Laboratory (TIK) 2 Presentation overview Introduction to System Level Performance Analysis](https://reader034.fdocuments.net/reader034/viewer/2022051810/6017eabe76778b0c02296733/html5/thumbnails/171.jpg)
Computer Engineering and Networks Laboratory (TIK) 34
DiscussionApproximation of complex event streams with standard event models can lead to poor performance predictions atlocal level
Holistic approaches better in the presence of correlationsamong task activations (e.g. data dependencies)
Cyclic dependencies represent a serious pitfall for the accuracy of compositional analysis methods
Holistic methods less appropriate for timing properties referred to the actual release time of an event within a large jitter interval