Moderate Highspeed Nyquist Adc
Transcript of Moderate Highspeed Nyquist Adc
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Modetarate / High Speed NyquistADC
Submitted By :
Anamika Singh
Megha Sharma
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A/D Converter (ADC) Introduction
A/D Fundamentals Sampling
Quantization
Factors Affecting A/D Converter Performance
Static Performance Dynamic Performance
ADC Architectures SAR ADCs
Pipelined ADCs
Flash Type ADC
Sigma-Delta ADCs
High Speed ADC Application Considerations
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3. Nyquist-Rate ADCs
How can Nyquist-rate ADCs be grouped?
What is a dual slopeADC?
What is a successive approximationADC?
What is an algorithmicADC? What is a flashADC?
What is a pipelinedADC?
What are the pros and consof the Nyquist-rateADCs?
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Nyquist-Rate ADCs
Sampling frequencyfsampis in the same range as frequencyfinof input signal
Low-to-medium speedand high accuracyADCs
Integrating
Medium speedand medium accuracyADCs Successive Approximation
Algorithmic
High speedand low-to-medium accuracy ADCs
Flash Two-Level Flash
Pipelined
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Successive Approximation ADC
Recursive One-Bit Sub-Ranging Architecture
ANALOG
INPUT
START
CONVERT
COMPARATOR EOC OR
DRDYSHA +
-
DAC
SAR*
*SUCCESSIVE
APPROXIM ATION
REGISTER
DIGITAL
OUTPUT
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Successive Approximation ADC
+FS
-FS
Analog
Input
Period 1
MSB
Bit 4
Bit 3
Bit 2
Period 3Period 2Period 1Period 4Period 3Period 2
AnalogInput
Internal signals for a 4-bit successive approximation ADC
test at 1
test at 1
test at 1
test at 1
test at 1
test at 1
test at 10
00
0
0
0
0
00
0
0
01
0
1
0
11
1
00
Conversion complete (1011),
start on next conversion
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How a Successive Approximation A/D ConverterWorks
Rising/Falling Edge of Convert Start Pulse Resets Logic
Falling/Rising Edge Begins Conversion Process
Bit Comparisons Made on Each Clock Edge
Conversion Time Equals Number of Comparisons
(Resolution) Times Clock Period
The Accuracy of Conversion Depends on the DAC
Linearity and Comparator Noise
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EXAMPLE : ANALOG INPUT = 6.428V, REFERENCE = 10.000V
MSB
5.000V2SB
2.500V
3SB
1.250V
LSB
0.625V
VIN> 5.000V VIN> 6.875VVIN> 6.250VVIN> 7.500V
YES
1
NO
0
YES
1
NO
0
How Successive Approximation Works
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Advantages to SAR A/D converters
Low Power (12-bit/1.5 MSPS ADC: 1.7 mW)
Higher resolutions (16-bit/1 MSPS)
Small Die Area and Low Cost
No pipeline delay
Tradeoffs to SAR A/D converters
Lower sampling rates
Typical Applications
Instrumentation
Industrial control
Data acquisition
Successive Approximation ADC
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Successive Approx.: pros and cons
Low Area / Low Power
High effort for DAC
Early wrong decision leads to false result
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Algorithmic ADC
Vin S&H
S&HX2
S1
Vref/4
-Vref/4
S2
D0 D1 DN-1
Shift register
Same idea as successive approximation ADC
Instead of modifying Vrefdoubling of errorvoltage(Vrefstays constant)
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Algorithmic ADC contStart
Sample V= Vin, i= 1
Di= 1
V > 0
Di= 0
V= 2(V - Vref/4) V= 2(V + Vref/4)
i= i+1
i > N
Stop
yes
no
yes
Vin
S&H
X2
S1
Vref/4-Vref/4
S2
D0 D1 DN-1
Shift register
no
S&H
D.A.. Johns, K. Martin,Analog Integrated Circuit design, John Wiley & Sons, 1997
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Algorithmic ADC: pros and cons
Less analog circuitry than Succ. Approx. ADC
Low Power / Low Area
High effort for multiply-by-two gain amp
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Flash ADC
Vinconnected with 2N
comparators in parallel
Comparators connectedto resistor string
Thermometer code
R/2-resistors on bottomand top for 0.5 LSBoffset
VinVref
Over range
D0
D1
DN-1
(2N-1) to N
encoder
R/2
R
R/2
R
R
R
R
R
R
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Some Flash ADC design issues
Input capacitive loadingon Vin Switching noise if comparators switch at the same
time
Resistors-string bowingby input currents ofbipolar comparators (if used)
Bubble errorsin the thermometer code based oncomparators metastability
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Flash ADC: pros and cons
Very fast
High effort for the 2Ncomparators
High Area / High Power
Recommended for 6-8 Bit and less
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Two-Level Flash ADC
Conversion in two steps:
1. Determination of MSB-Bits and reconverting ofdigital signal by DAC
2. Subtraction from Vinand determination of LSB-Bits
F.e. 8-Bit-ADC: Flash: 28=256 comparators, Two-level:224= 32 comparators
N/2-Bit
Flash ADC x2N
MSB (D0 DN/2-1) LSB (DN/2 DN-1)
N/2-Bit
Flash ADC
gain amp
VinN/2-Bit
DAC
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Two-Level Flash ADC: pros and cons
Same throughput as Flash ADC
Less area, less power, less capacity loading thanFlash ADC
Easy error-correction after first stage
Larger latency delay than Flash ADC
Design ofN/2-Bit-DAC
Currently most popular approach for high-speed/medium accuracy ADCs
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Q & A
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Thank You