Recent Advances in Multistep Nyquist ADC’s · Pipeline ADC PE Chart (< 2010) ISSCC & VLSI data...

Erik Jonsson School of Engineering & Computer Science

Recent Advances in Multistep Nyquist ADC’s

Yun Chiu

Erik Jonsson Distinguished ProfessorUniversity of Texas at Dallas

MWSCAS, 8/5/12 - 2 - © Y. Chiu

Performance vs. Energy Efficiency

MWSCAS, 8/5/12 - 3 - © Y. Chiu

···

Walden Figure-of-Merit (FoM) for ADC

ENOB

P JouleFoM2 BW 2 Conversion - Step

• P = power consumption

• ENOB = effective number of bits

• BW = min(fs/2, ERBW)

• ERBW = effective resolution BW

in sNout

ref

V nTD n = 2

V

Ref. [1]

FoM “measures” energy efficiency

MWSCAS, 8/5/12 - 4 - © Y. Chiu

How to compare ADC performance?

• Higher performance with lower cost is the obvious criterion for comparison

– ADC performance: speed (sample rate) or bandwidth, resolution

– ADC cost: power consumption, die size

Q: how to define performance quantitatively?

MWSCAS, 8/5/12 - 5 - © Y. Chiu

Definition of PERFORMANCE

• Bandwidth (or speed) performance– BW = min(fs/2, ERBW)

• Resolution (or precision) performance– Effective number of bits (ENOB), or equivalently

effective number of steps (ENOS) = 2ENOB

• Separately, it is easy. But how to combine the two in one merit? Just take the product?

MWSCAS, 8/5/12 - 6 - © Y. Chiu


• 2×BW 2×Power, 2×Area (same ENOS) Power, area scale linearly with bandwidth

• 2×ENOS 4×Power, 4×Area (same BW) Power, area scale quadratically with precision

(for thermal noise or matching limited design)

2

Power, Area BW,Power, Area ENOS

MWSCAS, 8/5/12 - 7 - © Y. Chiu


22

ENOB

Performance = 2 BW ENOSHz Step

= 2 BW 4

2Power & Area BW, ENOS

Definition:

2 BW = fsample ENOB1010log 4 = SNR

This definition avoids penalizing high-SNR works as Walden FoM does

MWSCAS, 8/5/12 - 8 - © Y. Chiu

Definition of ENERGY EFFICIENCY

2

2

ENOB

PEnergy Efficiency = J2 BW ENOSP Step

2 BW 4

Definition:

ENOBENOB

Performance Energy EfficiencyP= 2 BW 4 =

2 BW 4Power

Note:

2Power & Area BW, ENOS

MWSCAS, 8/5/12 - 9 - © Y. Chiu

Performance–Efficiency (PE) Chart

Energy Efficiency = Power/(2·BW·4ENOB)

Perf

orm

ance

= 2·

BW

·4EN

OB

PowerPe

rform

ance

Effic

ienc

y

Constant performance

Con

stan

t effi

cien

cyBe

st d

esig

n

Constant-power hyperbola

(log scale)

(log

scal

e)

X·Y = Power

MWSCAS, 8/5/12 - 10 - © Y. Chiu

Pipeline ADC PE Chart (< 2005)

Efficiency [J/Step2]

Perf

orm

ance

[Hz·

Ste

p2 ]ISSCC & VLSI data

100mW

1W

10mW

1mW100μW10μW1μW

MWSCAS, 8/5/12 - 11 - © Y. Chiu

Pipeline ADC PE Chart (< 2010)ISSCC & VLSI data

100mW

1W

10mW

1mW100μW10μW1μW


Perf

orm

ance

[Hz·

Ste

p2 ]

MWSCAS, 8/5/12 - 12 - © Y. Chiu

Pipeline ADC PE Chart(< 2012)ISSCC & VLSI data

100mW

1W

10mW

1mW100μW10μW1μW


Perf

orm

ance

[Hz·

Ste

p2 ]

MWSCAS, 8/5/12 - 13 - © Y. Chiu

SAR ADC PE Chart (< 2005)ISSCC & VLSI data

100mW

1W

10mW

1mW100μW10μW1μW


Perf

orm

ance

[Hz·

Ste

p2 ]

MWSCAS, 8/5/12 - 14 - © Y. Chiu


100mW

1W

10mW

1mW100μW10μW1μW


Perf

orm

ance

[Hz·

Ste

p2 ]

MWSCAS, 8/5/12 - 15 - © Y. Chiu


100mW

1W

10mW

1mW100μW10μW1μW


Perf

orm

ance

[Hz·

Ste

p2 ]

MWSCAS, 8/5/12 - 16 - © Y. Chiu

Nyquist ADC PE Chart (mid 90s – 2011)ISSCC & VLSI data

100mW

1W

10mW

1mW100μW10μW1μW


Perf

orm

ance

[Hz·

Ste

p2 ]

MWSCAS, 8/5/12 - 17 - © Y. Chiu


Industry

ADC’s

UniversityADC’s

100mW

1W

10mW

1mW100μW10μW1μW


Perf

orm

ance

[Hz·

Ste

p2 ]

MWSCAS, 8/5/12 - 18 - © Y. Chiu


Ours(ISSCC10)

MIT(ISSCC10)

Michigan

(ISSCC10)

NCKU(ISSCC10)

Twente(ISSCC08)

ADI(ISSCC10)

ADI(ISSCC11)

ADI(ISSCC09)

TI(ISSCC10)

NCKU(VLSI10)

100mW

1W

10mW

1mW100μW10μW1μW


Perf

orm

ance

[Hz·

Ste

p2 ]

MWSCAS, 8/5/12 - 19 - © Y. Chiu

Digital-Domain Calibration

MWSCAS, 8/5/12 - 20 - © Y. Chiu

DigitalComputation

The Basic Idea

ADC

UnknownSystem

SystemInversion

1o

2i

V 1- 1βA

-CCV

• match C1 and C2• make βA very large

Digital soln:• any constant C1 and C2• any constant A is fine

Analog soln:Switched-capacitor amplifier

Calibration = efficient digital post-processing to undo certain analog errors

MWSCAS, 8/5/12 - 21 - © Y. Chiu

Two Essential Components

1. A digital-domain technique (e.g. equation) to recover accurate analog information from raw digital output– Treat analog precision or linearity only– Neglect consequence on SNR

2. An algorithm to identify the error parameters– Foreground vs. Background approaches

1

2CL

1CC

A 1-βA

- = #

MWSCAS, 8/5/12 - 22 - © Y. Chiu

Example – Multistage Pipeline ADC

• Input coarsely quantized (< 5 bits)• Residue produced and passed on

2.5b MDAC:

V2

V1

0-VR

VR

Encoder

Φ1e

A

Φ2

VR6

VR1

6 CMP’s

Φ1 C4

Φ1 C3

Φ2

C2

C1

Φ1

Φ1

Φ2

Φ2

d1

MWSCAS, 8/5/12 - 23 - © Y. Chiu

Multiplying DAC Error Mechanism

2.5b MDAC

dj -3 -2 -1 0 1 2 3

dj,1 -1 -1 -1 -1 -1 0 1

dj,2 -1 -1 -1 0 1 1 1

dj,3 -1 0 1 1 1 1 1

DAC bit-encoding scheme

dj = dj,1 + dj,2 + dj,3

• Seven decision levels ENOB ≈ log27 = 2.807• Residue transfer function Vj (Vj+1) can be derived w/ charge conservation• Capacitor mismatch and amplifier gain error are dominant error sources

Vj+1

Vj

0-VR

VR

Encoder

Φ1e

A

Φ2

VR6

VR1

6 CMP’s

...

Φ1 C4

Φ1 C3

Φ2

C2

C1

Φ1

Φ1

Φ2

Φ2

dj

MWSCAS, 8/5/12 - 24 - © Y. Chiu

Residue Transfer Function (2.5b Pipeline)

Only half of the internal dynamic range is used under ideal condition

overflowrange

underflowrange

normalrange

MWSCAS, 8/5/12 - 25 - © Y. Chiu

What happens with comparator offset?

overflowrange

underflowrange

normalrange

MWSCAS, 8/5/12 - 26 - © Y. Chiu

Internal Redundancy

Comparator and amplifier offsets are tolerated by internal redundancy

overflowrange

underflowrange

normalrange

MWSCAS, 8/5/12 - 27 - © Y. Chiu

Redundancy in Subranging ADC

Do

Ref

eren

ce L

adde

r Coarse ADC

Enc

oder

Fine ADC

Vi

MSB’s

LSB’s

SHA

SHA

MUX

4 bits

5 bits

8 bits

Vi

Fine Encoder + Error Correction

extraCMP’s

extraCMP’s

To Coarse CMP’sVR

1 VR2

overflowrange

underflowrange

normalrange

MWSCAS, 8/5/12 - 28 - © Y. Chiu

Equation for MDAC RTF Correction

j,1 j,2 j,3j r j+

31 21

4CC C C + C A+ += +C C CV V Vd dC

d

ideal residue function

j,1 j,2 j,3

3j j+1

r

1 2

r

4CC C C + C A+ += +C C Cd dV V

V V Cd

j,1 j,2 j,j 3 j

j,

,1 j,2 j,3j j+1

j,k j+k jk

1

β + β + β= + α

=

d d dD D

β D+ αd

Digital representation (EC EQ):

j jj,1 j,2 j,

+1 j+1

r r3 j

r

V V VV V

1 1 1 1+ += + = +V

d d4 4

d d4 4

Analog residue function:

Normalized residue function:

error parameters: { αj, βj,k }

MWSCAS, 8/5/12 - 29 - © Y. Chiu

Bit-Weight (Radix) Correction

...

...

1 in

j j j+1 j+1 j+2 j+2 j+1 j j-1

j j+1 j+j j+1 j+22

D =D

=...+ d β + d β + d β +... α α α

=...+d +d +d +γ γ γ weighted sum of ALL bits!(bit weight or radix error)

segmental offset

For 1b or 1.5b MDAC:

...

...

1 in

j j+1 j+2j j+1 j+j j+1 j+2

j j j+1 j+1 j+2 j+2

2

j j+1 j+2j j+1 j+2

D =Dd d d

=...+ + + +2 2 2d + d + d +

=.

1+Δ 1+Δ 1+Δ

d Δ d Δ d Δ..+ + + +

2 2 2

Alternatively,

MWSCAS, 8/5/12 - 30 - © Y. Chiu

Bit-Weight (Radix) Correction

Vi-VR VR

Do

Vi-VR VR

Do

radix error:needs multiplication

segmental offset:addition only

d1=-1 d1=1d1=0 d1=-1 d1=1d1=0 d1=-1 d1=1d1=0

1.5b MDACresidue nonlinearity

MWSCAS, 8/5/12 - 31 - © Y. Chiu

Nonlinear MDAC Equation

43j,

j+1j r1 j,2 j,3 j

21

1+

VV V

C + C ACC C+ += +C C C Vd dC

d

431 2j,1 j,2 j,3

j+1j j+1

r r

C + C ACd dC C+ += +CVV V

V Vd

C C C

j,1 j,2 j,3j,1 j,2 j,3j j+1

jm

j,k,k j+1 j,mk m

d β + β + β= + f

β + α

d dD D

d D

Digital representation:

Analog representation:

Normalized analog representation:

error parameters: { αj,m, βj,k }

MWSCAS, 8/5/12 - 32 - © Y. Chiu

Let’s push this approach…

-70 dBFS

Give me a place to stand on, and I will move the Earth…

Corrected w/ 9th-order power series

LDrawn

0.15μm

VDD

1.2V

Correcting nonlinearity:

Archimedes, 200 BC

MWSCAS, 8/5/12 - 33 - © Y. Chiu

A few words on nonlinear correction

• Memoryless polynomial computation is efficient– A few coefficients fits/predicts full-range nonlinearity

(requiring digital multipliers and adders mostly)– Caveat: coefficients depend on signal statistics!– Caveat: coefficients depend on PVT variations!

• Piecewise-linear or lookup table can be useful– Memory, digital power, and cost– Complexity and convergence time (esp. tracking speed in

background mode)

Solution needs to be practical after all…

MWSCAS, 8/5/12 - 34 - © Y. Chiu

Error-Parameter Identification

MWSCAS, 8/5/12 - 35 - © Y. Chiu

Foreground Calibration

• Foreground calibration– Test signal injected at input with normal conversion stopped– Often executed at system power-up– Incapable of tracking ambient variations

• Pseudo-background calibration– Skip-and-fill technique (Ref. [2])– Queue-base technique (Ref. [3])

MWSCAS, 8/5/12 - 36 - © Y. Chiu

Background Calibration (Recent Trend)

• Parameter extraction w/ PRBS (1b) injection– Sub-DAC injection (DAC dithering)– Sub-ADC injection (comparator dithering)– Input injection (Independent Component Analysis)

• Parameter extraction w/ two-ADC equalization– Reference-ADC equalization (training sequence)– Split-ADC equalization (blind)– Offset double conversion (ODC) (blind, single ADC)

Model parameter extraction is what the game is all about…

MWSCAS, 8/5/12 - 37 - © Y. Chiu

Background Calibration (Recent Trend)

ADC2 x2(n) y2(n)

e(n)Vin

Lewis (03), Chiu (04), McNeill (05), et al.

ADC Adaptive Digital PP

x(n)

y(n)e(n)

t(n)

Vin

Temes (98, 00), Lewis (98), Galton (00), et al.

Two-ADCequalization

PRBS injection(Dither)

x1(n)

Adaptive Digital PP

ADC1Adaptive Digital PP

y1(n)

MWSCAS, 8/5/12 - 38 - © Y. Chiu

Digital Background Calibration Techniques

Method Parameter Test signal Injection point Reference†

DNC + GEC { βj,k, αj,m } multi PRBS sub-DAC [7–12]

Split capacitor { Δj } 1 PRBS sub-DAC [13, 14]

Sig.-dep. dither { γj } 1 PRBS sub-DAC [15]

GEC + SA { γj } 2 PRBS sub-ADC [16, 17]

Statistics { αj,m } 1 PRBS sub-ADC [18, 19]

Fast GEC { γj } 1 PRBS sub-ADC [20]

ICA { γj }, { αj,m } 1 PRBS input [21–23]

Ref. ADC { βj,k, αj,m } n/a n/a [24–27]

Virtual ADC { βj,k, αj,m } offset sub-DAC [28, 29]

Split ADC { αj,m } n/a n/a [30, 31]

ODC { γj } offset input [32, 33]

† References are furnished at the end of the slides

MWSCAS, 8/5/12 - 39 - © Y. Chiu

PRBS Injection Techniques

MWSCAS, 8/5/12 - 40 - © Y. Chiu

Comparison of PRBS Injection Techniques

• Sub-DAC injection– needs to be removed in digital output– higher sub-DAC resolution (injection and DAC matching req’d)– can work with quiet input

• Sub-ADC injection– considered as dynamic comparator offset, no removal needed– higher sub-ADC resolution (injection and ADC matching not req’d)– works only with busy input

• Direct input injection– needs to be removed in digital output– No impact on sub-ADC or sub-DAC resolution– works only with busy input

MWSCAS, 8/5/12 - 41 - © Y. Chiu

2D

Sub-DAC Injection – residue gain correction

Converge@

2D T = 0

• In steady state, analog gain (G1) and digital gain (G1-1) cancel exactly

• k ≤ ¼ to avoid overflow in residue output, DAC adds 2 bits minimum• Injection bit scaling factor (2-k) must match to the sub-DAC unit elements

MWSCAS, 8/5/12 - 42 - © Y. Chiu

2D

Sub-DAC Injection – residue gain correction


• k ≤ ¼ to avoid overflow in residue output, DAC adds 2 bits minimum• Injection bit scaling factor (2-k) must match to the sub-DAC unit elements

Converge@

2D T = 0

-VR/2

0

d1=1 d1=2

-VR

VR/2

VR

¼ bit½ bit

...

...

typ. k = 2

residuepath

MWSCAS, 8/5/12 - 43 - © Y. Chiu

Sub-DAC Injection – signal-dependent dither

Vj (VR) T = +1 T = -1

-1 -⅜ 0 0

-⅜ -⅛ 0 VR

-⅛ ⅛ -½ VR ½ VR

⅛ ⅜ -VR 0

⅜ 1 0 0

PRBS Injection Table

• PRBS only injected when input falls within the shaded region• Extra comparator thresholds needed to instrument the SDD

MWSCAS, 8/5/12 - 44 - © Y. Chiu

Sub-ADC Injection – comparator dither


• k ≤ ¼ to avoid overflow in residue output• No need to match injection bit scaling factor (2-k) to the sub-ADC thresholds

Converge@

1D T = 0

MWSCAS, 8/5/12 - 45 - © Y. Chiu

Sub-ADC Injection – comparator dither


• k ≤ ¼ to avoid overflow in residue output• No need to match injection bit scaling factor (2-k) to the sub-ADC thresholds

Converge@

residuepath

1D T = 0

MWSCAS, 8/5/12 - 46 - © Y. Chiu

Internal Redundancy Revisited

Ref. [34]

• Input falling in shaded region randomly sees one of two RTF’s dithering• Decision threshold needs not to be accurate or matched to each other• Digitization outcome is independent of PRBS when ADC is ideal !!

MWSCAS, 8/5/12 - 47 - © Y. Chiu

Inter-stage gain error identification

1 1 ideal 1 ideal 1If V { region 1 } and T = +1, D =D ; if T = -1, D =D -δ

1 2 31 1 11 1 1Segmental offset : D = + d + d +...d +d δ4 8 16

1 1 ideal 1 1 idealIf V { region 2} and T = +1, D =D +δ ; if T = -1, D =D

MWSCAS, 8/5/12 - 48 - © Y. Chiu

Inter-stage gain error identification

1 1 1δ =δ +μ D Tn+1 n n n

1 1 1ideal idealideal 1 ideal 1

1 11 1

1 1

1 1D T = Pr V { region 1 } Pr V { region 2 }D - -DD -δ D +δ2 21 1= δ Pr δ PrV { region 1 } V { region 2 }2 21= δ Pr V { region 1 or 2 }2

1 1D T 0δ removed

Calculating correlation:

LMS learning:

• Correlation reveals information about segmental offset• Exact size of shaded region is not important (only affects Pr(.))• Key observation: if ADC is ideal, D1 must be uncorrelated to T

MWSCAS, 8/5/12 - 49 - © Y. Chiu

Direct Input Injection

• Algorithm works reliant on the independence b/t input and T, a stronger statement than simply being “uncorrelated”

• Multiple parameter extraction is possible with Independent Component Analysis (ICA)

MWSCAS, 8/5/12 - 50 - © Y. Chiu

Equalization Techniques

MWSCAS, 8/5/12 - 51 - © Y. Chiu

Comparison of Equalization Techniques

• Reference-ADC equalization– Slow-Fast two-ADC architecture to accomplish accuracy and throughput

simultaneously using adaptive equalization– Two (different) ADC’s needed, subject to skew error without SHA

• Split-ADC equalization– Two almost identical ADC’s employed for blind equalization– Two ADC’s needed, subject to skew error without SHA

• Offset double conversion (ODC)– Self-equalization by digitizing every sample twice with opposite DC offsets

injected to the input– Single ADC with modified timing in background mode– Conversion throughput halved in background mode

MWSCAS, 8/5/12 - 52 - © Y. Chiu

Reference-ADC Equalization

• Concept inspired by adaptive equalization in digital comm. receivers

• Divide-and-conquer approach to achieve analog speed and accuracy

MWSCAS, 8/5/12 - 53 - © Y. Chiu

EQZ of Time-Interleaved ADC Array

All paths are aligned to the unique ref. ADC after equalization

Ф

Φ1

tnov

Фr

Φ2

Φ10

1 21002

1

2

11002

1002

ADC1

T/H

Ref.ADC

ADC10

ADF1

ADF10

D1

DLL

Ф1Vin

1X

1X

D10

Dr

Ф10

Ф1

Ф10

Фr

Ф

Ф′

DigitalCal.

MWSCAS, 8/5/12 - 54 - © Y. Chiu

600MS/s TI-ADC Array Achieving >60dB SFDR

Performance Comparison (@ publication time)

CMOS ADC’s Process Speed

[MS/s]SFDR[dB]

FoM[fJ/step]

ISSCC’06 0.13µm 600 43 220

ISSCC’08 0.13µm 1250 48 480

VLSI’08 65nm 800 58 280

This workISSCC’09 0.13µm 600 65 210

Die photo Ref. [35]

MWSCAS, 8/5/12 - 55 - © Y. Chiu

ADC Array EQZ – Measured Linearity (#3)

50 100 150 200-2

-1

0

1

2DNL (1.24/-0.93 LSBs)

LSB

50 100 150 200-2

-1

0

1

2INL (1.72/-1.81 LSBs)

LSB

50 100 150 200-2

-1

0

1

2DNL (0.54/-0.52 LSBs)

LSB

code50 100 150 200

-2

-1

0

1

2INL (0.33/-0.33 LSBs)

LSB

code

Before Cal.

After Cal.

Before Cal.

After Cal.

(fs = 600MS/s, fin = 1.8MHz, Ain = 0.9FS, 100k samples)

MWSCAS, 8/5/12 - 56 - © Y. Chiu

ADC Array EQZ – Measured Linearity (array)

50 100 150 200-2

-1

0

1

2DNL (1.24/-0.93 LSBs)

LSB

50 100 150 200-2

-1

0

1

2INL (1.72/-1.81 LSBs)

LSB

50 100 150 200-2

-1

0

1

2DNL (0.54/-0.52 LSBs)

LSB

code50 100 150 200

-2

-1

0

1

2INL (0.33/-0.33 LSBs)

LSB

code

Before Cal.

After Cal.

Before Cal.

After Cal.


50 100 150 200-2

-1

0

1

2DNL (1.30/-0.94 LSBs)

LSB

50 100 150 200-2

-1

0

1

2INL (1.67/-1.71 LSBs)

LSB

50 100 150 200-2

-1

0

1

2DNL (0.30/-0.30 LSBs)

LSB

code

50 100 150 200-2

-1

0

1

2INL (0.23/-0.19 LSBs)

LSB

code

Before Cal.

After Cal.After Cal.

Before Cal.

MWSCAS, 8/5/12 - 57 - © Y. Chiu

0 100 200 300-90

-80

-70

-60

-50

-40

-30

-20

-10

0

frequency [MHz]

Before Calibration

0 100 200 300-90

-80

-70

-60

-50

-40

-30

-20

-10

0

frequency [MHz]

After Calibration

0 100 200 300-90

-80

-70

-60

-50

-40

-30

-20

-10

0

frequency [kHz]

Reference ADC

SNDR=31.2dBSFDR=33.0dB



3fs/10

2fs/10 4fs/10

fs/10

HD3

HD3 HD3

SNDR=31.2 dBSFDR=33.0 dB



ADC Array EQZ – Measured Spectrum


MWSCAS, 8/5/12 - 58 - © Y. Chiu

101 102 103 104 10532

34

36

38

40

42

44

46

48

reference sample

SN

DR

[dB

]ADC Array EQZ – Convergence Speed

200k Samples

MWSCAS, 8/5/12 - 59 - © Y. Chiu

Split-ADC Equalization

Vi

Vo

ADCA

Vi

Vo

ADCB

• Blind equalization w/o reference possible by offsetting the RTF’s

• Fast convergence due to zero-forcing equalization (vs. de-correlation)

MWSCAS, 8/5/12 - 60 - © Y. Chiu

Split-ADC Equalization – Zero Forcing

Radix correction Zero-forcing EQZError observation

εε = dA−dB

MWSCAS, 8/5/12 - 61 - © Y. Chiu

Self-Equalization – Offset Double Conversion

• Every sample is converted twice w/ opposite offsets injected (ODC)

• Self-equalization, hardware efficient, no skew issue, half throughput

• Simultaneous multiple parameter learning, zero-forcing, very fast

DigitalCal.

MWSCAS, 8/5/12 - 62 - © Y. Chiu

• Single ZX comparator insensitive to offset and nonlinearity

• All-switching analog architecture scaling friendly, low power and area

• Op-amp free rail-to-rail swing, inherently linear operation

The Return of SAR ADC

VFS = 2VR

MWSCAS, 8/5/12 - 63 - © Y. Chiu

• Single ZX comparator insensitive to offset and nonlinearity

• All-switching analog architecture scaling friendly, low power and area

• Op-amp free rail-to-rail swing, inherently linear operation

Binary Search

VFS = 2VR

1 0 0 00 1 1 1…

If VX > 0, Dj = 1;o.w., Dj = 0.

MWSCAS, 8/5/12 - 64 - © Y. Chiu

> <=

Binary(no redundancy)

Super-binary(no redundancy)

Sub-binary(redundancy)

SAR Conversion Redundancy

MWSCAS, 8/5/12 - 65 - © Y. Chiu

inout

FS

N-1os

jj=0 FS

N-

=

j

j

j

1

j 0j

Vd =V

V2D -1= + +QNV

2D -1

CC

w=

Charge balance:

Sub-Binary Bit-Weight Correction

N-tap linear equalizer

j jD = 0,1 , w = bit weights

0 0.2 0.4 0.6 0.8 10

2000

4000

6000

8000

10000

12000

14000

16000

VIN/VFS

D0 0.2 0.4 0.6 0.8 1

0

500

1000

1500

2000

2500

3000

3500

4000

VIN/VFS

d

Raw(14 bits)

Cal’d(12 bits)

MWSCAS, 8/5/12 - 71 - © Y. Chiu


• Shift-invariant ONLY when the transfer curve is completely linear !!

• Non-constant difference b/t D+ and D− reveals bit weight information

MWSCAS, 8/5/12 - 72 - © Y. Chiu

Offset Double Conversion for SAR

• Offset double conversion (ODC) enables self-equalization• ALL bit weights { wj } are learned simultaneously !!

DigitalCal.

MWSCAS, 8/5/12 - 75 - © Y. Chiu

Measured Performance @ 12b, 22.5MS/s

0 5 10-120

-100

-80

-60

-40

-20

0

dB

Freq [MHz]0 5 10

-120

-100

-80

-60

-40

-20

0

dB

Freq [MHz]

After Cal.Before Cal.

SNDR = 60.2 dBSFDR = 66.4 dBTHD = -61.7 dB

SNDR = 70.7 dBSFDR = 94.6 dBTHD = -89.1 dB

MWSCAS, 8/5/12 - 76 - © Y. Chiu

Convergence Speed

0 1 2 3 4 5 6x 10

4

-5

05

10

e [L

SB]

Number for samples

0 1 2 3 4 5 6x 10

4

-5

05

10e

[LSB

]

Number for samples

0 1 2 3 4 5 6x 10

4

-5

05

10

e [L

SB]

Number for samples

22000 samples @ 22.5 MS/s ≈ 1 ms

MWSCAS, 8/5/12 - 77 - © Y. Chiu

Comparison with 12b ADC’s

2000 2002 2004 2006 2008 201010

-2

10-1

100

101

Year

FoM

(pJ/

conv

. ste

p)

2000 2002 2004 2006 2008 201010

-2

10-1

100

101

102

Year

Act

ive

area

(mm

2 )

0.06 mm2

46 fJ/step @ 22.5 MS/s31 fJ/step @ 45 MS/s

Total Power: 3.0mW

@ time of publication

MWSCAS, 8/5/12 - 79 - © Y. Chiu

Speed Concerns for Background Calibration

• Component aging, ambient variations, e.g., voltage, temperature,require different tracking speed for background calibration algorithms

• Amplifier nonlinearity is very sensitive to variations and signal statistics needs special attention

• Reported speed performance varies. In general, equalization outperforms PRBS injection by large margin

MWSCAS, 8/5/12 - 81 - © Y. Chiu

1.E+03

1.E+04

1.E+05

1.E+06

1.E+07

1.E+08

1.E+09

1.E+10

1.E+11

11 12 13 14 15 16 17

SFDR Bits

# of

Sam

ples

Convergence Time

Convergence/tracking speed determines the sensitivity, testability, and ultimately practicality of a treatment…

# Ref. Sample SFDR

1 [9] 134M 90dB

2 [18] 40M 80dB

3 [13] 268M 93dB

4 [12] 225M 96dB

5 [15] 400M 98dB

6 [30] 10k ?

7 [32] 22k 95dB

~4N

1 453

2

6(?)7

104 : 1

MWSCAS, 8/5/12 - 82 - © Y. Chiu

Why Dithering is Slow?

Clean observation through correlation process requires ~22N samples

…1110010110

1D T exhibits large fluctuation !!

MWSCAS, 8/5/12 - 85 - © Y. Chiu

Bibliography

1. R. H. Walden, “Analog-to-digital converter survey and analysis,” IEEE JSAC, issue 4, 1999.2. S.-U. Kwak, B.-S. Song, and K. Bacrania, “A 15-b 5-Msamples/s low spurious CMOS ADC,” JSSC, Dec.

1997.3. E. Erdogan et al., “A 12-b digital-background-calibrated algorithmic ADC with -90-dB THD,” JSSC, Dec.

1999.4. T. Sun, A. Wiesbauer, and G. C. Temes, “Adaptive compensation of analog circuit imperfections for

cascaded delta-sigma ADCs,” in ISCAS 1998.5. P. Kiss et al., “Adaptive digital correction of analog errors in MASH ADC’s—Part II: Correction using test-

signal injection,” TCAS II, July 2000.6. D. Fu, K. C. Dyer, S. H. Lewis, and P. J. Hurst, “A digital back-ground calibration technique for time-

interleaved analog-to-digital converters,” JSSC, Dec. 1998.7. I. Galton, “Digital cancellation of D/A converter noise in pipelined A/D converters,” TCAS II, Mar. 2000.8. P. C. Yu et al., “A 14b 40MS/s pipelined ADC with DFCA,” in ISSCC 2001.9. E. J. Siragusa and I. Galton, “A digitally enhanced 1.8V 15b 40MS/s CMOS pipelined ADC,” in ISSCC

2004.10. A. Panigada and I. Galton, “Digital background correction of harmonic distortion in pipelined ADCs,” TCAS

I, Sept. 2006.11. A. Panigada and I. Galton, “A 130mW 100MS/s pipelined ADC with 69dB SNDR enabled by digital

harmonic distortion correction,” in ISSCC 2009.12. K. Nair and R. Harjani, “A 96dB SFDR 50MS/s digitally enhanced CMOS pipeline A/D converter,” in ISSCC

2004.13. H.-C. Liu, Z.-M. Lee, and J.-T. Wu, “A 15b 20MS/s CMOS pipelined ADC with digital background

calibration,” in ISSCC 2004.

MWSCAS, 8/5/12 - 86 - © Y. Chiu

Bibliography

14. J.-L. Fan, C.-Y. Wang, and J.-T. Wu, “A robust and fast digital background calibration technique for pipelined ADCs,” TCAS I, June 2007.

15. Y.-S. Shu and B.-S. Song, “A 15b linear, 20MS/s, 1.5b/stage pipelined ADC digitally calibrated with signal-dependent dithering,” in VLSI 2006.

16. J. Li and U.-K. Moon, “Background calibration techniques for multistage pipelined ADC’s with digital redundancy,” TCAS II, Sept. 2003.

17. J. Li et al., “0.9V 12mW 2MSPS algorithmic ADC with 81dB SFDR,” in VLSI 2004.18. B. Murmann et al., “A 12b 75MS/s pipelined ADC using open- loop residue amplification,” in ISSCC 2003.19. J. Keane et al., “Background interstage gain calibration technique for pipelined ADCs,” TCAS I, Jan. 2005.20. R. Massolini, G. Cesura, and R. Castello, “A fully digital fast convergence algorithm for nonlinearity

correction in multistage ADC,” TCAS II, May 2006.21. Y. Chiu, “A framework of digital-domain background calibration of multi-step ADC using pseudorandom test

signal injection,” in SampTA 2011.22. S.-C. Lee, B. Elies, and Y. Chiu, “An 85dB SFDR 67dB SNDR 8OSR 240MS/s SD ADC with nonlinear

memory error calibration,” in VLSI 2012.23. W. Liu, P. Huang, and Y. Chiu, “A 12-bit 50-MS/s 3.3-mW SAR ADC with background digital calibration,” in

CICC 2012.24. X. Wang et al., “A 12-bit 20-MS/s pipelined ADC with nested digital background calibration,” in CICC 2003.25. Y. Chiu et al., “Least mean square adaptive digital background calibration of pipelined analog-to-digital

converters,” TCAS I, Jan. 2004.26. C. Tsang et al., “Background ADC calibration in digital domain,” in CICC 2008.27. Y. Chiu, “Equalization techniques for nonlinear analog circuits,” IEEE Comm. Mag., Apr. 2011.

MWSCAS, 8/5/12 - 87 - © Y. Chiu

Bibliography

28. B. Peng et al., “A virtual-ADC digital background calibration technique for multistage A/D conversion,”TCAS II, Nov. 2010.

29. B. Peng et al., “A 48-mW, 12-bit, 150-MS/s pipelined ADC with digital calibration in 65nm CMOS,” in CICC 2011.

30. J. McNeill et al., “Split ADC architecture for deterministic digital background calibration of a 16b 1MS/s ADC,” in ISSCC 2005.

31. J. McNeill et al., “Split-ADC digital background correction of open-loop residue amplifier nonlinearity errors in a 14b pipeline ADC,” in ISCAS 2007.

32. W. Liu, P. Huang, and Y. Chiu, “A 12bit 22.5/45MS/s 3.0mW 0.059mm2 CMOS SAR ADC achieving over 90dB SFDR,” in ISSCC 2010.

33. B. Peng et al., “An offset double conversion technique for digital calibration of pipelined ADCs,” TCAS II, Dec. 2010.

34. H. S. Fetterman et al., “CMOS pipelined ADC employing dither to improve linearity,” in CICC 1999.35. W. Liu et al., “A 600MS/s 30mW 0.13μm CMOS ADC array achieving over 60dB SFDR with adaptive digital

equalization,” in ISSCC 2009.

Recent Advances in Multistep Nyquist ADC’s · Pipeline ADC PE Chart (< 2010) ISSCC & VLSI data...

Documents

Transcript of Recent Advances in Multistep Nyquist ADC’s · Pipeline ADC PE Chart (< 2010) ISSCC & VLSI data...