M O D E L L I N G O F H V D C C O N V E R T E R S F O R R E A L - T I M E

T R A N S I E N T S I M U L A T O R S

by

Salvador Acevedo

Electrical Engineer, Institute Tecnologico y de Estudios Superiores de Monterrey, 1985

M . E n g , Institute Tecnologico y de Estudios Superiores de Monterrey, 1987

M . A . S c , Institute Tecnologico y de Estudios Superiores de Monterrey, 1993

A THESIS S U B M I T T E D I N P A R T I A L F U L F I L L M E N T O F

T H E R E Q U I R E M E N T S F O R T H E D E G R E E O F

D O C T O R O F P H I L O S O P H Y

in

T H E F A C U L T Y OF G R A D U A T E S T U D I E S

D E P A R T M E N T OF E L E C T R I C A L A N D C O M P U T E R E N G I N E E R I N G

We accept this thesis as conforming

t o ^ e required s/ajndard

T H E U N I V E R S I T V (iv B R I T I S H C O L U M B I A

December 1997

© Salvador Acevedo, 1997

In presenting this thesis in partial fulfilment of the requirements for an advanced

degree at the University of British Columbia, I agree that the Library shall make it

freely available for reference and study. I further agree that permission for extensive

copying of this thesis for scholarly purposes may be granted by the head of my

department or ; by his or her representatives. It is understood that copying or

publication of this thesis for financial gain shall not be allowed without my written

permission.

Department

The University of British Columbia Vancouver, Canada

Date

DE-6 (2/88)

A B S T R A C T

This thesis presents developments in the computer modelling of High Voltage Direct Current

( H V D C ) converters and other F A C T S devices for EMTP-type simulators.

The high number and frequency of switching operations in power electronic converters cause

numerical difficulties that require additional computational effort. The additional computational

burden requires the development of techniques that can accelerate the simulation speeds of

conventional electromagnetic transient modelling and may allow real-time simulations.

The main results are two models that effectively reduce the computational time required to

obtain the solution of an electrical network containing H V D C converters. Both approaches have

in common the principle of subdividing an electrical circuit containing a 6«-valve converter into

at least n subsystems. For each 6-valve subsystem, the 64 matrix combinations are precalculated

and prestored in computer memory. The interaction between subsystems to obtain the network

solution is particular to each approach. With this criterion, the number of precalculated

combinations for a 24-valve H V D C substation is reduced from more than 16 mil l ion to only 256.

Both models present a considerable reduction in the computational time required to simulate

circuits containing H V D C converters. The most efficient model has been successfully

implemented in the real time power systems simulator under development by the power research

group at the University of British Columbia.

The exact calculation of the network solution at switching events is another important aspect

required to accurately simulate power electronic converters in power systems. The thesis

proposes the zero crossing detection algorithm, which eliminates the erroneous delays present in

i i

traditional E M T P simulators. The proposed algorithm resynchronizes the solution to the original

simulation time increment.

To solve the problem originated by the forced commutation of Gate Turn Of f Thyristors, an

exploratory solution technique is proposed. This methodology eliminates the unrealistic voltage

spikes that arise when chopping currents in discrete-time simulators. The resultant algorithm

avoids the necessity of forcing the semiconductors to work as pairs, as some E M T P simulators

solve the problem.

Finally, the thesis includes a model for a Thyristor Controlled Reactor that maintains a

constant conductance at switching operations, thus reducing the computational time when

modelling Static Var Compensator substations.

i i i

T A B L E O F C O N T E N T S

ABSTRACT ii

TABLE OF CONTENTS iv

LIST OF TABLES vi

LIST OF FIGURES vii

ACKNOWLEDGMENTS ix

DEDICATION x

1. Chapter 1 INTRODUCTION.... 1

1.1. HVDC Transmission Systems 2

1.2. Applications of Power Electronic Devices in Power Systems 6

1.3. A Real-Time Power System Simulator 7

1.4. Thesis Objectives 10

2. Chapter 2 HVDC AND POWER SYSTEMS SIMULATORS. 12

2.1. Analog Simulators 12

2.2. Digital Simulators 13 2.2.1. The Electromagnetic Transient Program and EMTP-Type Simulators 13 2.2.2. State Variable Simulators 16 2.2.3. TLM Simulators 17 2.2.4. Transient Stability Programs for HVDC Simulation 18

2.3. Real Time HVDC Studies 19

3. Chapter 3 COMPUTER SOLUTION TECHNIQUES. 23

3.1. Discrete-Time Solution of Networks using Nodal Analysis 23 3.1.1. Nodal Analysis 24 3.1.2. Integration Rules 25

3.1.2.1. Resistors, Inductors and Capacitors 25 3.1.2.2. Transformers 25 3.1.2.3. Transmission Lines 26

3.1.3. Filter Models 29 3.1.3.1. RLC Series 30 3.1.3.2. Parallel RL in series with C 32

3.1.4. Semiconductors 35 3.1.4.1. Diodes 37 3.1.4.2. Thyristors 39

3.2. Zero Crossing Detection 41

3.3. The Multi-Area Thevenin Equivalent Algorithm (MATE) 50

4. Chapter 4 HVDC CONVERTER MODELS 54

4.1. The High Voltage Direct Current Substation 55 4.1.1. Bridges „..56 4.1.2. Smoothing reactors 57 4.1.3. Converter transformers 59 4.1.4. Filters 61

iv

4.1.5. Controllers 63

4.2. HVDC Model I - The HVDC Object 66 4.2.1. The HVDC Object Definition 67 4.2.2. Solution of a Network containing HVDC Objects 71

4.3. HVDC Model II - The MATE Approach 76 4.3.1. HVDC Converter as an Independent Area 76 4.3.2. Multiple HVDC Converters Interconnected by Links 78

4.4. Test Cases 83 4.4.1. Simulations for a 12-pulse test system 83

4.4.1.1. Case 1: Steady-state operation 84 4.4.1.2. Case 2: DC fault 86 4.4.1.3. Case 3: Single-phase AC fault 88 4.4.1.4. Case 4: Inverter operation in steady-state 90 4.4.1.5. Case 5: Commutation failure 90

4.4.2. Simulation times 93 4.4.2.1. Model I and Model II performance 93 4.4.2.2. Simulation in OVNI 95

5. Chapter 5 MODELLING OTHER FACTS DEVICES 97

5.1. Forced Commutated Inverters 98 5.1.1. Exploratory Solution in Circuits with GTOs 100 5.1.2. Modelling a Forced Commutated Inverter using the HVDC Object 108

5.2. Static Var Compensators 112

6. Chapter 6 CONCLUSIONS AND RECOMMENDATIONS 122

BIBLIOGRAPHY 126

APPENDIX A THE MULTI-AREA THEVENIN EQUIVALENT ALGORITHM 136

APPENDIX B TRANSFORMER DISCRETE-TIME EQUIVALENT 148

v

L I S T O F T A B L E S

Table 3-1. Trapezoidal and backward Euler discrete-time equivalents for basic electric circuit elements 27 Table 3-2. Discrete-time equivalents for transformers and lossless transmission lines 28 Table 3-3. Element values and expressions for the RLC filter in the discrete-time domain 32 Table 3-4. Equations for the high pass filter in the discrete-time domain 34 Table 3-5. Procedure to check and change the state of a diode 38 Table 3-6. Procedure to check and change the state of a thyristor 40 Table 3-7. Algorithm for zero crossing detection and synchronization 48 Table 3-8. Comparison between EMTP, CDA,

and interpolation schemes for 3 time steps during a switching action 49 Table 3-9. Generalized MATE algorithm 53 Table 4-1. Generalized algorithm to solve a network containing 'n' HVDC Objects 75 Table 4-2. Generalized MATE algorithm for circuits containing W HVDC converters 82 Table 4-3. Description of the test cases 84 Table 4-4. Test cases for simulation times comparisons 94 Table 4-5. Simulation times in microseconds per time step 96 Table 5-1. Exploratory solution algorithm for circuits containing GTO thyristors 104 Table 5-2. Simulation time per simulated second-step in seconds for the SVC substation of Fig. 5-21 121

Table A- 1. MATE algorithm for two areas connected by one link 142 Table A- 2. Generalized MATE algorithm 144

vi

L I S T O F F I G U R E S

Fig. 1-1. HVDC Systems in operation in the world 4 Fig. 1-2. HVDC link: (a) Line is operating as a positive pole, (b) Line is operating as a negative pole 5 Fig. 3-1. Two-winding single-phase transformer with leakage inductance Lt 26 Fig. 3-2. Filters for HVDC converters: (a) Tuned filter, (b) High pass filter 29 Fig. 3-3. Discrete-time equivalent for the series filter using the trapezoidal integration rule: 30 Fig. 3-4. Discrete-time equivalent for a RLC filter 31 Fig. 3-5. Steps for the derivation of the discrete-time equivalent of Fig. 3-2(b) 33 Fig. 3-6. Diode symbol and model parameters 37 Fig. 3-7. Diode model: (a) V-I characteristic, (b) Turn on transition, (c) Turn off transition 38 Fig. 3-8. Thyristor symbol and parameters 40 Fig. 3-9. Thyristor characteristic 40 Fig. 3-10. Switch current for the opening transition in traditional EMTP simulators: (a) Trapezoidal rule for all

points (b) CDA algorithm at switching events 42 Fig. 3-11. Diode voltage during the closing transition with a fixed time-step scheme 43 Fig. 3-12. Switch current transition with linear interpolation 45 Fig. 3-13. Diode current with complete interpolation algorithm plus synchronization 47 Fig. 3-14. Thyristor current in a rectifier: (a) Interpolation scheme II. (b) CDA (MicroTran) 49 Fig. 3-15. Network subdivided by links and transmission lines 51 Fig. 3-16. Example for the direct formulation of MATE equations 52 Fig. 4-1. Monopolar 12-pulse HVDC substation 55 Fig. 4-2. Graetz bridge and symbol 56 Fig. 4-3. A 6-pulse HVDC converter feeding a passive load 57 Fig. 4-4. Rectified DC voltage and AC phase-a current including their corresponding harmonics for the circuit of

Fig. 4-3 58 Fig. 4-5. Effect of the smoothing reactor in the DC current 58 Fig. 4-6. A 12-pulse HVDC converter feeding a passive load 59 Fig. 4-7. Operation of the 12-pulse bridge 60 Fig. 4-8. Filter configurations and frequency response 62 Fig. 4-9. Phase-a line current when installing AC filters 62 Fig. 4-10. Constant current - equidistant 6-pulse HVDC control 64 Fig. 4-11. Voltage controlled oscillator: (a) Steady-state, (b) Idc>set point -> error>0 and Uc>0 65 Fig. 4-12. HVDC Object 67 Fig. 4-13. Inserting one of the 64 HVDC Object's matrices into the network matrix 71 Fig. 4-14. Four HVDC Objects constituting a 24-valve, 12-pulse bipolar HVDC substation 72 Fig. 4-15. Areas for a circuit containing one 6-pulse HVDC converter 77 Fig. 4-16. A 24-valve HVDC substation divided in 6 areas by 16 links 79 Fig. 4-17. The 24-valve system divided in 4 areas by 11 links 81 Fig. 4-18. 12-pulse test system 84 Fig. 4-19. Case 1. Results for steady-state operation 85 Fig. 4-20. Case 2. Results for a DC fault with controller 87 Fig. 4-21. Case 2. Results for a DC fault without controller, and current comparison against the controlled case 88 Fig. 4-22. Case 3. Results for a single-phase AC fault 89 Fig. 4-23. Case 4. Results for inverter operation in steady-state 91 Fig. 4-24. Case 5. Commutation failure 92 Fig. 4-25. Test systems: (a) 6-valve monopolar, (b) 12-valve monopolar, (c) 24-valve bipolar 94 Fig. 4-26. Solution times for the test cases with ADA 95 and MicroTran (At=50 us) 95 Fig. 4-27. Simulation times per time step (platform: single-processor Pentium Pro 200 MHz) 96 Fig. 5-1. Basic 6-pulse inverter bridge 98 Fig. 5-2. Basic inverter output voltage waveforms 99 Fig. 5-3. Buck regulator 101 Fig. 5-4. Forced commutation of a GTO in the discrete time solution 102 Fig. 5-5. Effect of the exploratory solution algorithm in solution of the buck regulator 106

vii

Fig. 5-6. Buck regulator simulations with and without the exploratory solution 107 Fig. 5-7. Forced commutated inverter simulation with the exploratory solution 108 Fig. 5-8. Inverter as an HVDC Object 109 Fig. 5-9. MS-PWM inverter simulation using the exploratory solution algorithm: (a) Load is predominantly resistive

(b) Load is predominantly inductive 110 Fig. 5-10. A 12-pulse STATCOM 111 Fig. 5-11. System voltage, inverted voltage, and inverted current for a 12-pulse STATCOM: (a) Supplying reactive

power (b) Absorbing reactive power 112 Fig. 5-12. Ideal SVC 113 Fig. 5-13. Single-phase TCR 113 Fig. 5-14. TCR current for 6=90°, 120°, and 150° 114 Fig. 5-15. SVC operating point (combined TSC and TCR) 114 Fig. 5-16. Discrete time equivalent for a single-phase TCR: (a) Normal representation (MicroTran). (b) Proposed

model 115 Fig. 5-17. Single-phase TCR connected to a TWvenin network 117 Fig. 5-18. Simulations with the new TCR model and with MicroTran for 2 firing angles (XL»X1) 117 Fig. 5-19. Effect of increasing the system inductance 118 Fig. 5-20. Effect of increasing the time step 118 Fig. 5-21. SVC substation at Langdon, Alberta 119 Fig. 5-22. Simulation results for a SVC substation 120

Fig. A-l. One link dividing a network into two areas 136 Fig. A- 2. Thevenin equivalents interconnected by the link 141 Fig. A- 3. An electrical network subdivided by links 143 Fig. A- 4. Two areas joined by two links: (a) Link currents flowing from Al to A2. (b) First link current from Al to

A2, second link current from A2 to Al 145 Fig. A- 5. Three systems connected by two links 147

Fig. B- 1. Two-winding single-phase transformer with leakage inductance Lt 148

v i i i

A C K N O W L E D G M E N T S

I would like to express my gratitude to the Instituto Tecnol6gico y de Estudios Superiores de Monterrey

(ITESM), not only for the scholarship but also for the inestimable education and professional opportunities that I

have had, first as a student and then as a professor, at my alma mater. I would like to share this accomplishment

with my good friends and colleagues from the Electrical Engineering Department at ITESM, particularly with

Federico Viramontes, Javier Rodriguez, and Hector Yeomans, who were my three best professors during my

studies, and especially with Sergio Martinez, Armando Llamas, and Jesus Baez who have had the patience to

harmoniously work with me while being my good friends.

I also thank the Consejo Nacional de Ciencia y Tecnologia of Mexico for supporting my graduate studies and

those of many other Mexicans studying abroad. I hope we are able to help our country when we come back home.

My recognition and gratitude to my thesis supervisor, Dr. Jose R. Marti, for his guidance, his pertinent advice,

his patience, and for sharing his worldwide recognized knowledge with me.

I am also thankful to Dr. Hermann Dommel, for his ideas and suggestions during the development of my thesis,

and for conferring me the honor to be part of my thesis committee. He gave me the basic idea to start the

development of the TCR model, and I am also grateful about that.

I thank Dr. William Dunford for supporting my work and for participating in my thesis committee.

I would like to thank my friend and colleague Luis Linares for taking the time to teach me OOP, for sharing

with me part of his extensive experience in language programming, and for his calmness to work with me during the

development of this project.

And last but not least, I would like to recognize the incredible friendship of Louie, Natalie, and Carmen.

I cannot express with words the deep gratitude that I have for the emotional support they gave me during these

years.

ix

D E D I C A T I O N

To my parents:

Salvador Acevedo Ricdrdez

Alicia Lilia Porras de Acevedo

Through my life I always have had the unconditional support of my parents in all my

personal and professional activities. They consistently have encouraged me to pursue a new goal

after finishing the previous one. They have been there for me at all times. I would like to

recognize their invaluable support, constant encouragement, and truthfully love by dedicating

this especial achievement to both of them.

x

C H A P T E R 1

I N T R O D U C T I O N

Electric power system networks transport electric energy from generating stations to

consumption loads. The optimal and efficient operation of these systems requires constant

research and development from power system engineers.

For many years, power system simulators have helped not only to analyze, understand and

improve the operation of power systems, but also to design new configurations and new

applications. The testing of equipment under abnormal situations is another important feature

that some simulators provide.

Analog simulators are extensively used for both analyzing and testing power networks and

their equipment. Their drawbacks are their high cost and restricted flexibility.

Digital simulators have the flexibility to simulate almost any kind of network topology. They

rely on the availability of accurate models and are widely accepted nowadays.

When modelling electromagnetic transient phenomena, digital simulators solve the electrical

network at discrete time steps, and commonly, this requires important amounts of computation.

In most cases, the number of computations is so large that the time required to obtain the solution

is several times longer than the actual simulated time. This is especially true when simulating

large networks or networks with switching operations.

Power electronic circuits contain semiconductor devices that are operated as switches with

periodical closing and opening. If the semiconductors are modeled using a digital simulator, the

switching actions increase the required simulation time.

1

The Power Systems Group at the University of British Columbia ( U B C ) is presently working

on the development of a general-purpose digital simulator for power systems. One of the

objectives is to be able to simulate cases in real time. Among other applications, this feature wi l l

allow users to test protective devices and control equipment.

The development of a real-time simulator requires models that are not only accurate, but are

fast enough to solve the network under study as fast as the real-time events that the simulator

interfaces.

During the work of this thesis, the author has developed models for High Voltage Direct

Current ( H V D C ) converters and other Flexible Alternating Current Transmission System devices

( F A C T S ) for electromagnetic transients simulation. The form and solution algorithmic design of

these models is aimed at allowing much faster solutions than conventional models while giving

results that are accurate and free of numerical noise and numerical stability problems.

1.1. H V D C Transmission Systems

High Voltage Direct Current ( H V D C ) transmission systems have several advantages over

their A C counterparts.

The main problem of A C systems is the necessity to maintain all the synchronous generators

operating in synchronism. Synchronous operation requires to keep the A C lines loaded below the

steady-state and transient stability limits, and to have a common frequency for the entire system

at all times. It is particularly difficult to maintain a stable weak connection between two large A C

systems. On the other hand, i f a D C link is used, then the power transfer capability is not related

2

to the transmission line and the two A C systems joined by the D C link are not required to be in

synchronism [76], [78].

Cables and lines for D C transmission have fewer losses and are less likely to be affected by

disturbances. However, difficulties to convert D C signals, most notably in the early years of

power systems, made alternating current systems more popular. It was not until the development

of the high voltage mercury arc valve during the 1950s, and the introduction of solid-state

technology in H V D C systems at the end of the 1960s, that D C systems became commercially

competitive. F ig . 1-1 depicts the H V D C world scenario.

Despite the benefits of D C systems and the economical savings in cables and lines, the high

cost of the required equipment in H V D C substations explains the reduced amount of H V D C

systems in the world. It is at the bulk level of transmission of electric energy, where long

transmission lines, underground and submarine lines, asynchronous interconnection of A C

systems, and interconnection of A C systems with independent control strategies, make the cost

and technical performance of D C transmission links advantageous [78]. For example, the largest

application in the world is the 6,300 M W Itaipu H V D C system installed in Brazi l [84]. The

H V D C link at Itaipu provides a 50/60 H z asynchronous tie which allows transmission distances

in the order of 800 km.

To achieve high voltages, Sil icon Controlled Rectifiers (SCRs, also called thyristors) are

connected in series to form a valve. A single thyristor is commonly designed for 8 k V , and

typical applications have up to 60 series-thyristors per valve [32]. The operation of thyristors is

explained in further detail in section 3.1.

3

Fig . 1-1. H V D C Systems in operation in the world.

A n H V D C link has one sending end and one receiving end. There are several configurations

in use depending on the number of converters and lines. A monopolar system has only one pole

that may have either positive or negative voltage, and normally has a ground return. A bipolar

system essentially consists of two monopolar systems of opposite polarity. A back-to-back

converter is mainly used to interconnect systems with different frequencies; it does not have a

D C transmission line and both converters are at the same substation.

The converter located at the sending end is called the rectifier and the converter at the

receiving end is the inverter. For power reversal, the voltage polarity is changed and the rectifier

now receives energy, thus becoming the inverter, and vice versa. It should also be noted that,

because of the commutation requirements of thyristor valves, thyristor based D C links require

A C systems at both ends. F ig . 1-2 shows the sending end and receiving end for each polarity of

the D C line.

4

SENDING END + + + Line voltage is positive +++ RECEIVING END

CONVERTER IN

RECTIFIER MODE

(a)

CONVERTER IN

INVERTER MODE

RECEIVING END Line voltage is negative - • SENDING END

CONVERTER IN

INVERTER MODE

(b)

CONVERTER IN

RECTIFIER MODE

Fig . 1-2. H V D C link: (a) Line is operating as a positive pole, (b) Line is operating as a negative pole.

From the power system perspective, the control of an H V D C system is fast and simple.

However, the power electronic semiconductors that constitute the D C bridges require

sophisticated controllers with accurate and reliable circuitry and the substation design and

installation are fairly complicated when compared to A C transformer substations. Also , the

interactions among A C - D C systems can be quite complex [83]. It is at this level where analog

and digital simulators provide an excellent tool for the planning, design and development of D C

based systems [60].

5

1.2. Applications of Power Electronic Devices in Power Systems

The application of power electronic devices in power systems has been gaining popularity as

manufacturing companies increase the rating of semiconductor devices, and as more reliable

controllers become available. These factors have permitted and encouraged a substantial growth

of H V D C links during the last two decades [12], [32], [76]. The use of thyristors has evolved into

the development of F A C T S devices to improve the operation and control of A C systems [12],

[31], [33].

Thanks to the semiconductor revolution, Direct Current transmission systems now are

practical. There are yet other H V D C related applications, and some of them are now briefly

described.

Static Var Compensators ( S V C ) improve voltage regulation by generating or absorbing the

required reactive power at strategic points in the network [28]. The first S V C s were developed in

the late 1960s. The basis of their operation is the dynamic adjustment of reactive power by

connecting or disconnecting Thyristor-Switched Capacitor banks (TSC) and by controlling

Thyristor-Controlled Reactors (TCR) [71].

In addition to their present use in certain applications, newer developments in high power

Gate Turn Off thyristor (GTO) technologies are the future for a large spectrum of modern and

sophisticated power system applications [53], [70], [77], [105], [108], [109], [110]. Chapter 5

includes models developed in this thesis for efficient modelling of GTO-based converters.

The advanced static V A R compensator or S T A T C O M is the power electronic version of the

synchronous condenser. A modulated G T O inverter converts the D C voltage of a charged

capacitor into an A C voltage. S T A T C O M s provide both lagging and leading reactive powers by

6

adjusting the inverted voltage. Detailed theory on advanced static V A R compensators can be

found in [21] and [29].

In [92], Schauder et al. planned the first large application of a ±100 M V A R S T A T C O N (now

S T A T C O M ) substation. Another application presented by Kimura et al. demonstrates how a

static condenser can help improve the performance of an H V D C inverter when feeding a weak

A C system [46].

The use o f G T O thyristors in H V D C converters allows the supply of remote passive loads

without A C generation. A large 300 M W self commutated inverter is under development [95].

H V D C Light [1] is the first successful application of a self commutated H V D C inverter

feeding a passive load (where there is no A C source). Instead of dealing with bulk power

transmission, H V D C Light is designed to use the advantages of D C transmission when

transmitting just a few M W to a passive load. This first 10 km, 3 M W ±10 k V H V D C Light

installation was commissioned in Sweden in March, 1997 and is based on a forced commutated

voltage source converter (VSC) . This new technology promises to be an alternative to

conventional A C transmission or local generation under situations where the load size and

location are relatively small when compared to traditional H V D C links.

1.3. A Real-Time Power System Simulator

Software based power system simulators have turned out to be not only an excellent tool in

the analysis and design of networks and devices, but also have become an essential instrument

for the power systems engineer.

7

When studies are performed off-line, system data is collected and entered into the computer,

processed by the simulator, and analyzed once the simulation output is ready. Sometimes several

iterations give a clearer picture of the situation under study and help make decisions.

In the case of performing online simulations, the user can interact with the power system

with the help of a computer simulator. The importance of the interaction between the user and

the computer becomes crucial i f the simulator results are used to control the network. The actions

that the operator takes after obtaining the computer results w i l l affect the system response. Stand­

alone online simulators do not require contact with any operator but may exchange information

with other computers or with a physical controller.

Critical factors in real-time applications are the simulation time and the accuracy of the

models. The simulation time is the time that the simulator takes to solve the programmed models

that represent a particular system. In an online simulator, real-time simulation is essential.

Real-time simulation implies computation of a phenomenon and precise reproduction of its

behaviour at the same rate as the phenomenon occurs. For slow changing systems, the currently

available digital computers are likely to be able to simulate and reproduce a case in real time. For

power electronic applications in power systems, a frequency bandwidth of about 2 k H z in the

solution waveforms is considered adequate. If real-time performance is desired, the simulator has

to produce a solution in less than the chosen integration step. Taking into account the distortion

introduced by the integration rule (e.g. trapezoidal or backward Euler) in the numerical solution,

an integration step of 100 ps produces a distortion error of about 10% while an integration step

of 50 (j.s reduces this error to about 3%. On the other hand, a 50 ps step corresponds to

approximately 1° in the firing angle of the converter valves, and this resolution or better may be

8

desirable in some cases involving the proper operation and testing of controller actions. With the

use of such small time steps, it is possible to perform accurate investigation of faults, harmonic

interference, resonance and other fast transient phenomena of special interest when modelling

H V D C systems [88].

During the past few years, the main interest of the Power Systems Group at U B C has turned

to the development of a software-based real-time simulator for power systems. References [64],

[67], and [68] present the latest efforts of the group. This simulator is named Object-oriented

Virtual Network Integrator (OVNI™) [52], [68]. It is a goal to have the first release ready within

the next year.

The main intention of O V N I involves having a computer program that is running

continuously while simulating the power system. For instance, the program simulates any normal

or abnormal behaviour of a power system network in real time and may suggest actions to

prevent instability. Another application is the testing of protective equipment and control

equipment without having to provoke faults in the actual power system. N e w control strategies

can be extensively experimented using such a simulator. If the simulator behaves as the power

system, then the tested device may be connected directly to a hardware interface, and the

computer simulates the power system behaviour to prove and adjust the equipment. More

advanced applications w i l l allow prediction and correction under disturbances with the support of

artificial intelligence routines.

9

1.4. Thesis Objectives

The O V N I simulator requires the development of models for each element of a power

network that are suitable for real-time simulation. Power electronic devices are of special interest

to the power systems community involved in the development of real-time digital simulators.

The objective of this thesis is to provide a model for High Voltage Direct Current Converters

that can be adapted to the O V N I simulator under development.

A s a result of the research, the author presents two approaches to modelling H V D C

converters that considerably improve solution times over off-line simulators like MicroTran®

( U B C ' s Electromagnetic Transients Program). One of these approaches has already been

implemented in a companion research project [52] and proven its real-time performance [64].

It is important to mention that the models developed in this work achieve real-time

performance within the context of a simultaneous solution with the rest of the power network. To

this author's knowledge no other research group working on real-time simulators has achieved

real-time performance for full-size converters (12 and 24 valves) with simultaneous power

system and converter solutions. Alternatives have been proposed in which the solution of the

converter is decoupled from the solution of the network by a time delay equal to the solution

time step [101]. This approach allows an independent solution (possibly in separate processors)

of the network and of the converter. The problem with this approach is that it can lead,

depending on the simulation, to not only inaccurate solutions but also to numerical instability.

The possibility of having these problems was considered unacceptable under the concept of

O V N I which is that of a continuously running simulator, thus requiring high confidence in the

results and absolute long-term numerical stability of the output.

10

In addition to the modelling of H V D C converters for real-time simulators, research was also

done on accuracy and numerical optimization issues pertaining to other F A C T S devices. One of

these issues was the development of an efficient zero crossing detection and interpolation

algorithm to accurately simulate the commutation point of the valves within the context of the

Critical Damping Adjustment algorithm ( C D A ) of the E M T P [66]. Another development is an

efficient exploratory solution algorithm for the accurate simulation of GTO-based forced

commutated converters such as the H V D C GTO-inverter feeding passive loads and the

Advanced Static Converter ( S T A T C O M ) . Further work permitted the creation of a model for the

simulation of Static V A R Compensator substations (SVC) with improved solution times.

A l l o f the models and features described above have been programmed and tested in an

Object Oriented Programming (OOP) environment using the A D A 95 programming language.

This document has six chapters including this Introduction in Chapter One. Although the

complete document includes appropriate references, Chapter Two is an extensive literature

review and a discussion of H V D C simulators. Chapter Three reviews briefly the nodal analysis

and the discrete time solution technique of the original Electromagnetic Transients Program

E M T P . This chapter also includes the diode and thyristor models, the filter models, the zero

crossing detection algorithm, and an example of application of the Mult i -Area Thevenin

Equivalent Algori thm ( M A T E ) . Two H V D C models, with very good solution speed times, are

proposed in Chapter Four, while Chapter Five is reserved for the models of some F A C T S

devices, such as forced commutated inverters, S T A T C O M s and S V C s . Finally, Chapter Six

contains the conclusions of this work and suggestions for future developments. Appendix A

includes a description of the M A T E algorithm. Appendix B contains the derivation of the

discrete-time equivalent model for power transformers.

11

C H A P T E R 2

H V D C A N D P O W E R S Y S T E M S S I M U L A T O R S

Both analog and digital simulators are useful tools to model the behaviour of fast transients

in power systems and play an important role when analyzing H V D C systems and their controls.

A literature review of power system simulators for H V D C and related problems is now

presented.

2.1. Analog Simulators

Analog simulators are also known as Transient Network Analyzers ( T N A ) and those for

H V D C systems are known as D C simulators. A D C simulator consists of a physical scaled-down

replica of the system under study. These simulators always operate in real time because they are

physical devices interconnected as the original system they represent. They also give a practical

sense of the case under study.

The real-time ability of D C simulators makes them excellent tools for testing of protective

devices and H V D C or F A C T S controllers. D C simulators have been successfully used for many

years in the design of H V D C schemes [37], [60].

The disadvantages of D C simulators are the expensive cost of the equipment, the restricted

flexibility to represent different networks, and the lack of accurate representation of some

elements. For example, to represent a transmission line, a T N A uses multiple n or T sections of

resistors, inductors and capacitors. This configuration cannot very accurately represent the

distributed nature and frequency dependence of the line parameters [67]. To overcome this

12

problem, Mathur and Wang [69] have proposed to incorporate a digital model of the transmission

line to a T N A using digital-to-analog converters.

2.2. Digital Simulators

The most common approaches used to solve transients in H V D C systems are: the use of

programs developed under the Electromagnetic Transients Program ( E M T P ) technique, the State

Variable technique, the Transmission Line Modell ing ( T L M ) method, and the use of transient

stability programs.

2.2.1. The Electromagnetic Transient Program and EMTP-Type Simulators

These digital simulators use a mathematical discrete-time model for each network element.

B y choosing an appropriate methodology, they combine the element models to solve the system

equations. Among the advantages of digital simulators, it is worthwhile to emphasize their

accuracy, their non-susceptibility to environmental factors, their flexibility, and their lower cost.

The E M T P is based on Dommers algorithm [17] and is probably the most widely accepted

computer program for electromagnetic transient studies in power systems. In [56], Long et al.

presented a summary of the different E M T P capabilities. The models in this thesis are based on

E M T P methodology. Due to the importance that this has for this project, section 3.1 is dedicated

to illustrate the E M T P foundation. A l l the models and cases developed during this research were

compared against the results obtained with the program MicroTran, which is based on the U B C

version of the E M T P .

E M T P simulators have been extensively validated in the simulation of power systems

containing H V D C converters. In [26], [30], and [60], there are complete validations of H V D C

13

models in the E M T P with field data obtained from the Pacific H V D C Intertie and the

Intermountain Power Project H V D C transmission systems. Additionally, [60] compared E M T P

simulations with tests performed on a D C simulator. These papers' conclusions coincide in

stating that E M T P simulators are excellent tools for the simulation of H V D C transmission

systems. A paper comparing E M T P with field test measurements on the Hydro-Quebec - New

England system is presented by Mor in , Bur i , Casoria and Reeve in reference [73].

Woodford, Gole and Menzies presented the structure and performance of the Manitoba

Hydro Electromagnetic Transients Program for D C systems ( E M T D C ) as compared to field data

for a fault recorded at the Nelson River D C Transmission system [103]. E M T D C is also based on

Dommel's algorithm placing emphasis on the simulation of H V D C systems, and in particular,

their controllers. E M T D C has proved to be an excellent simulator for the solution of H V D C

control problems [100] and is the base for the Real Time Digital Simulator (RTDS™) developed

by the Manitoba H V D C Research Centre [48], [74].

Other comparisons useful for the validation of H V D C cases with EMTP-type simulators can

be found in [11], [13], [45], [85], [93], [96], [98], [102], [104], and [111]. For those involving

F A C T S devices the reader may consult [51], [87], and [91].

N E T O M A C is a digital program used in Europe for the simulation of electromagnetic

transients developed under the E M T P methodology. In [47], Kruger and Lasseter used

N E T O M A C to simulate the transient behaviour in H V D C converters. The main difference of

N E T O M A C is that it allows the shifting of the time mesh to coincide with a switching event.

This shift, coupled with the correction in the integration solution, eliminates the problem of

14

numerical oscillations. With this scheme, however, the simulator output is not available at

uniform time steps, which poses a problem for real-time solutions.

P E C A N , now P S P I M , is another example of a circuit analysis simulator useful for the

analysis of power electronic circuits [3], [39], [90]. P S I M has a user friendly interface. It has

been a useful simulator for H V D C studies, and has good capability to model the converter

controllers as demonstrated by Jin, Sood, and Chen in [40].

Simulators such as E M T P , MicroTran, E M T D C , N E T O M A C and P S I M have demonstrated

how to produce accurate results when modelling H V D C systems, and are widely used

worldwide. In all these simulators, however, there is a notorious increase in the computational

effort required to obtain the solution at switching events. The resultant augmented solution times

hinder any attempt to obtain simulations of power electronic devices in real time.

The iterative solution of the discrete-time equations of a network equations with the Newton-

Raphson leads to the development of important general-purpose programs such as SPICE

(Simulation Program with Integrated Circuit Emphasis) [75] and Saber [60]. One advantage of

these programs is their ability to use elaborate models of microelectronics and integrated circuits,

a very important feature for the design of semiconductors and chips. Despite the emphasis on

integrated circuitry that SPICE has, it is also useful for the simulation of power converters in

power systems. See [106] as an example of the simulation of a S T A T C O M using PSPICE.

In SPICE-type simulators, the solutions are even slower because the detailed modelling of

semiconductors involves sets of non linear equations that in many instances increase the number

of iterations per time step. A n appropriate set of equations for semiconductors is essential for the

modelling of electronic amplifiers and integrated circuits, because their transistors operate in the

15

active zone at almost all times. For power electronic applications, though, the semiconductors are

operated as switches; in the case of using transistors, this is accomplished by turning them either

into saturation or cutoff. Therefore an on/off representation is satisfactory.

2.2.2. State Variable Simulators

The state variable formulation uses the network topology to generate incidence matrices.

Kirchhoff laws are then applied and differential equations are generated using a Tableau. The

solution is then found using any integration technique.

A s opposed to the E M T P , a variable time step is allowed with the state variable technique. In

fact, this has been advantageous when simulating power electronic converters and some authors

have interfaced E M T D C solutions of power systems with the state variable representation of

H V D C and S V C converters. In [27], Gole and Sood used a state representation for a S V C

converter and an E M T P representation for the rest of the network. Their excellent work uses a

reduced time step during switching operations for the S V C only and keeps a fixed time step for

the rest of the network. A similar procedure is presented for an H V D C converter by Zavahir,

Arril laga and Watson [107]. The simulation does not slow down notoriously because only the

solution of the converters are simulated with a reduced time step. In [72], Mi l ias , Hatziadoniu

and Galanos developed a general and computationally efficient algorithm for the construction of

state equations of power converters as a function of the state of their switching elements, thus

reducing the number of operations required by the algorithm.

The simulation of any circuit is feasible with the state variable algorithm since it is of general

purpose. Examples of programs using this technique for the simulation of H V D C and other

power electronic converter systems are the Converter Analysis Program ( C A P ) [54], the

16

Switched Electronic Analysis Program ( S W E A P ) [16] and A T O S E C 5 and A T O S E C M [97], just

to mention a few.

There is an interesting comparison between the E M T D C and a Transient Converter

Simulator (TCS) based on the state variable formulation showing similar results and similar

simulation times for an H V D C test circuit under certain circumstances [7]. The authors of this

paper mention that despite the reputation of less efficiency attributed to the T C S , the results

obtained show its advantages.

The main drawback of simulators based on the state variable formulation is the requirement

of an iterative algorithm to find the solution at each time step. The number of iterations is

sensitive to non-linearities in the circuit, thus considerably increasing the computational time at

switching events. Such a disadvantage makes state variable-based simulators much slower than

EMTP-based simulators. This explains why the authors in [22] and [95] (from the discussion

presented above) combined the E M T P representation for the network with the state

representation for the converters.

2.2.3. T L M Simulators

The Transmission Line Modell ing ( T L M ) technique applied to the solution of power

electronic switching networks is detailed in [34]. Each element is converted to a discrete-time

equivalent by the use of transmission line sections and a constant matrix is formed. In order to

keep the matrix constant, Hui and Christopoulous [34] model diodes and thyristors as an

inductance for the closed state and as a capacitance for the open state. Applications of the T L M

technique to the simulation of power electronic converters can be studied in [24], [34], [35], and

[36].

17

The approximation of a switch as an inductance/capacitance for the on/off states can also be

done with the E M T P by using a constant conductance and changing the history source equation

in the discrete-time equivalent. In [82], Pejovic and Maksimovic related both approaches.

T L M is an innovative way to discretize an electric circuit, and can be visualized as an E M T P

dual. Nevertheless, the representation of the elements as a transmission line introduces modelling

inaccuracies. A transmission line always includes both inductive and capacitive effects, and,

most likely, the simulation of pure inductors or capacitors is subject to error.

2.2.4. Transient Stability Programs for H V D C Simulation

Transient stability programs are used to solve the dynamic response of power networks, and

in particular, the effects of the disturbance on the frequency. In transient stability programs,

H V D C converters and F A C T S devices can be modeled as quasi-steady state elements where the

D C and A C quantities are related by transfer functions [41], [79], [88], [104]. Because in these

programs H V D C converters are visualized from the outside terminals, it is not necessary to

represent the valves' behaviour in detail. If the D C converter is not the main focus of attention

during the analysis of a network, this approach may have some merit. The lack of detail in the

simulation of the H V D C converter saves computational effort. Moreover, because the individual

valves are not modeled thoroughly, it is possible to use large calculation steps, in the order of

100-200 ps, as suggested by Woodford et al. [104].

Since this approach lacks a detailed representation of the converter's components, it is not

useful for modelling the behaviour of the H V D C converter during fast transient phenomena, A C

faults, D C faults, converter faults (e.g., commutation failures and misfiring), or to study the

H V D C controls and protection schemes.

18

2.3. Real Time H V D C Studies

Researchers around the world are working on optimizing models and algorithms and on

using state of the art technology to make real-time digital simulation of H V D C systems a reality.

The large number of switching operations in the digital simulation of power electronic

devices requires special attention i f real-time performance is attempted.

In EMTP- type simulators, each switching operation requires a change in the admittance

matrix, which is a time consuming task. In [60], Martensson et al. emphasized that E M T P does

not offer the advantages of real-time simulation, capability inherent with a D C simulator which is

of critical importance to suppliers of H V D C equipment.

The state variable technique requires a reformulation of the state equations. This process is

computationally expensive. Attempts to maintain the admittance matrix constant during an

E M T P simulation and the use of the T L M method have been referred to in section 2.2.3.

Other attempts to achieve real-time simulation are now discussed, and some of them have

already been successful when using appropriate hardware/software technology.

The Manitoba H V D C Research Centre developed a Real-Time Digital Simulator (RTDS).

This real-time digital simulator is probably the most recognized application of this kind available

for power systems. In [48], Kuffel et al. presented details on the design, architecture and

applications of R T D S . The simulator is a combination of specialized computer hardware and

software designed specifically for the solution of power system electromagnetic transients. Its

capabilities allowed it to substitute for existing analog simulators in applications such as the

testing of protective relays and the testing of system controllers. The hardware is organized into

19

individual racks. Each one contains digital processing cards for interfacing with a host computer,

and for communication among processors. The software includes a graphical user interface, a

compiler, and a library with power system component models written in low level machine

language code. The systems under study are subdivided into areas isolated by transmission lines

and these areas are solved separately in individual intercommunicated racks using nodal analysis

as in the E M T P .

R T D S has also been used to expand the capability of traditional D C simulators. For example,

an interconnection of an analogue simulator to R T D S is shown in [9] and [50]. This application

permits the representation of larger A C networks and the use of the accurate modelling of system

elements available when using digital simulators. A n actual H V D C controller may be completely

modeled with R T D S as demonstrated by Giesbrecht, Jiang and Mazur in [25]. In [99], Valiquette

et al. used R T D S to optimize the controller system of an H V D C station in the Manitoba Hydro

Power System.

In R T D S , the splitting of the network into independent areas can introduce inaccuracies i f

these areas have coupling between them. This is not a problem when the areas are separated by

transmission lines, since the lines effectively decouple the network. However, to achieve real­

time performance, the user needs to chose other points for subdividing the network where there

are no transmission lines. For these cases, Kuffel et al. suggest to identify tightly coupled

components to subdivide the network [48]. The solution in terms of these tightly coupled areas

with a time-step delay may lead to poor accuracy and instability problems. Moreover, the user

requires a vast knowledge of computer modelling of electrical networks, and an extensive

familiarity with the tested system. Interconnection of the R T D S simulator to analogue simulators

can introduce the same problems. Another limitation is the rigidity of a test system once it has

20

been set up; making changes to the network topology may be difficult and time consuming. In

addition, the high cost of the R T D S equipment gives it a limited market.

The subdivision of the system into areas is similar to the methodology proposed and

implemented in U B C ' s Real Time Network Simulator (RTNS) , by Mart i and Linares in [67].

R T N S has as an advantage that it is completely software-based providing flexibility to simulate

different configurations. R T N S was the starting point for the new O V N I development [52], [68].

Parallel processing techniques using multiple processors have also been proposed to achieve

improvements in the solution speed. In [10], Bridges et al. used parallel processing techniques to

simulate the behavior of a Static Var Compensator.

In the parity simulator presented in [42], the state variable equations of the studied circuit are

hardwired in an analog computer. Physical modules for integrators, summers, multipliers,

divisors, source generators, limiters, and other basic components are interconnected and the

solution is obtained in real-time. Unfortunately, topological changes require a reformulation of

the equations and new interconnections of the components.

Another power electronics simulator, using the state variable approach, uses multiple digital

signal processors and solves the network at nearly real-time speeds [86].

For relay testing, reference [44] illustrates an EMTP-type digital simulator with real-time

performance. Although it is not directly related to H V D C systems, this application presents a

clear example of the usefulness of a real-time simulator. This design uses a conventional single

processor in combination with advanced digital signal processors.

21

Computer simulation is an important step when developing new systems. Detailed modelling

of the power electronic equipment is needed when testing actual physical controls and protective

relay equipment. The use of analog simulators and real-time digital simulators is the easiest way

to corroborate an adequate functionality whenever new equipment is introduced or changes in the

system operation are studied.

2 2

3 . C H A P T E R 3

C O M P U T E R S O L U T I O N T E C H N I Q U E S

The first part of this chapter reviews the fundamentals of nodal analysis and E M T P

discretization techniques, and describes how these are applied in the models developed in this

thesis for the elements of an H V D C converter station. The second part contains an algorithm that

improves the accuracy of the solution of circuits containing switches by detecting the exact

instant at which the current crosses zero; the algorithm resynchronizes the solution to maintain a

fixed time step in the output. The last part reviews the use of the Mul t i -Area Thevenin

Equivalent ( M A T E ) algorithm to subdivide a network into subsystems that can be solved

independently.

The contents of this chapter are the base for the development of the new H V D C and F A C T S

models derived during this thesis work which are part of the O V N I Project in progress in the

Power System Simulation research group [68].

3.1. Discrete-Time Solution of Networks using Nodal Analysis

In the E M T P , every element is converted into its discrete-time equivalent. I f a constant time-

step size is used, nodal analysis can be applied by forming a constant conductance matrix and a

current source vector. If a variable time step is desired, the conductance matrix has to be

reevaluated whenever the time-step size is changed. The matrix also needs to be reevaluated i f

there is a change in the network topology. For example, to simulate power electronic circuits, the

E M T P models the semiconductors as ideal switching devices. Every time a valve opens or

closes, a switching event is generated and the conductance matrix is changed accordingly [18],

[20].

23

The E M T P uses the trapezoidal rule of integration which has good accuracy as demonstrated

in [65]. The trapezoidal rule, however, produces numerical oscillations when discontinuities

arise; the use of Critical Damping Adjustment ( C D A ) , developed by Marti and L i n [66], solves

this problem.

3.1.1. Nodal Analysis

Nodal analysis is based on Kirchhoff s Current Law leading to the formulation of a system

of N equations of the form,

Y V = J

( 3 - 1 )

where: N is the number of nodes in the system, excluding ground Y is the admittance matrix (order NxN) V is the vector of N voltages referred to ground J is the vector of N current sources injected into the nodes

For each independent voltage source, the voltage of the node at which the source is

connected is known. If there are N 2 sources, the number of nodes with unknown voltages is

N1=N-N2 and (3-1) can be partitioned as follows,

V J l

v 2 _ . J 2 _

then

Y..V,

( 3 - 2 )

where: V, is the vector of Nl nodes with unknown voltages referred to ground V 2 is the vector of N2 nodes with voltage sources connected to it (known voltages) Y n , Y 1 2 Y 2 1 , Y 2 2 are admittance submatrices of order NlxNl, NlxN2, N2xNl, N2xN2, respecitvely J, is the vector of source currents entering the Nl unknown votage nodes J 2 is the vector of source currents entering the N2 known votage nodes

24

Equation (3-2) is a system of N l equations that can be solved for V , by any numerical

method. Currents in the element are then obtained using the original elements' branch equations.

3.1.2. Integration Rules

Each element in an electric circuit has a certain relationship between its voltage(s) and

current(s). Sometimes this relationship is a differential equation (or a set of differential

equations) that can be translated to the discrete-time domain generating difference equations.

These equations can be represented by a discrete-time equivalent circuit consisting of resistance

and source combinations. Their values depend on the integration rule.

If each element of a network is represented by its discrete-time equivalent, nodal analysis can

be applied for the solution of the circuit at discrete time steps. Since the discrete-time equivalents

contain only conductances, the admittance matrix Y in (3-1) does not have reactive components

and becomes a conductance matrix G [17].

3.1.2.1. Resistors, Inductors and Capacitors

Table 3-1 shows the discrete-time equivalents for resistors, inductors, and capacitors using

both the trapezoidal and the backward Euler integration rules. The reader may consult [18] and

[66] to review the basis of the derivation of these equivalents.

3.1.2.2. Transformers

Transformers are modeled as ideal transformers with leakage inductance. Winding

resistances and a magnetization branch can be added externally. The derivation of the

transformer equivalent of Fig . 3-1 using the trapezoidal rule is presented in Appendix B . The

same procedure can be extended to three-phase transformers and to n-winding transformers.

25

Both the trapezoidal and the backward Euler equivalents for the two-winding single-phase

transformer of F ig . 3-1 are summarized in Table 3-2.

3.1.2.3. Transmission Lines

There are several transmission line models for EMTP-type programs; among them we have

the constant parameter line model [20], and those including frequency dependance [14], [59],

[61]. For simplicity in the initial development of the proposed H V D C model, the constant

parameter line model was implemented (Table 3-2). To include the line resistance (losses), two

line segments are used with concentrated resistances at both ends of each segment.. In the context

of the O V N I real time simulator, transmission lines in the proximity of the part of the system

under study are more accurately represented using a frequency dependent line model, particularly

when line to ground faults are involved. For the range of frequencies under consideration

(<4 kHz), a two- or three-pole frequency dependent model for the ground mode with the rest of

the modes modeled as constant parameters is sufficient for a very accurate line representation.

The increase in the total system solution time would normally be in the order of 20 to 30%

(closure to [67]).

n=Nl/N2

Fig . 3-1. Two-winding single-phase transformer with leakage inductance Lt .

26

27

28

The structure of the transmission line models in the discrete-time domain both for constant

and frequency dependent parameter line models (such as [14], [20], [59], and [61]) allows an

effective decoupling of both ends of the line through the traveling time x. A s long as the solution

time step is smaller than the traveling time, the equivalent circuit at one end of the line is

independent of the equivalent circuit at the other end. This peculiarity presents a numerical

advantage because the nodal analysis formulation can be subdivided to solve the independent

subnetworks split by the transmission line [67].

3.1.3. Filter Models

A more efficient converter station filter model can be obtained by combining the components

of the filter branch into a single equivalent discrete-time equation. A discussion of the filters'

functionality, its usefulness in power systems, and the details of an H V D C substation, can be

found in Section 4.1. Two cases are considered: R L C series, and parallel R L with series C.

Fig . 3-2 shows two passive filter arrangements used in H V D C substations on both D C and A C

sides [85].

+

R L C A A A — |£-

R H W V 1 c

L

(a) (b)

F ig . 3-2. Filters for H V D C converters: (a) Tuned filter, (b) High pass filter.

29

3.1.3.1. R L C Series

Using the trapezoidal discrete-time equivalents shown in Table 3-1, the series R L C circuit of

F ig . 3-2(a) is represented as shown in F ig . 3-3 (as proposed in [18]).

From the circuit,

V = V L + V R + V C

( 3 - 3 )

Resistance

R

—wv

R

—wv

Inductance

G=At/2L

i — W V -

(a)

R=2L/At -AAAr- •'hL i \ i—\ K i t-^f & h r

-O v w - O ^ (b)

Capacitance

G=2C/At l — W V -

<3k

R=A t /2C e

Fig . 3-3. Discrete-time equivalent for the series filter using the trapezoidal integration rule:

(a) A s obtained from Table 3-1. (b) In Thevenin form.

If we define:

i=i(t)

i' = i(t-At)

vL' = vL(t-At)

vc = vc(0

vc' = vc(t-At)

VR=VR(t)

vr' =vR(t-At)

current at t ime ' t '

current at time 't-At'

voltage across the inductance at t ime ' t '

voltage across the inductance at time 't-At'

voltage across the capacitance at t ime ' t '

voltage across the capacitance at time 't-At'

voltage across the resistance at t ime ' t '

voltage across the resistance at time ' t-At'

30

v =v(t) => total R L C voltage at t ime ' t '

v ' = v(t-At) =^> total R L C voltage at time 't-At' ehL =ehL(0 ^ inductance history source voltage at t ime ' t ' ehC = £hc(t) ^ inductance history source voltage at t ime ' t ' eeq = eeg(t) => equivalent history source voltage at t ime ' t ' h =h(t) => equivalent history source value at t ime ' t '

The history sources for the trapezoidal rule of integration are:

2L h L At

At Cur- = — /'—V̂ '

2 C C

( 3 - 4 )

The resistances obtained in Fig . 3-3(b) can be added to give an equivalent resistance. Adding

the individual sources also produces an equivalent source. The result is in F ig . 3-4.

eq Req

- A V V f +)- Thevenin to Norton

Geq A A / V

heq

Fig . 3-4. Discrete-time equivalent for a R L C filter.

The values and the expressions for the equivalent elements are presented in Table 3-3. The

same procedure can be repeated using the backward Euler integration rule to obtain the circuit o f

Fig . 3-4 with different values for the equivalent elements (also shown in Table 3-3).

31

T R A P E Z O I D A L R U L E

+

1

i = vGeq + heq

2L At R + ^ t + 2 C

Kq = Geq v'-2 vc' + 2L_ At_

^At~2C

At

RJr =[Av'+Bvc'+cr]

V^2~d (/ + r ) + v c '

A = G eq B = -2G C = G ^ eq eq

2_L At_

At ~ 2C R

B A C K W A R D E U L E R R U L E

i = v Geq +heq

Ge« 2L At R + ^+2-C-

Kq = Geq -2vc' + ^ji' =[Av'+Bvc' + Ci']

A = 0

, A 0 • .

B = -Geq C = Geq

At

Table 3-3. Element values and expressions for the R L C filter in the discrete-time domain.

3.1.3.2. Parallel R L in series with C

For the filter of F ig . 3-2(b), the discrete-time equivalents for the resistance and the

inductance connected in parallel are first combined into a single one, and then are added to the

capacitance equivalent to generate the discrete-time equivalent for this filter. The steps are

presented in F ig . 3-5.

32

Resistance

G=l/R A / V V

G=At/2L

I W V "

Inductance

G^At^L+l/R G=2C/At

i — W V — i i—wv-

Resistance & Inductance

eq Req /r-^s

- A / V V - ( - +J-

Capacitance

G=2C/At r-^WV-

RRL=1/GRL E > R=At/2C eh c

— w v — G W V - H G ^

Geq

heq

Fig . 3-5. Steps for the derivation of the discrete-time equivalent of F ig . 3-2(b).

A s it may be expected, the values for the equivalent depend again on the integration rule

ee Table 3-4).

33

T R A P E Z O I D A L R U L E

i = vGeq + heq heq=[Av'+Bvc' + Ci]

eq

1 At_ R<«-f\_ At)+2C

R + 2Ls

A =G eq

At_ J _

2L~ R At_ J_ 2L + R~

B = -G eq

2_L R At_ j _

^2L + RJ

+ 1 C = G 1

1 *L R + 2L

At

2C

At V C = 2 C ( / + / " ) + V C '

B A C K W A R D E U L E R R U L E

i = vGeq +heq heq=[Av'+Bvc' + Ci']

° e q R„

1 At Re« ~'f\ AO ' C

1 + L

A=G eq

R At 1 £ = G

«9

R At_ I

V 2 Z + RJ

C = G eq

1

' J _ At_

k~R+L

Vc = ~cl+Vc

Table 3-4. Equations for the high pass filter in the discrete-time domain.

34

3.1.4. Semiconductors

The semiconductor devices commonly used in H V D C systems and F A C T S devices are

diodes, thyristors and GTOs. Thyristors and GTOs are used to control the transfer of electric

energy by behaving as controlled switches.

Among the available computer models for semiconductors, the one to use depends on the

level of detail desired during the simulation. For power converters, an O N / O F F switch is

generally sufficient for the analysis of the transferred energy and for the study of the behaviour

of voltages and currents in the converter. In this case, the semiconductor may be visualized as an

ideal or quasi-ideal switch. Semiconductor designers, on the other hand, often require the use of

more detailed models than those commonly used in E M T P simulators.

The original E M T P and different EMTP-type programs such as MicroTran use ideal

switches. In these programs, each switch in the circuit is defined between two network nodes. If a

switch closes, the two nodes collapse forming a common node. The program then reduces the

order of the admittance matrix. If the switch opens, the nodes are separated, and the order of the

matrix is now increased [18].

In addition, when modelling diodes, appropriate voltage polarity is checked for closing the

switch, and zero crossing of the current is checked when opening. When the device is a thyristor,

a firing signal must also be present to allow switch closing. G T O ' s forced commutation is

achieved by comparing the current with a very large value (normally many times higher than the

order of magnitude found in the circuit). Once the order to open has been given, opening takes

place i f this value is larger than the current [18].

35

Another approach for switch modelling uses a variable resistance with a high value when the

switch is opened and a low value when the switch is closed. Collapsing o f nodes is not necessary

in this case, thus maintaining the dimensions of the conductances matrix constant. A high/low

variable inductance is a variant to this approach [94].

When switches are modeled as O N / O F F binary elements, a switching operation modifies the

admittance matrix. This requires a new matrix factorization or matrix inversion depending on the

solution algorithm.

A s an attempt to improve the solution speed, [34] and [82] model a switch as an

inductor/capacitor that has the same resistance value in the discrete-time equivalent for both

states (open and closed). For a given At, a small value for the inductance in the O N state provides

the required capacitance value for the O F F state. Since the inductance and capacitance

equivalents are reciprocal, a small inductance provides a low impedance and the corresponding

capacitance value gives a large impedance. This is an excellent approach because it keeps the

conductance matrix constant despite the switch status and only the history source expression

needs to be changed. This author has tried this technique but ran into the problem of choosing the

inductor and capacitor values that would meet appropriate impedance values for the modelling of

H V D C converters. In these cases, the required value of the inductor/capacitor to present an

appropriate low/high impedance requested in values comparable with other impedances in the

system in the system.

In this thesis, the representation of diodes and thyristors as low/high resistances is adopted.

This keeps the number of nodes constant and translates into less programming effort. It maintains

the same network topology during the entire simulation, thus saving the computational time

36

needed to reduce or increase the system matrix when using ideal switches. The H V D C cases

simulated with this model were successfully compared with MicroTran, which also uses ideal

switches to represent semiconductor valves.

The problems that arise in a circuit when modelling G T O thyristors are solved with the

exploratory solution algorithm proposed in section 5.1.

3.1.4.1. Diodes

Fig . 3-6 shows the diode symbol and the parameters included in its model. The diode current

is given by,

iD(0 for the O N state

for the OFF state

anode(A) -

+ "D

cathode (K)

DIODE PARAMETERS R Q N : Resistance value for ON state

Resistance value for OFF state Conductance value for ON state (G0N=1/R0N) Conductance value for OFF state (G0FF=1/R0FF) Holding current Threshold voltage

RoFF: G O N :

GOFF :

V. 'THR-

Fig . 3-6. Diode symbol and model parameters.

( 3 - 5 )

To model the changes of state in the diode, the steps from Table 3-5 are applied at the end of

each step of the solution.

37

1. If diode state is ON and ij)(t) < Holding Current (Ijj) -> change to OFF state 2. Else if diode state is OFF and v£)(t) > Threshold Voltage (VTHR)

change to ON state

Table 3-5. Procedure to check and change the state of a diode.

A s a result, the characteristic of the model is that of F ig . 3-7(a), which is parameter

dependent. The transition when the switch closes is shown in F ig . 3-7(b), and the transition when

it opens is in F ig . 3-7(c).

Not to scale. VTRH=0)

JOFF

(a)

JOFF

(b)

A G O N

IH- A i T / X

/ X * "

| op. point | V D

Fig . 3-7. Diode model: (a) V - I characteristic, (b) Turn on transition, (c) Turn off transition.

38

3.1.4.2. Thyristors

To a certain extent the thyristor and the diode models are similar. The thyristor symbol and

parameters are shown in Fig . 3-8.

Compared to the diode, the thyristor has two more attributes, both of which we need to

include in its model: first, to turn on, a thyristor must have a firing signal applied to its gate

terminal; second, after conduction, a thyristor requires a period of time tq to recombine the

internal charges before operating in the blocking state. I f the device voltage becomes positive

before the internal charges have recombined totally, the thyristor w i l l conduct again with or

without the presence of a firing signal. This event, which may lead to undesired reclosure of a

thyristor, is known as commutation failure.

The extinction angle is a quantity used to measure and prevent the occurrence of a

commutation failure. It is defined as the time interval (converted to electrical degrees) between

the instant that the current crosses zero and the instant at which the thyristor voltage becomes

positive. The algorithm for updating states in a thyristor is presented in Table 3-6 and the

modeled thyristor characteristic is presented in F ig . 3-9.

The calculation of the extinction angle is performed in the computer code. A n integrator is

started when a thyristor opens. I f the time value that the integrator has when the opened

thyristor's voltage becomes positive is smaller than the recombination time tq the thryrisor is

closed again (this is not shown in the characteristic of F ig . 3-9).

39

V

anode (A) gate (G)

cathode (K)

"AK

THYRISTOR PARAMETERS R 0 N : Resistance value for ON state RO F F: Resistance value for OFF state G Q N : Conductance value for ON state (G ON=l/RON) G O F F : Conductance value for OFF state (G OFF= 1 /RO F F) IH: Holding current V T H R : Threshold voltage tq: Minimum recombination time

Fig . 3-8. Thyristor symbol and parameters.

F ig . 3-9. Thyristor characteristic.

1. If thyristor state is ON and ij(t) < Holding Current (I}j) -> change to OFF state

2. Else if thyristor state is OFF and v^(t) > Threshold Voltage (VfHR) > then If a firing signal (ig) is present and the extinction angle >tq change to ON state

Table 3-6. Procedure to check and change the state of a thyristor.

40

3.2. Zero Crossing Detection

The transient solution relies on the integration method, on the time step, and on how closely

the device models reproduce the behaviour of the physical devices.

Diodes and thyristors open at the time instant at which the current crosses zero. Since the

transient simulation is performed at discrete time steps, the exact instant at which the current

becomes zero rarely coincides with an evaluated instant. The detection of a zero crossing event

occurs at the end of the time interval at which the current crossed zero, and the network is not

solved with the switch (diode or thyristor) open until the following time step. This generates a

delay of up to two time steps between the instant at which the switch should have opened and the

instant at which the simulator does open the switch.

Fig . 3-10(a) depicts the traditional procedure for opening a switch when using a fixed time-

step pattern (assuming a null value for the holding current parameter I H). A t point 1, the switch is

at its conducting state. Since the current is positive, the state is not changed. When the current

crosses zero (point 2), the algorithm changes the switch to its off state. However, the solution at

point 2 has already been obtained with the switch closed. It is not until point 3 that the system is

solved with the switch open for the first time during this transition. To avoid numerical

oscillations, it is recommended to use C D A after a switching event. The solution for the opening

of the switch using C D A is illustrated in Fig . 3-10(b).

The closing of a switch has also slight imprecisions. The instant at which the voltage exceeds

the threshold value does not necessarily coincide with an obtained solution. Moreover, when

working with thyristors the origination of a firing signal w i l l probably occur between two

simulation steps, thus delaying the closure of the switch.

41

At At At At rt »r* M »T« »i

current i i i i i

2

(a)

1. switch closed (current is positive -> no action) 2. switch closed (polarity changed detects zero crossing -> switch will open at next At) 3. 1st solution with switch opened 4. solution continues with switch opened until switch voltage becomes positive

At At At/2 At/2 At current ? T" T V T 1

time

(b)

1. switch closed (current is positive -> no action) 2. switch closed (polarity changed detects zero crossing -> switch will open at next At) 3. 1st backward Euler 14 step solution with switch opened (CDA) <- this point is not plotted 4. 2nd bacward Euler Vi step solution 5. solution continues with trapezoidal and switch opened

Fig . 3-10. Switch current for the opening transition in traditional E M T P simulators: (a) Trapezoidal rule for all points (b) C D A algorithm at switching events.

42

A diode voltage for the off-to-on transition of a switch is illustrated in F ig . 3-11 (we assume

a zero value for the threshold voltage V - ^ ) . The diode is open at points 1 and 2. A t point 2,

however, the voltage has become positive, and the diode changes to the on state for point 3.

voltage

time

1. switch opened (voltage is negative -> no action) 2. switch is still opened (positive polarity zero crossing -> switch will close at next At) 3. 1st solution with switch closed 4. solution continues with switch closed until next switching event

Fig . 3-11. Diode voltage during the closing transition with a fixed time-step scheme.

Corrective measures to overcome these slight deviations include the use of a smaller time

step, the application of variable time-step algorithms, and the utilization of interpolation

techniques.

The uncertainties produced by switching operations in the discrete-time domain become

important when modelling thyristors in H V D C and F A C T S devices, as they may produce

43

improper results and lack of control precision. Clear examples and suggestions to diminish their

effects are neatly presented in [4] and [49].

The use of linear interpolation, as presented in [4], brings the solution closer to reality

because the interpolated opening time w i l l be nearer to the actual zero crossing. The solution

output though, is no longer obtained at fixed time steps introducing a dynamic change in the time

intervals.

In F ig . 3-12, the switch is assumed to be originally closed at point 1. I f we use a fixed

simulation time step, we find that the next solution (point 2) is negative. This signals that the

current has crossed zero at some instant in between points 1 and 2. With the solution at these two

points, linear interpolation allows us to find point 3. Point 2 can now be neglected, allowing us to

resume the analysis with the original time step and with the switch open to find point 4, and then

continuing until the next switching event. It is clear from Fig . 3-12 that the solution points are no

longer at fixed time intervals.

44

current At <At At At

.3 4 o

4 5 time

solution is now known at zero crossing

2 (not an output value)

1. switch closed (current is positive -> no action) 2. switch closed (current is negative -> interpolate points 1 & 2 and negelect 2) 3. result from interpolation of points 1 & 2 (switch closed) 4. first solution in this transition with switch opened and original time step 5. solution contines with original time step

Numerical oscillations w i l l most likely arise when a switch opens. To eliminate them,

Kuffel, Kent and Irwin [49] used an extra Vi step interpolation whereas Araujo, Marti and

Dommel [4] opted for the always stable and well proven C D A algorithm [66].

Let us recognize that the methods described above improve the accuracy of the numerical

solutions. Let us also focus our attention to the circumstance that the time intervals are non­

uniform. The non-uniformity of the time intervals can actually be an important issue in real-time

simulators.

A s an example, assume a 50 ps time step. If point 3 in F ig . 3-12 is too close to point 1, say at

only 5 ps, the solution for points 2 and 3 needs to be ready in less than 5 ps. If we had a "super

computer" that was able to solve points 2 and 3 in the required 5 ps, we still would be achieving

Fig . 3-12. Switch current transition with linear interpolation.

45

real-time. What i f the distance between point 1 and 3 were only 1 ps? or 0.5 ps?

or 0.1 ps?or ...?

O f course, it was easy to take the above example to an extreme. There are yet other

consequences emerged as a result of the variable time interval.

A real-time simulator is expected to generate output values. Suppose, for example that the

output device is a simple oscilloscope. The real-time simulator and the oscilloscope need to

establish an intercommunication by an appropriate interface. This communication requires two

important factors: timing and synchronization. Both factors have limitations and implementation

difficulties. If the data exchange between the external device and the real-time simulator is

performed at constant time intervals, the synchronization is made simpler: both devices can work

independently, knowing the time frame that each one has to perform its tasks before the next data

exchange occurs. Other examples of output devices are: an equipment under testing (such as a

controller or a protective relay), an analog simulator, another digital simulator, a real power

system, another computer processing another area of the power system in parallel, etc.

The discussion above has been presented to emphasize both the importance and the benefits

of having a constant interval for output. The solution to this problem (in the zero crossing

detection scheme) is straightforward and only requires an extra linear interpolation or

extrapolation calculation.

Fig . 3-13 annexes points 6 and 7 to the solution presented in Fig . 3-12. In this case, points 4

and 5 are the two backward Euler lA time steps that C D A requires. Point 6 is the final

interpolation or extrapolation to synchronize the solution back to the original time increment.

Point 7 resumes the simulation with the trapezoidal rule of integration.

46

">0

2 • Solid circles are output points at equal intervals • Blank squares are only evaluated and are not output points

1. switch closed (current is positive -> no action) 2. switch closed (current is negative -> interpolate points 1 & 2 and negelect 2) 3. result from interpolation of points 1 & 2 (switch closed) 4. Is1 bacward Euler Vi step solution (first solution with switch open). 5. 2nd backward Euler 'A step solution 6. result from interpolation of points 4 & 5 (resynchronized to original time step) 7. solution continues with original time step and trapezoidal

Fig . 3-13. Diode current with complete interpolation algorithm plus synchronization.

Table 3-7 summarizes the complete algorithm for the detection.of zero crossing 1 and

synchronization with the original time increment.

Fig . 3-14 shows a simulation comparing the proposed interpolation scheme with the solution

when using C D A . The proposed technique does not show spikes at switching events. The plot

corresponds to the current of one thyristor of a three-phase bridge that is feeding a

predominantly inductive load.

If modelling semiconductors, it may be adequate to use the holding current (IH) or threshold voltage (VJHR) parameters as the values for crossing detection. The same interpolation scheme is also valid to improve HVDC controllers accuracy.

47

Solve the network using Trapezoidal New solution is (2)

Previous solution is (1)

-No-

Interpolate new and previous solution (1&2) to find the solution at the zero crossing instant (3)

Change switch state. Enable CDA: 2 backward Euler solutions with

1/2 time-step (4&5)

Interpolate CDA solutions to find the solution at the time corresponding to the original time

increment (6)

(6) is the solution for output (2) is the solution for output

1

increment time step increment time step

Table 3-7. Algorithm for zero crossing detection and synchronization.

48

< Q 1200 CJ J= 1000

e 'I 800

urrr

e <u

urrr

e he

m

600 o 400

o C CO 200 >>

Th

rpol 0

a>-200 e s - 1 - 400

time (s) 0.05 time (s)

Fig . 3-14. Thyristor current in a rectifier: (a) Interpolation scheme II. (b) C D A (MicroTran).

Table 3-8 establishes a comparison of the computational effort between E M T P , C D A

without zero crossing adjustment, the method suggested in [49], and the approach proposed here

(fourth column).

E M T P C D A (MicroTran)

Interpolation scheme I

Interpolation scheme II

Number of solutions 3 Trapezoidal 2 Trapezoidal &

2 B . Euler

5 Trapezoidal 3 Trapezoidal &

2 B . Euler Number of interpolations

0 0 3 2

Numerical oscillations?

yes no no no

Negative current? yes yes no no

Interpolation scheme I: Corresponds to the one presented in [49]. Interpolation scheme II: Corresponds to the one studied in this section.

Table 3-8. Comparison between E M T P , C D A , and interpolation schemes for 3 time steps during a switching action.

49

3.3. The Multi-Area Thevenin Equivalent Algorithm (MATE)

The compensation method used in the E M T P [17], [20] is extended in [62] to subdivide a

network into independent subsystems that can be solved separately. Current injections between

Thevenin equivalents interconnect the subsystems and determine the combined network solution.

The M A T E algorithm is reviewed in Appendix A . Because the methodology is general, it

can be used to subdivide a network at any point and in as many subsystems as desired. One or

more "l inks" are inserted at each point where the network is to be split into two independent

subsystems. For the purposes of the M A T E methodology, the definition of a link is a device that

has two states and is somehow similar to an ideal switch. The link, however, serves as a tie

between two subsystems and is not part of the solution of either one.

With the M A T E concept, equation (3-2) is used to apply nodal analysis to each subnetwork

with all the links in their open state. Finally, the link currents needed to interconnect the

subsystems are obtained from Thevenin equivalents as seen from the link terminals. Using these

equivalents, the link currents are injected into each subsystem to modify all the voltages

accordingly.

Similarly to the transmission line model, M A T E presents the advantage of splitting a circuit

into independent subnetworks. The price is the additional expense of evaluating the link currents

and performing the corresponding current injections. The example of F ig . 3-15 shows how both,

transmission lines and M A T E , divide a system's admittance matrix into decoupled submatrices.

50

A D M I T T A N C E M A T R I X F O R N O D A L A N A L Y S I S

system

: 0 0 0 : y A 2 0 0 i 0

y A 3

C O R R E S P O N D I N G I M P E D A N C E M A T R I X

J system

where

1 system

i-l

-1 Z A 1 i o 0

0 i z A 2 0 0 ; o Z A 3

y A 2 1 A3 _

Fig . 3-15. Network subdivided by links and transmission lines.

General case: M links connecting N areas

If we study with detail the examples presented in Appendix A , we w i l l be able to formulate

the equations directly from the circuit. A s an example, let us generate the equations for the 4-area

7-link system presented in F ig . 3-16. Assume that area 1 has 3 nodes, area 2 has 3 nodes, area 3

has 4 nodes and area 4 has 4 nodes.

51

Area Al (3 nodes)

3»-

LINK-I

LINK-1I

Area A2 (3 nodes) -»-J 1^

LINK-III

LINK-IV

Area A3 (4 nodes)

LINK-VI

LINK-V11

AreaA2 (4 nodes) -• 1

4

Fig . 3-16. Example for the direct formulation of M A T E equations.

If we select two links at a time, we can either have them connecting two or three areas. If the

chosen pair does not connect two consecutive areas, it does not contribute to the solution. This

produces:

^ links ~~

yAl yAl \ yAl yAl 11 II : ^13 + ^12

yAl yAl £ll ^12 0 0 0

yA\ yAl • yAl yAl C l l + ^21 i ^ 2 2 + Z 3 3

yAl yAl £l\ ^11 0 0 0

yAl yAl £\\ *-ll

yAl yAl : yAl yAl £- \ \ + * - \ \ : ^12 + ^13

yAl ^11

yAl ^•11 -zA3

14 yAl yAl yAl yAl • yAl yAl *-ll + ^31 : ^ 2 2 + ^ 3 3

yAl yAl £•11

yAl £-n

0 0 yAl yAl *-l\ ^13 ZA3 + ZA* ZA3 + ZM

£-11 T ^"12 ZA3 + ZM

£-14 T ^13 0 0 yAl yAl

*-ll C l l yAl yA4 ^•11 + ^21

yAl y AA £•11 + ^ 2 2 ZA3 + ZA4

£-li T ^-23 0 0 yAl yAl

^43 yAl yA4 yAl yA4

Z 4 3 + £-11 yAl yAA £ 4 4 + £ »

AE,,,

Ef -Ef2' Ef -Ef

Ef -Ef Ef -Ef Ef -Ef

Ef -Ef

EA3

£ , 4 -Ef\

' ZA]

£ 1 1 yAl £ 1 1 0 0 0 0 0

ZA]

£ 1 1 ZAX

£ 1 1 0 0 0 0 0 yAl £ll

yAl £yi 0 0 0 0 0

yAl £ll -ZA1

£ 1 1 ZA1

£ 1 1 yAl £\2 0 0 0

yAl £i\

yAl £ll ZA1

£ 2 1 yAl £ 2 2 0 0 0

-ZA1

£ 1 1 -ZA1

£ 1 1 yAl £ 1 1

yAl £ll 0 0 0

Z = 0 0

0 0

yAl £i\

-ZA3

£-21

-ZM

£ 1 1

-z" £-21

yAl £ 1 1 yAl £ 2 1

ZA3

£ 1 1 yAl £ 2 1

zA3

£ 1 4 yAl £ 1 4

0 0 -ZA3

£ 1 1 yAl £ll ZA3

£ 1 1 yAl £ll ZA3

£ 1 4

0 0 -ZAi

£ 4 1 -ZA3

£ 4 1 yAl £41

yAl £41

yAl £44

0 0 0 0 -ZM

£-11 £-12 yA4 £ll

0 0 0 0 yA4 C 2 l

yA4 £ 2 2

yA4 £ll

0 0 0 0 -ZAi

£ll -ZM

£yi yA4 £yi

0 0 0 0 yA4 £41

yA4 £41

yA4 £41

( 3 - 6 )

52

This result can be corroborated following the procedure presented in Appendix A , and the

system solution can be obtained from the algorithm presented in Table 3-9.

1. Divide any given network in Mareas Al, A2, ...AM.

2. Interconnect areas with L links with a link as in Fig. A- 3 (from Appendix A).

3. Form admittance matrices Y A 1 , Y A 2 , . . . , Y A M and obtain the corresponding inverse matrices Z A 1 , Z A 2 , . . . , Z A M . Form matrices Z , i n k s and Z by row elimination as for the 2 areas example in Eq. A- 4 and in Eq. A- 5, or by direct inspection.

4. Solve areas separately using Eq. 3-2 with links opened. This produces the Thevenin vector voltage E l i n k s needed in steps 5 and 6.

5. Obtain matrix Z l i n k s and solve for the link currents using Eq. A- 8.

6. Inject vector i l i n k s using Eq. A- 9 to obtain the final solution.

Table 3-9. Generalized M A T E algorithm.

The Mul t i -Area Thevenin Equivalent Algorithm ( M A T E ) is one of the approaches presented

in the next chapter to attempt modelling H V D C converters in real time.

53

4. C H A P T E R 4

H V D C C O N V E R T E R M O D E L S

The large number and frequency of switching operations that take place in power electronic

converters originate numerical difficulties that require supplementary computational effort. In the

previous chapter, the use of C D A and zero crossing detection helped to eliminate the arising

oscillations and reduce the resulting inaccuracies.

To overcome the subsequent increase of computational time, it is necessary to study other

aspects of the solution algorithm that effectively reduce the number of operations.

For example, i f at a certain time step an element's equivalent conductance changes, the

admittance matrix also changes. A s a result, the new solution requires a matrix refactorization or

a matrix inversion. Due to the involved number of multiplications, this is probably one of the

most time consuming tasks during the transient simulation.

One solution to the system matrix recalculation problem is to precalculate and prestore all

possible matrix combinations. This option, however, is not always practical, particularly when

there is a large number of varying elements in the circuit.

The two H V D C models presented in this chapter use the criterion of prestoring the system

matrices. However, the approaches permit the sectionalizing of the network in such a way that

the number of prestored matrices is relatively low.

Before describing the two models, it is worthwhile to gain familiarity with the modelling

requirements of H V D C converters.

54

4.1. The High Voltage Direct Current Substation

The operation of H V D C substations has been extensively studied through the years and the

analytical details can be found in [6], [78]. This section briefly reviews the components in an

H V D C substation and discusses some considerations for electromagnetic transient simulations.

The basic components that make up an H V D C substation are converter bridges, power

transformers, smoothing reactors, and filters. F ig . 4-1 shows the schematic diagram for a typical

monopolar 12-pulse H V D C substation. The filters supply part of the reactive power required by

the converters. In addition, shunt capacitors, synchronous condensers and static V A R systems are

often used as reactive power sources depending on the speed of control desired.

AC system

smoothing reactor

AC filters

Fig . 4-1. Monopolar 12-pulse H V D C substation.

55

4.1.1. Bridges

Each bridge in F ig . 4-1 consists of 6 valves. When the valves in a bridge are arranged as in

Fig . 4-2, it is named a Graetz Bridge. A valve is used to switch in a segment of an A C voltage

waveform. The term valve originates from the mercury arc valves used in the original H V D C

bridges. Nowadays thyristors are grouped in series and parallel to form a thyristor valve.

Commonly, H V D C applications use only series connected thyristors.

Tl T3 Tl T3 T3 T5

T2 symbol

F ig . 4-2. Graetz bridge and symbol.

Bridges control the electrical energy transferred between A C and D C sides by adjusting the

firing angle a at which the valves are fired. The firing angle parameter is normally measured

from the instant at which valve T l is able to be fired (when its voltage crosses zero becoming

positive). In a 6-pulse converter, each subsequent valve is fired at 60° intervals to maintain the

A C system balanced in steady-state operation. For a 12-pulse converter the intervals are spaced

30°. The thyristor numbers in Fig . 4-2 correspond to the firing signals sequence ( T l , T 2 , . . . , T6).

The bridge's operation mode determines the power flow direction. A bridge operating as a

rectifier transfers energy from the A C side to the D C side. The same bridge in inverter mode

transfers energy from the D C side to the A C side.

56

- n n n n -

Tl T3 T5

% % % J T4 | T6 J T2

Fig . 4-3. A 6-pulse H V D C converter feeding a passive load.

However, the A C to D C conversion is far from ideal and harmonics arise on both A C and

D C sides. To illustrate this consider the 6-pulse bridge of F ig . 4-3 operating as a rectifier in

steady-state and feeding a passive load. F ig . 4-4 shows the A C and D C waveforms and the

corresponding Fourier spectrum for a 15° firing angle.

4.1.2. Smoothing reactors

A large reactor installed in series with the bridge output terminals provides D C current

smoothing and protection. This linear reactor is therefore named "smoothing reactor" (the

inductance connected in series with the bridge in Fig . 4-3). F ig . 4-5 shows the smoothed D C

current provided by the smoothing reactor. I f the smoothing reactor was not present, the current

waveform would be equal to the voltage waveform, thus increasing the current ripple.

57

1000

0.21 0.22 0.23 time (s)

0.24 0.25

100

5 7 11 13 17 19 Harmonic number

Fig . 4-4. Rectified D C voltage and A C phase-a current including their corresponding harmonics for the circuit of F ig . 4-3.

1000

800

•g 600 CD u u 3 ° 400 u Q

200

h / w w w w v w w w ^ £ 100

0.21 0.22 0.23 0.24

time (s) 0.25 6 12

Harmonic number

Fig . 4-5. Effect of the smoothing reactor in the D C current.

58

4.1.3. Converter transformers

Three single-phase two-winding units form a three-phase converter transformer. For 12-pulse

operation, two three-phase transformers connected in Y - Y and Y - A feed two series connected

bridges (Fig. 4-6). In both cases the A C side neutral is solidly grounded. Sometimes, single-

phase three-winding transformers or three-phase transformers are used. The transformer's design

should consider D C voltage stresses and D C magnetization due to unsymmetric firing and

increased eddy current losses provoked by high order harmonics. Additionally, the leakage

reactance's design limits short circuit currents.

^ V \ A r / Y Y Y \ .

Tl T3 T5

% % % |T4 |T6 |T2

Tl' T3'

1 \ \

T5'

% * ¥ |T4' IT61 |T2'

Fig . 4-6. A 12-pulse H V D C converter feeding a passive load.

59

o

-a

**-» o u OS

CD 2 3 o >

Total DC voltage

| / Bridge-2 voltage | Bridge-1 voltage

0.225 0.23 0.235 0.24 0.245 0.25

time (s) 12 24

Harmonic number

3000

<j" 1000

100

-300i I.2 0.21 0.22 0.23 0.24 0.25 time (s)

s _ 3 I °< 5 «£ 3 CD S3 '5 i 5 oo O W

80

60

40

20

o

THD=13%

Da JlCL no 11 13 2527

Harmonic number 35 37

2000

0.2 0.21 0.22 0.23 0.24 0.25 time (s) Harmonic number

Fig. 4-7. Operation of the 12-pulse bridge.

60

The 30° phase shift provided by the Y - A transformer allows 12-pulse operation. In this type

of operation the firing is alternated between the two bridges (i.e., T l , T l ' , T2, T 2 ' , etc.). Because

the bridges are connected in series, the sum of the phase-shifted rectified voltages produces a 12-

pulse D C voltage as demonstrated in Fig . 4-7. Also shown in this figure is the benefits in the

harmonic content for 12-pulse operation (compare Fig . 4-4 with F ig . 4-7). Passive filters

installed on both A C and D C sides reduce the effects of the higher order harmonics.

4.1.4. Filters

Filters for A C and D C sides are passive circuits that provide low impedance paths for

harmonics (review the filters location in Fig . 4-1). With an appropriate design and location,

filters confine harmonics to the substation boundaries and avoid their flow to the rest of the

system. Fig . 4-8 shows two filter configurations commonly used in H V D C systems.

Tuned filters eliminate specific harmonics, and high pass filters filter out higher order

harmonics that might exist above the H V D C operational switching frequency. For details on

filter design for H V D C systems please refer to [78].

Fig . 4-9 illustrates the reduced harmonic content in the A C current for the complete 12-pulse

H V D C substation when installing one single tuned filter per phase for the 11 t h harmonic, one

single tuned filter per phase for the 13 t h harmonic, and one second order high pass filter per phase

for higher order harmonics (20 t h and above). The original A C current harmonic distortion factor

(THD) has been reduced from 29.5% for the 6-pulse converter (Fig. 4-4) to 2% for the 12-pulse

converter substation (including transformers and filters, F ig . 4-9).

61

frequency (Hz)

62

4.1.5. Controllers

H V D C systems have the advantage of permitting a fast controllability of transmitted power.

The controls also offer reliable protection during the presence of faults. Modern controllers use

high speed microprocessors for many of the control functions.

In an H V D C link, the rectifier is commonly operated at constant current, and the inverter at

minimum extinction angle. This facilitates the protection against line faults, and produces a

better voltage regulation [78].

The most widely used firing angle control in H V D C converters is the equidistant pulse

control [2], [6], [22], [78]. The controlled variable (dc current or extinction angle) is measured

and compared to a reference set point value (this deviation is named error). The error is applied

to a control amplifier, which generates a corrective order. In many instances, this controller

rectifier is a proportional integral controller. Then a voltage controlled oscillator and a ring

counter alter the firing angle trying to eliminate the error. F ig . 4-10 shows the block diagram of

the equidistant controller scheme.

63

AC system

frequency measurement

Set point from higher level controller

error Uc Voltage controlled oscillator

a

rrrrrr signals to valves

LLLLU -Ring counter

control amplifier limiter

360 Hz filter

Idc

Fig . 4-10. Constant current - equidistant 6-pulse H V D C control.

The controlled oscillator is essentially a pulse generator. It consists of a ramp function with a

frequency proportional to the A C system frequency. When the ramp reaches its peak value, it

generates a pulse that is fed into a ring counter and used to fire the next valve. In steady state

operation, the pulses are equidistant. When an error exists, the reference value of the ramp is

changed (as shown in Fig . 4-11), changing the distance between pulses until a new steady state is

reached.

The firing angle control constitutes only one of the many components of a practical H V D C

controller. It is beyond the scope of this thesis to model a complete controller. To get a panorama

of some controller implementations in digital simulators, the reader is encouraged to consult

references [8], [15], [37], [45], [55], [57], [80], [81], and [102].

64

;atel gate2 gate3 gi ;ate4 gate5 gate6 gatel

pulses to ring counter

(b)

Fig . 4-11. Voltage controlled oscillator: (a) Steady-state, (b) IdOset point -> error>0 and Uc>0.

65

4.2. H V D C Model I - The H V D C Object

In chapter 3 we studied methodologies for the discrete-time solution of electrical circuits and

we reviewed the discrete-time equivalents for the various elements of an H V D C substation. We

also discussed some of the numerical difficulties that power electronics circuits have and

possible solutions.

This section addresses the problem of changing the admittance matrix after a switching

operation and proposes a new way to solve an electrical network containing several H V D C

converters. The strategy for fast solutions is based on both, the precalculation of a certain amount

of matrices, and the appropriate formulation of the system solution. The result is a discrete-time

model for an H V D C converter that produces a noticeable reduction of the computational time

required to solve the network.

In a recent conference in Montreal, Kelper, Dessaint, Do, and Sybille [43] presented a real­

time simulator for a 6-thyristor converter precalculating and storing the 64 possible matrices

resulting from all the possible combinations of the valve states. However, they did not present an

algorithm to allow the inclusion of more than one bridge without including the entire number of

combinations of valve states: 2", where n equals the number of valves.

In the approach proposed in this section, it is possible to store only 64 combinations for each

6-valve bridge, and then combine the bridges to obtain the system solution with simulation times

that are adequate for real-time simulation.

66

4.2.1. The H V D C Object Definition

The first step in this development is to define a subcircuit with elements that are common to

typical H V D C substations. We w i l l name this subcircuit the HVDC Object. It is obvious that

different Object definitions are feasible; the one presented here is only one particular case.

a

/ Y Y or Y A

6-valve bridge smoothing

reactor (optional)

6-valve bridge

—

Fig . 4-12. H V D C Object.

Consider an H V D C Object containing the elements indicated in F ig . 4-12. The Object's core

is the 6-pulse bridge; the transformer can be connected in Y - Y or Y - A , and the smoothing reactor

is optional.

The discrete-time models for each of the elements were detailed in Chapter 3. The bridge

valves are modeled as thyristors, the transformers consist of three single-phase units, and the

smoothing reactor is modeled as an inductance.

To review the different discrete-time models available, please refer to Tables 3-1 and 3-2.

Diodes and thyristors are modeled with a conductance that can have two values. Inductors and

capacitors consist of a fixed conductance in parallel with a history current source. Transformers

and transmission lines have conductance matrices and history source vectors. Although the filters

are not included in the H V D C Object, they can be incorporated without difficulties using the

filter models presented in Tables 3-3 and 3-4. The object in Fig . 4-12 does not contain reactive

67

power sources either; in the case of using S V C s , they can be modeled as proposed in the next

chapter.

The discrete-time equivalent for an H V D C Object developed here has a conductance matrix

(with 64 possibilities) and a history source vector.

Associated with the H V D C Object there are 64 states resulting from all the possible valves'

combinations 2.

A t this point, it is important to emphasize the feasibility and convenience of storing the 64

possible matrices in the computer memory, before the beginning of the transient analysis loop.

Since the Object defined in F ig . 4-12 has only up to 9 nodes, the number of elements in the

Object's conductance matrix for one state is 81. The R A M required to store the 64 combinations

is approximately 20 Kbytes when using double precision.

The H V D C Object of F ig . 4-12 has 5 external nodes that are used as terminals to connect it

to an external network. The number of internal nodes varies from 3 to 5 depending on the

transformer connection and on the presence of the smoothing reactor. A s long as the filters are

modeled as proposed in subsection 3.1.3, the number of nodes is not affected when A C and D C

filters are included in the object.

Each valve has 2 positions (ON and OFF) giving 2̂ combinations.

68

The nodal analysis representation of an electrical network in the discrete-time domain [65] is

of the form:

G v = i - h

( 4 - 1 )

where: G: is the conductance matrix at time / v : is the voltages vector at time / (for both external and internal nodes) I : is the independent current sources vector (the HVDC object does not have any) h : is the history sources vector at time t

The contribution of an H V D C Object based on (4-1 ) can be written as:

G x y - h x "

^ * y x G y y

( 4 - 2 )

The matrix contribution has been partitioned in external and internal nodes (subindex ' x '

denotes external nodes and subindex ' y ' denotes internal nodes).

Assume that at time t the external voltages vx are known. The internal voltages for time t can

be found from (4-2 ) as follows:

( 4 - 3 )

The new state of the valves can now be determined. For each closed valve, zero current

crossing is checked to decide i f that valve needs to be opened for the next solution step. To close

open valves, voltage polarity needs to be positive and a firing signal generated by the converter

69

controller must be present at the gate terminal. The new state determines the Object's matrices

G x x G x y G y x and G y y to be used at time t+At.

The electrical network to which the H V D C Object is connected does not require to know the

internal Object details. For the global solution, each H V D C Object appears as a block with a

discrete-time equivalent consisting of an equivalent conductance matrix G e q and an equivalent

history source vector h e q . Since the object defined in F ig . 4-12 has 5 terminals, G e q and h e q are of

order 5. The discrete-time equivalent seen by the external system is found by obtaining a

relationship between external voltages v x and the equivalent history source vector h e q from the

following procedure.

From (4-2 ) we rewrite the first row

G x , v x + G x y v y = - h x

( 4 - 4 )

Secondly, we substitute ( 4-3 ) in ( 4-4 ) and solve for v x to obtain the discrete-time

equivalent for the H V D C Object:

G e q V x = - h e q

( 4 - 5 )

where:

G e q = G x x _ G x y G y y G y x

h e q = h x " G x y G y y h y

( 4 - 6 )

70

To obtain the complete solution of the network, the elements of the equivalent matrix G e q are

properly inserted in the system's admittance matrix, and the currents of the equivalent history

vector h e q are inserted into the system's currents vector at the nodes corresponding to the

Object's external nodes. F ig . 4-13 illustrates the insertion of G e q into the system's G for a

particular Object state.

HVDC OBJECT MATRICES GI: matrix for status 1 G2: matrix for status 2 G3: matrix for status 3

G63: matrix for status 63 G64: matrix for status 64 v j

Fig . 4-13. Inserting one of the 64 H V D C Object's matrices into the network matrix.

4.2.2. Solution of a Network containing H V D C Objects

A s an archetype, Fig . 4-14 presents a 24-valve system fragmented into 4 H V D C Objects. The

system represents a 12-pulse bipolar H V D C converter substation (the bipolar version of the one

shown in F ig . 4-1). Note that the H V D C Objects do not need to be identical, and that a load has

been inserted at each D C output.

71

The network of F ig . 4-14 can be seen as a 10-node circuit containing 2 load resistances (DC

system), 3 inductances, 3 resistances and 3 voltage sources ( A C system), 3 sets of filters ( A C

filters and D C filters), and 4 H V D C Objects. For this case, the external elements are constant and

only the H V D C Objects may change. The representation of the same network in MicroTran or

E M T P would require a minimum of 31 nodes.

A C S Y S T E M

AC FILTERS

HVDC Object 1 +

•9 c -Y Y

HVDC Object 2 +,

- 9 c -Y A

DC FILTERS

HVDC Object 3 +

- 9 c -Y A

HVDC Object 4 + L J

Y Y

DC FILTERS

D C

S Y S T E M

F ig . 4-14. Four H V D C Objects constituting a 24-valve, 12-pulse bipolar H V D C substation.

The simulator's driver is the main program that integrates the network elements and obtains

the discretized transient solution at fixed time intervals.

To solve a circuit like the one presented in Fig . 4-14, the driver updates the circuit's

conductance matrix at every time step. To do so, at any given time t the driver subtracts each of

the H V D C Objects' matrices that were used to solve the circuit at t-At, and then adds the new

72

H V D C Objects' matrices (based on the updated valves' positions). In addition, C D A is used

when there is a switching operation.

Table 4-1 details the generalized algorithm to solve a network containing one or more

H V D C Objects. Each H V D C Object may be physically and mathematically represented as the

one proposed in the previous subsection. Remember that for each H V D C Object in the network

that we intend to solve, there are 64 matrices (and related submatrices) that need to be stored and

processed before the transient solution starts. Section 4.4 presents simulation results for several

test cases demonstrating the solution times for this algorithm.

This algorithm presents several benefits:

1. Precalculating and prestoring the 64 matrix combinations for each object saves

computational effort during the transient solution.

2. The way in which the algorithm combines the matrices of the circuit Objects presents an

important advantage: " I f a network has n H V D C objects, only 64« matrices are

prestored". A s an example, consider the sending end of a 24-valve H V D C converter. It is

not practical to store the 22 4=16,772,216 combinations that the 24 valves in the converter

give. However, with the new methodology proposed here, i f we define 4 H V D C Objects,

we only need to precalculate and prestore 256 combinations (i.e., 4 Objects x 64

matrices/Obj ect=256).

3. The internal Objects' nodes are not seen by the network simulator, thus reducing the total

number of nodes in the external system and the computational time required. When

attempting real-time simulation, it is important to minimize the number of operations; the

73

number of total nodes is directly related to the size of the system's matrix, and, therefore,

to the computational time required to obtain the solution.

4 . The algorithm can be extended to include other devices, whenever it is feasible to

predetermine the number of possible states and the related matrices.

7 4

For each HVDC Object, precalculate and prestore the Object's matrices

Assume an initial state for each Object

Build the system's cond with all the elements in

HVDC

uctance matrixG-system the system except for the Objects

Start transient analysis t=0

Update the system's matrix G-system by including the active G-matrix of each

HVDC Object

Solve the network at time t

For each HVDC Object, determine the valve positions and the new HVDC Objectstatus

(use the known voltages, obtain currents and check controller firing signals)

Evaluate histories for all the elements in the system

Increment time-step:

t = t + At

** Increment half time-step if there is any switching event (CDA)

Table 4-1. Generalized algorithm to solve a network containing 'n' H V D C Objects.

75

4.3. H V D C Model II - The M A T E Approach

The second model bases its functionality on the Mut i Area Thevenin Equivalent ( M A T E )

algorithm. The theory for M A T E is presented in section 3.3, and in Appendix A .

With M A T E , a network containing H V D C converters can be subdivided into several areas.

The areas are interconnected by the minimum possible number of links. A s in the H V D C Object

model, the areas containing H V D C converters have states that change according to the valves'

states ( O N or OFF) . B y defining an appropriate segmentation of the network, the number of

combinations can be kept reasonable (e.g., 64 combinations per area).

4.3.1. H V D C Converter as an Independent Area

Consider an electrical circuit containing only one 6-pulse H V D C converter. The four links

inserted in F ig . 4-15 divide the circuit into three independent areas: the first area A l contains the

sources and line inductances, the second area A 2 contains the H V D C substation, and the third

area A 3 contains the load. There are three links connecting areas A l and A 2 , and one link

containing areas A 2 and A 3 . For this example, areas A l and A 3 have constant elements, and area

A 2 has 6 valves that cause 64 states.

We can apply the M A T E algorithm with slight adjustments. The main difference with

respect to the M A T E , as introduced in section 3.3, is that at switching events area A 2 changes.

A s a consequence, elements in the links matrix z l i n k s need to be updated at switching events.

76

Area Al Area A2 Area A3

6-valve bridge

r —

Fig . 4-15. Areas for a circuit containing one 6-pulse H V D C converter.

To get an efficient solution using M A T E 3 for this circuit, use the following procedure:

i . For each area containing changing elements, predetermine all the possible combinations

before the transient solutions starts.

i i . Precalculate, preinvert and prestore in memory all the conductance matrices for each

area. The inverted matrices are impedance matrices. For each area A l and A 3 , there is

only one matrix, whereas for area A 2 , there are 64 matrices.

i i i . Assume an initial state for area A 2 (initial conditions) and form the links' impedance

matrix z I i n k s, using elements from the impedance matrix of area A l and from the initial

state's impedance matrix of area A 2 . Factorize Z | j n k s

iv. Start the transient analysis.

v. Solve areas A l and A 2 separately with links open. For area A 2 use the correct state

according to the valves' position. Form Thevenin voltages vector \ l i n k s .

3 Refer to Appendix A for the details of MATE and the corresponding variable definitions.

77

v i . If in step i i i the state o f area A 2 is different from the state in the previous time step, form

and factorize the new links impedance matrix z l i n k s.

v i i . Calculate the links currents vector i , i n k s from Z | i n k s i | i n k s = v, i n k s.

v i i i . Inject vector i , i n k s into areas A l and A 2 and update all the internal voltages in each area.

ix. In area A 2 , determine what switches need to change their position and decide the new

state for area A 2 . This new state w i l l be used for the next time step.

x. If there has been a switching operation, activate C D A (the next two solutions are at lA

time steps and use the backward Euler rule).

x i . Stop here i f the final simulation time has been reached. Otherwise, increase the time step

counter and go to step v.

Regardless of the number of nodes in the system, the order of the system of equations to

solve after a switching event, is equal to the number of links (4 in this case). Compare this with

the system size required to simulate the circuit with MicroTran, where the order of the system is

equal to the number of nodes with unknown voltages (9 nodes).

4.3.2. Multiple H V D C Converters Interconnected by Links

The generalization of M A T E for circuits containing several bridges is straightforward.

Consider the 24-valve system of Fig . 4-16. The circuit corresponds to the bipolar 12-pulse

substation utilized in the previous sections. A s a first attempt we may divide the circuit into 6

areas interconnected by 16 links: the sources and line inductances are grouped in Area A l ; the

78

H V D C substation is split into four areas A 2 , A 3 , A 4 , and A 5 , each one containing a 6-valve

bridge (and therefore 64 combinations); and the last, area A 6 , corresponds to the load resistances.

6-valve bridge

$ 1 Al 6-valve bridge

$ 1 Al

6-valve bridge 1 A5

l

1 A5

A6

Fig . 4-16. A 24-valve H V D C substation divided in 6 areas by 16 links.

We can improve the circuit partition (see F ig . 4-17) by considering some practical issues:

i . In H V D C transmission links, the D C side feeds transmission lines. In this case, the links

on the D C side can be eliminated and the equivalent circuit of the sending (or receiving)

end of the transmission line can be incorporated into the area to which the line is

connected. Remember that the transmission lines already have the property of

subdividing a network in subsystems without the use of the links required by the M A T E

algorithm.

79

i i . If the source side consists of constant elements, the source area can be incorporated into

any of the converter areas. Examples of constant sources are constant Thevenin

equivalents; constant sources in series with constant parameters; or as in the D C side,

transmission lines feeding the A C side.

Applying these considerations, the 24-valve circuit can be subdivided into 4 areas

interconnected by 11 links as shown in Fig . 4-17.

The general algorithm to solve networks containing multiple H V D C converters using M A T E

is detailed in Table 4-2.

Section 4.4 presents test cases to validate this methodology, and makes a comparison with

the results obtained with the H V D C Object model presented before.

80

6-valve bridge 1 A2

|l'

6-valve bridge 1 A2

|l'

Fig . 4-17. The 24-valve system divided in 4 areas by 11 links.

The benefits of this algorithm are:

1. Precalculation, preinversion and prestoring of all the possible combinations for each area

saves computational effort during the transient solution.

2. The order of the system of equations to be solved is equal to the number of links. If the

number o f links is considerably smaller than the number of nodes, there is a considerable

saving in computational effort. (For the 24-valve example, the solution with M A T E was

obtained with 11 links; whereas the entire circuit has 26 nodes).

81

Increment time-step

Inspect the circuit and insert Links to subdivide it in N independent Areas

(try to minimize the number of links)

Determine the number of combinations per Area and precalculate, preinvert and prestore the

corresponding matrices

Form the matrices Z j j ^ and Z

needed in Eqs. A - 8 and A - 9 (from Appendix)

Start transient analysis t=0

Solve Areas independently using Eq. 3-2. This is the Thevenin solution. Calculate vector AE.. ^links'

Update values in matrices

l̂inks a n c ^ ̂ ' a c c o r c u n g to the Areas' states

Solve for links' currents using Eq. A-8: 'links [^linksl ' links

Inject links' currents using Eq. A-9 to obtain all the node voltages: V - Z i | i n k s

For each Area, determine the new valves' positions and the consequent Area state

Table 4-2. Generalized M A T E algorithm for circuits containing 'N' H V D C converters.

82

4.4. Test Cases

This section presents several test cases that confirm the accuracy and solution speed of the

two models and their corresponding methodologies proposed in this thesis (sections 4.2 and 4.3).

The section is divided into two parts. The first part simulates a 12-pulse H V D C converter

substation, and shows the behaviour of the converter in steady-state and under different fault

situations. The second part simulates different H V D C converter configurations and shows

simulation time comparisons.

4.4.1. Simulations for a 12-pulse test system

The 12-pulse H V D C converter of F ig . 4-18 is simulated in steady-state and under the

influence of D C and A C faults. Table 4-3 summarizes the five tested cases for this circuit.

Switches SI and S2 are time controlled. Closure of SI simulates a D C fault, whereas closure

of S2 simulates a single-phase A C fault.

The load is represented by a resistance and a D C source. The value of the D C source is set to

zero for those cases where the converter operates in rectifier mode, and is negative for the

inverter mode. The spikes in the valve currents can be eliminated using the zero crossing

technique presented in section 3.2.

83

Fig . 4-18. 12-pulse test system.

Case Description Operating mode

1 steady-state operation Rectifier

2 dc fault Rectifier

3 single-phase ac fault Rectifier

4 steady-state operation Inverter

5 commutation failure Inverter

Table 4-3. Description of the test cases.

4.4.1.1. Case 1: Steady-state operation

The steady-state operation is shown in Fig . 4-19. The D C current set point is 1600 amperes

and the controller starts operation at 50 milliseconds. The plots include the rectified D C current,

the non-filtered D C voltage (before the filtering action of the smoothing reactor), and the voltage

and current of one valve.

84

2000

<D fc 3 O

U Q

00 c cS 00

> u 00 « "o > u Q

500

0.1 0.2 time (s)

0.3 0.4

> 00

o >

CO

>

200

<* 2000 *—-

1500 E 3 1000

500 > ct) >

""0732

TJ73T

~0734 0736" time (s)

"073T 073S time (s)

0738"

"0738"

TT4

"074

Fig . 4-19. Case 1. Results for steady-state operation.

85

4.4.1.2. Case 2: D C fault

The influence of a D C fault in the test circuit is presented in F ig . 4-20. The fault is simulated

by closing the switch SI in F ig . 4-18 from 0.2 to 0.3 seconds.

The controller limits the current by increasing the firing angle during the fault, thus reducing

the rectified voltage and the fault current. Once the firing angle exceeds 90°, the converter

operates in the inverter mode. This help rapidly reducing the short circuit current to zero.

In F ig . 4-21, the controller has been turned off to show the worst case condition. Note the

constant increase in the current during the duration of the fault. The high short circuit current that

circulates without the controller can cause damage to the converter valves. The controlled current

of Fig . 4-20 has also been plotted in F ig . 4-21 to show the favorable effect of the controller.

86

100 L

0.3 0.4 time (s)

"TX3 04" time (s)

0T3 0.4 time (s)

500

-500. 0.15"

10000

5000

TT25~ time (s)

025 time (s)

Fig . 4-20. Case 2. Results for a D C fault with controller.

87

time (s)

Fig . 4-21. Case 2. Results for a D C fault without controller, and current comparison against the controlled case.

4.4.1.3. Case 3: Single-phase A C fault

A n A C fault is applied to phase-a by closing switch S2 in Fig . 4-18 from 0.2 to 0.3 seconds.

The behaviour of the circuit under the action of the controller is now shown in F ig . 4-22. The

lack of A C voltage produces reduced rectified voltage and current. The controller tries to

compensate by decreasing the firing angle to its minimum value.

88

fc 3 O

U a

00 e 00 c

> <L> 00 CS •*-» o >

U Q

2000

1000

500 L

>

"o > u

_> "to >

c fc

_> CO >

500

-500. 0.15

4000

3000

2000

1000

0°15-

U725-

time (s)

-oi 0^5-^ time (s)

U 3

Fig. 4-22. Case 3. Results for a single-phase A C fault.

89

4.4.1.4. Case 4: Inverter operation in steady-state

To operate as an inverter, the H V D C converter requires a power supply on the D C side to

transfer energy from the D C side to the A C side. The D C source in F ig . 4-18 has a negative value

and the steady-state operation is shown in Fig . 4-23.

The power flow reversal can be found by multiplying the D C current times the D C voltage.

Since the voltage polarity is negative at all times, the power is also negative. A negative value for

the power indicates that the D C side delivers energy to the A C side.

The time interval between the instant at which a valve is turned off, and the instant at which

the same valve voltage becomes positive is the extinction angle y. A s discussed in Chapter 3, the

angle (converted to seconds) needs to be larger than the valve's minimum recombination time tq.

The extinction angle for this operating condition is shown in Fig . 4-23.

4.4.1.5. Case 5: Commutation failure

During the influence of a single-phase A C fault from 0.25 to 0.29 seconds, the inverter

controller tries to compensate for the lack of power transferred by taking the firing angle to the

maximum limit. For an inverter, this corresponds to a minimum extinction angle.

Fig . 4-24 shows the increased D C current during the fault. The higher current and the

increased firing angle reduce the time of the commutating voltage for valve 1, producing a

commutation failure. When this voltage changes polarity, the valve current starts growing, not

permitting the current commutation from valve 1 to valve 3. Note from Fig . 4-24 that during the

fault the extinction angle / i s decreased until the commutation failure arises. F ig . 4-24 also shows

the overlapping angle p, which is the commutation time interval.

90

4000

e c

u Q

ao c OB

>

f O >

Q

03 >

ii _>

>

400 > 60 CS

O >

2 -200

3000

| 2000 3 O

1000

to

0.205 0.21 215 0.22 0.225 time (s)

0.23 ;235

0.205 0.21 0.215 0.22 0.225 0.23 0.235 time (s)

Fig . 4-23. Case 4. Results for inverter operation in steady-state.

91

5000 c ID t 3 O

U Q

oo c 00

>

"o > Q

150

100

500

0.05

0.15 0.2 time (s)

"0TT5 072 time (s)

~07T 0.15 0.2 time (s)

0.25 0.3

500 oo •S

> >

CD v _ '

> -500 0.22

4000

c £ 3 O

"en CD > >

H2B 0.28 time (s)

Fig. 4-24. Case 5. Commutation failure.

92

4.4.2. Simulation times

To compare the simulation times required by different H V D C converter models, the three

configurations shown in Table 4-4 and Fig . 4-25 were run first with MicroTran, and then using

the algorithms proposed earlier in sections 4.2 and 4.3, which are denominated Model I and

Model II, respectively. Model I corresponds to the H V D C Object, and Model II to the use of

M A T E . The platform used for these simulations is an Intel-based personal computer with a

Pentium Pro 200 M H z C P U , and the time step used for all the simulations is 50 ps.

4.4.2.1. Model I and Model II performance

To evaluate the speed performance of the models proposed in sections 4.2 and 4.3, both

approaches were programmed in a power system simulator written in the A D A 95 programming

language.

The bar graph of F ig . 4-26 presents the average computer times per one second of simulation

for the cases presented in Table 4-4 and Fig . 4-25. The timings show the improved performance

of both models over MicroTran. Notice that the advantage of both models over MicroTran

increases as the number of valves grows. Because the best times correspond to Model I, this

model was chosen to be tested in the real-time simulator O V N I , as presented in the next

subsection.

93

Case 1 6-valve monopolar H V D C converter

Case 2 12-valve monopolar H V D C converter

Case 3 24-valve bipolar H V D C converter

Table 4-4. Test cases for simulation times comparisons.

(c)

Fig . 4-25. Test systems: (a) 6-valve monopolar, (b) 12-valve monopolar, (c) 24-valve bipolar.

94

24-valve

12-valve

6-valve

10.99

] 16.22

[J Model I • Model II H MicroTran

43.8

0 10 20 30 40 time per simulated second (in seconds)

50

Fig . 4-26. Solution times for the test cases with A D A 95 and MicroTran (At=50 [is).

4.4.2.2. Simulation in OVNI

Based on the benchmarks obtained for the two proposed models for the H V D C converter, it

was decided to code Model I for the O V N I real-time simulator [68]. This work was performed by

Luis Linares as part of his Ph. D . research work [52]. The results presented next correspond to

the O V N I driver using the backward Euler integration rule. For these tests, the A C network

consisted of a simple Thevenin equivalent (source with impedances). The H V D C converter was

represented in full, as presented in this thesis. The public-domain gcc (C++) compiler of the

G N U toolset of the Free Software Foundation was used to compile the code.

These simulations show the real-time performance of O V N I when simulating circuits

containing H V D C converters modeled as described in section 4.2. These results are consistent

with those obtained when using MicroTran and have been published in [64].

Due to the fact that the number of operations per time step changes during the transient

solution, the associated solution times are different for different time steps. Those time steps

95

involving switching operations require more operations and longer solution times. Real-time

performance is restricted by the solution time required by the time step that takes the longest.

The solution times presented in Table 4-5 and Fig . 4-27 correspond to the longest time step

during the simulation of the test cases of Fig . 4-25. A s indicated, these timings correspond to a

single processor Pentium Pro 200 M H z computer. Even though not yet tested, these timings

should be reduced to about 2/3 with the new Pentium 11-300 M H z machines. This should bring

the timings for the 24-valve case down to the 50 ps real-time performance benchmark.

6-valve 12-valve 24-valve MicroTran (v2.06) 459 983 3120 Model I in O V N I 26 45 81 Ratio: 17.7 21.8 38.5

Table 4-5. Simulation times in microseconds per time step.

a.

3000

2500

2000

1 1500

1000 <D

ex on -a c o 8 500 o

459

26

6-valve

983

45

12-valve

3120

81

24-valve

B Model I in OVNI

• MicroTran

Fig . 4-27. Simulation times per time step (platform: single-processor Pentium Pro 200 M H z ) .

96

C H A P T E R 5

M O D E L L I N G O T H E R F A C T S D E V I C E S

Flexible Alternating Current Transmission System ( F A C T S ) are another important example

of the issue of modelling multiple switching operations. This chapter presents models for F A C T S

devices that include forced-commutated inverters and Static V A R Compensators (SVC) . The

objective again is to support the development of models of power electronic converters for the

O V N I real-time simulator. The first part of this Chapter proposes a general methodology to solve

circuits involving forced commutations. The second part proposes a new model for the Thyristor

Controlled Reactor (TCR) , an essential device in S V C stations.

During this decade, forced-commutated inverters based on Gate Turn Of f (GTO) thyristors

are finding newer and more flexible applications in power systems [53], [70], [77], [105], [108],

[109], [110]. In Chapter One, two applications were already mentioned: the Advanced Static

V A R Compensator ( S T A T C O M ) used for reactive power compensation [21], [29], [46], [92],

and the H V D C inverter used for feeding remote passive loads without local A C generation [1],

[95].

GTOs have similar behaviour to conventional thyristors but they can also be turned off with

a gate signal. Currently there are GTOs with up to 6 k V and 3 k A ratings, as described in [70],

[95], and [105].

S T A T C O M s are the static version of the synchronous condenser, but with the advantages of

improved dynamic capabilities and less maintenance. S T A T C O M s operate on the principle of the

forced commutated voltage source converter (VSC) . They also have the advantage of requiring

lower ratings while occupying less space than conventional S V C s . In H V D C systems,

97

S T A T C O M s are installed at the receiving end to improve the H V D C inverter operation,

especially when feeding weak A C systems. For more details consult references [29], [46], and

[92].

S V C s were first developed in the 1960s but in late 1970s their use has increased dramatically

[28]. S V C s provide leading and lagging current by switching capacitor and reactor banks with

the use of conventional thyristors; detailed theory can be found in [71].

5.1. Forced Commutated Inverters

The basic 6-pulse inverter has 6 GTOs with 6 anti-parallel diodes as shown in Fig . 5-1. The

D C supply can be the output of a rectifier or a charged capacitor. When the current through a

G T O crosses zero, it is instantaneously transferred to the anti-parallel connected diode

constituting natural commutation. The diode either turns off naturally or by turning on the G T O

on the opposite side of the same branch. Forced commutation requires a gate signal applied to the

G T O to turn it off.

+ Vdc

+ Vdc. 2

GTOl

x GT04

n GTo^hn GTO5 1 Dl * ID3 ' 1 D5

1 GT06 1 GT02 Transformers AC

system

'D4 JD6 D2

Fig . 5-1. Basic 6-pulse inverter bridge.

A n alternating voltage is obtained in phase-a by switching G T O l and G T 0 4 , alternatively.

The same applies for the other phases when switching their corresponding semiconductors on

98

and off. F ig . 5-2 depicts the basic inverter concept, and shows the semiconductors that must be

conducting in order to produce such voltages. The inverter controls the A C voltage magnitude

and the harmonic content using pulse width modulation techniques and multilevel configurations

[29], [70], [92], [110]. To prevent the G T O valves from overheating, the carrier frequency is

limited to less than 600 Hz .

*• wt

*• wt

*• wt

Fig . 5-2. Basic inverter output voltage waveforms.

If the inverter is feeding a passive load, electrical energy flows from the D C to the A C side

as in the case of an H V D C transmission system.

If the inverter operates as a reactive power compensator ( S T A T C O M ) , there is no real power

nor reactive power transferred from the D C to the A C side. Hence, the D C supply can be a

relatively small charged capacitor. In a similar way as the synchronous condenser interacts with

an A C system via the synchronous reactance, the reactive power exchange takes place between

the A C inverter's terminals and the A C system via an inductance (e.g., the transformers

inductance).

99

v. GT01 or D1

-*• wt

V...

\ GT04 or D4

GT03 or D3

V.

• wt

GT06 or D6

GT05 or D5

*• wt

\ GT02 or D2

V abf

2V„

V b c *

The S T A T C O M can supply or absorb reactive power by controlling the inverter voltage [29].

If the magnitude of the inverter voltage exceeds the system's voltage magnitude, the inverter

supplies reactive power. I f the system's voltage magnitude is greater than the inverter's voltage,

the inverter absorbs reactive power. The converter controller maintains the inverter's and the

system's voltages in phase.

5.1.1. Exploratory Solution in Circuits with GTOs

The forced commutation of a G T O induces negative voltages in inductors located in the

chopped current's path. In practical power electronic converters, a freewheeling diode provides a

low impedance trajectory for the current. The diode turns on at the exact instant it becomes

positively polarized, and the current is instantaneously transferred from the G T O to the

freewheeling diode.

However, the discrete time nature of the traditional E M T P methodology has difficulties

modelling G T O thyristors. When a G T O opens, its current goes to zero in one time step, causing

numerical problems.

100

Consider the buck regulator of Fig . 5-3. Assume the G T O is conducting current 7/ at time t],

and the diode is blocking. Under this condition, the inductor current equals the G T O current. If at

time t2=ti+At the G T O is forced to open, then its current becomes zero. The inductor voltage at

time t2 is vi(t2)=-U]/At For example, i f Vs=100 V , 7/=10 A , L= 10 m H , and At=50 jus, then

vi(t2)=-2 kV. Since at t2, both the G T O and the diode are open, then iL(t2)=0. The influence of

this large voltage changes the diode to the conducting state for ts=t2+At/2 (if using C D A ) . A t

time t3, however, the inductor history current is zero ( if using C D A ) . Both the inductor and the

diode current become iD(t3)=iL(t3)=-vc(t3)K2^'/^) < 0, forcing the diode to open again for time

t4=t3+At 12. The result is that both the G T O and the diode are opened, and there w i l l not be a

current until the G T O is fired again. The currents and voltages for the described events are

depicted (not to scale) in F ig . 5-4. The half time-step solution at time ts is skipped for plotting in

MicroTran.

+ v c « constant

F ig . 5-3. Buck regulator.

+ v + v,

101

N O T T O S C A L E

E M T P simulators, such as MicroTran, solve this problem by making the G T O and

freewheeling diode work as a pair [18]. The diode is doing the opposite of the G T O . If the G T O

is opened at time 1*2, the diode is forced to close at the same instant «*2, regardless of the diode

operating conditions. This provides a path for the ii(t2) current through the diode, and, therefore,

the inductor current is never forced to be zero. This solution has three disadvantages: first, the

user needs to select those semiconductors working as pairs (this requires some knowledge of the

circuit behaviour; which can be difficult for some complicated circuits involving many GTOs,

diodes, and inductors); second, the diode model is altered so that it works as the G T O ' s pair,

affecting the basic diode fundamentals; finally, the diode is a pair of a specific G T O , not

guarantying an appropriate operation as a freewheeling diode for any other chopped current.

The exploratory solution proposed below provides a solution to the problem of switching off

GTOs. It is easy to program and is used here to simulate circuits with several GTOs and diodes,

such as the inverter of F ig . 5-1. Similar techniques have also been proposed by other authors

[38], [89].

Assume that a G T O firing signal ceases. Before proceeding to the next time-step solution we

can perform an experimental half time-step solution, which we w i l l name an exploratory

solution. This exploration consists of solving the network with the G T O opened. With the

exploratory results, we can decide which diodes need to close due to the high voltages induced in

the inductors, whose currents were chopped. The exploratory solution is then neglected, except

for the new diode positions, and the solution is resumed normally. The exploratory solution

algorithm is summarized in Table 5-1.

103

Y e s -

Save the previous time-step solution.

Solve the network with the GTO opened

(exploration solution)

No

1

Solve the ne trape;

;twork using zoidal

Decide which semiconductors need to open or close, and change the system's matrix accordingly

Restore the saved solution

Output Results Perform 2 half-time step solutions Backward Euler

solutions

Increase time-step

end

Decide which semiconductors

need to open or close, and change the system's matrix

accordingly

Table 5-1. Exploratory solution algorithm for circuits containing G T O thyristors.

104

To visualize how the algorithm works, consider the buck regulator again, and refer to the

plots of F ig . 5-5. Assume that the G T O conducts at time tj. I f at time t2=t]+At, the firing signal

ceases, we perform a one-step exploratory solution. The high negative voltage vi(t2) helps us

decide to close the diode. We then go back to t], and solve for t3=t]+At/2 with the diode closed

(and with the G T O opened). With the diode closed, the inductance current i£ flows through the

diode. Since this current is positive, the diode remains closed at time t4=t2=t3+/S\J2.

Fig . 5-6 compares the solution of the buck regulator with and without the proposed

algorithm, where the benefits of the exploratory solution can be appreciated. I f C D A is used

alone, the inductor current goes to zero when the G T O is switched off, thus impeding the buck

regulator to build up a load voltage.

F ig . 5-7 presents the exploratory solution for the forced commutated inverter circuit of

Fig . 5-1.

105

N O T T O S C A L E

At , At/2 , At/2 , At gto

VL(0

^ •« exploratory solution

At , At/2 , At/2 , At

v3 '4 l 2 5

exploratory solution

At/2 , At/2

Fig . 5-5. Effect o f the exploratory solution algorithm in solution of the buck regulator.

106

i L ( A )

igto(A) 40

20

i D ( A )

v,.(V)

0.4 0.6 0.8

time (ms)

Dashed line (CDA only)

1.2

Solid line (CDA & exploratory solution)

Fig . 5-6. Buck regulator simulations with and without the exploratory solution.

107

2.5

> 3 -1 -

-1.5 -

-2 -

" ' 0 0.01 0.02 0.03 0.04 0.05

time (s)

Fig . 5-7. Forced commutated inverter simulation with the exploratory solution.

5.1.2. Modelling a Forced Commutated Inverter using the H V D C Object

The exploratory solution presented above was adapted to use the H V D C Object of section

4.2 for the simulation of forced commutated inverters.

Consider the anti-parallel connection of G T O l and diode D l from the basic 6-pulse inverter

presented in F ig . 5-1. Both G T O l and D l can be in their open state at the same time, but only

G T O l or D l can close at a specific time. Hence, the combination G T O l - D l has two states (on or

off) and the total number of combinations for the inverter is 64. The difference with respect to

the conventional thyristor bridge is that a valve current can now flow in both directions (either

through a G T O or through the anti-parallel diode).

If the inverter bridge is defined as the H V D C Object, then there are 64 related matrices seen

by the external system as a consequence of the 64 bridge status.

108

The Object's status and the corresponding matrix are selected according to the controller

firing signals. The firing signals are modeled as pulses that are present when a particular valve

has to be in the closed position. A G T O closes i f there is a firing signal and a positive voltage

applied. The G T O opens when the firing signal ceases or when the current crosses zero. When

opening GTOs , one extra exploratory backward Euler solution is performed to check for required

closure of diodes.

The simulation results for the circuit of F ig . 5-8 with modified sinusoidal pulse width

modulation ( M S - P W M ) are shown in F ig . 5-9. The simulation uses the exploratory solution

algorithm, and the inverter as an H V D C Object. The plots show the good performance of the

exploratory solution algorithm under the influence of multiple switching operations.

6-valve GTO inverter

A A / V

A A A r

A A / V

Fig . 5-8. Inverter as an H V D C Object.

109

Advanced Static V A R Compensators ( S T A T C O M s ) use a 12-, 24- and 48-pulse operation to

improve the harmonic content. The 12-pulse S T A T C O M of F ig . 5-10 is now simulated to control

the reactive power direction. F ig . 5-11 shows the 12 pulse operation case when generating and

absorbing reactive power. In [29], Gyugyi et al. described the fundamentals of a 24-pulse

S T A T C O M . In [92], Schauder et al. presented a +100 M V A R S T A T C O M based on a 48-pulse

scheme.

The exploratory solution increases the solution times at those time steps involving forced

commutations. A t the time steps involving the exploratory solution, the implementation of this

algorithm in the A D A - 9 5 driver showed an increase of 50% in the solution time for the 6-pulse

inverter and 63% for the 12-pulse S T A T C O M . A s in Chapter 4, the simulations are performed in

an off-the-shelf Pentium Pro 200 M H z personal computer.

F ig . 5-10. A 12-pulse S T A T C O M .

I l l

inverter voltage system voltage

« 2

o C > 3

40

20

0

20 -40

- \f —. \ V7 TJ leading

M current̂ -

|x /' / k" 1

'"k- - k k ' k

• 1 x ^ 1

/ T

-V / k ' — l v ""1—

0.16

system voltage

0.17 0.18

(a)

0.19 0.2 time (s)

inverter voltage

0.16 0.17 0.18

(b)

Solid line: system voltage — Dashed line: system voltage

0.19 0.2

time (s)

• Dotted line: current

F ig . 5-11. System voltage, inverted voltage, and inverted current for a 12-pulse S T A T C O M : (a) Supplying reactive power (b) Absorbing reactive power.

5.2. Static Var Compensators

A n ideal Static V A R Compensator ( S V C ) provides any required amount of reactive power at

the bus where the compensator is connected. The most common way to achieve this task is to

connect a capacitor bank by means of a Thyristor Switched Capacitor (TSC), in parallel with a

Thyristor Controlled Reactor (TCR) that neutralizes the leading effect of the capacitor bank. A

T C R is a varying inductance obtained by an appropriate change of the thyristors' conduction

angle. F ig . 5-12 shows the basic idea under the S V C .

The nominal power of the T C R inductor normally exceeds that of the capacitor bank to

compensate or overcompensate the capacitor's leading reactive power. The net reactive power is

112

adjusted as needed between the rating of the T S C (leading reactive power) and the combined

effect of the T S C , minus the operating point of the T C R (leading to lagging reactive power).

Fig . 5-12. Ideal S V C .

The circuit in F ig . 5-13 corresponds to a single-phase T C R connected to an ideal source. Let

the voltage source be vs(t) = Vm sin wt volts. If T l and T2 are alternately fired at T/2, 3T/2,

5T/2, 7T/2,..., then full conduction occurs and each thyristor conducts for half a cycle. The

resulting current is sinusoidal with no harmonics. The firing angle ' B ' is 90°.

F ig . 5-13. Single-phase T C R .

A s the firing angle increases, the current is no longer continuous and harmonics arise (see

Fig . 5-14). For /3<90°, an undesired D C component of current appears. N o conduction exists for

13>180°. When the firing angle varies, the apparent inductance changes. The reactive power

absorbed by the T C R changes with the fundamental current variation.

113

Fig . 5-14. T C R current for 13=90°, 120°, and 150°.

F ig . 5-15 shows an S V C and its current-voltage characteristic. The operating point " Q " is

found at the intersection between this characteristic and the system load line. The equivalent

system in F ig . 5-15 consists of a source in series with an impedance j X l . The value for the

inductance that creates the S V C characteristic is obtained by using the fundamental current

through the inductance and neglecting the higher order harmonics. A control circuit determines

the conduction angle required for the T C R . The T S C is either fully connected or fully

disconnected.

*"X TCR at full conduction

leading current lagging current

Fig . 5-15. S V C operating point (combined T S C and T C R ) .

114

The discrete-time equivalent circuit for the single-phase T C R of F ig . 5-13 is shown in Fig . 5-

16a where the conductance and the history current source represent the inductance.

TCR Proposed TCR model

T2 Tl

GL heq CD

Geq

I

(a) (b)

Fig . 5-16. Discrete time equivalent for a single-phase T C R : (a) Normal representation (MicroTran). (b) Proposed model.

In the proposed T C R model of F ig . 5-16b the series connection of thyristors and inductance

are treated as a special inductance that contains a resistance in parallel with a history current

source [19], [23]. U p to this point, the thyristors have been modeled as switches, and the

admittance matrix has been changed at switching events. The thyristors in the proposed model

are not modeled as switches. Instead, the special inductance model senses the thyristors

conduction or blocking condition and adjusts the history term of the inductance's discrete time

equivalent as follows:

i f T l andT2 O F F

i f T l o r T 2 0 N

( 5 - 1 )

115

The T C R model checks for the presence of a firing signal and turns on the history term. The

model then waits for the current to change direction to turn off the history term. This approach

avoids the use of switches and permits having a constant conductance matrix.

A s an example, let us use typical values, e.g., L=10 m H , At=50psec, and a frequency of 60

Hz. The steady-state value of the T C R impedance at full conduction is Z=2Tif L=3.77 Q. In the

discrete-time equivalent, this T C R impedance is the parallel equivalent of the history current

source in the on state and a resistance of value 2L / At =400 Q (trapezoidal rule).

If the thyristors open, the history term is set to zero and the impedance increases from 3.77 Q

to 400 Q. (a factor of more than 100). Since 400 Q is not an infinite impedance, some current

wi l l flow through it. A s the firing angle increases, the ratio between the apparent inductance at 60

H z and the 400 Q resistance decreases, and the error becomes larger. Fortunately, at high firing

angles the effective current is only a small percentage of the nominal reactor current. Moreover,

the error only exists during no-conduction intervals.

Fig . 5-18 shows the simulation results with the new T C R model and with MicroTran for the

single-phase circuit of F ig . 5-17. To evaluate the model accuracy and limitations, the Thevenin

of the system is simplified to a voltage source and an inductance.

116

Fig . 5-17. Single-phase T C R connected to a Thevenin network.

0.02 0.025 0.03 0.035 0.04 0.045 0.05 0.02 0.025 0.03 0.035 0.04 0.045 0.05

time (s) time (s)

Solid line (new model) Dashed line (MicroTran)

Fig . 5-18. Simulations with the new T C R model and with MicroTran for 2 firing angles ( X L » X 1 ) .

A s mentioned earlier, the impedance for the off state is simply the discrete-time equivalent

conductance (At/2L for trapezoidal) with the history term set to zero. To get acceptable results,

the time step needs to be small, and the conductance in the off state needs to be much smaller

than the external impedance. If these conditions are not satisfied, the simulation results do not

accurately represent the T C R behaviour. A simulation with a T C R inductor that is much smaller

than the system impedance is shown in F ig . 5-19. The solution is compared against MicroTran.

117

500

0.02 0,025 0.03 0.035 0.04 0.045 0.05

time (s) Solid line (new method with X1»XR) Dashed line (MicroTran with X1»XR)

Fig . 5-19. Effect of increasing the system inductance.

The effect of increasing the time step by a factor of ten is shown in F ig . 5-20. This plot is

compared to the solution obtained with MicroTran for the same time-step size and with the new

model for a smaller time step.

1.5

1

c 1> I ° o

c4 U -°'5

H -1

0.035 0.04 0.045 0.05

time (s) 1) Broken line (new method: time-step=500 xl0"6s) 2) Solid line (new method: time-step=50 xlO "6 s) 3) Dashed line (MicroTran: time-step=500 xlO "6 s)

Fig . 5-20. Effect of increasing the time step.

In practical situations, there are two factors that allow us to have the conditions under which

the model is accurate. First, electromagnetic transient studies for power electronic devices in

118

power systems require small time steps (100 p or less). Second, T C R are large reactor banks

connected as reactive power compensators and the reactance value is typically several times

larger than the combined system impedance.

The proposed T C R model was validated by simulating the S V C substation shown in Fig . 5-

21. This substation was simulated using MicroTran and also using the proposed new model in

the A D A 95 simulator. The simulated currents and voltages closely match those obtained with

MicroTran, as can be appreciated in F ig . 5-22.

Transformer 239/20/20 kV

250/125/125 MVA

w v

It-

A-connected TCR

A-connected TSC

Y-connected 11th harmonic filter

Y-connected 13th harmonic filter

Y-connected 23th harmonic filter

A-connected TCR

A-connected TSC

AA/V

A A A Y-connected v v ^ 11th harmonic filter

Y-connected 13th harmonic filter

Y-connected 23th harmonic filter ie-

Fig . 5-21. S V C substation at Langdon, Alberta.

119

6000 10,000

0 0.02 0.04 0 06 0.08 0.1 0.12 0.14 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14

time (s) time (s)

time (s) time (s)

— Solid line (new model) Dotted line (MicroTran)

F ig . 5-22. Simulation results for a S V C substation.

120

In the simulation shown, the T C R s are operated with a firing angle equal to 120°, the T S C

are fully connected an the station is supplying reactive power to the power system. The plots

include phase current in the T C R connected in the secondary side of the transformer, the

corresponding line current in the T C R , the total line current in the secondary side which includes

the filter and T S C currents, and the line-to-neutral and line-to-line secondary voltages. A similar

match between the results of this new model and MicroTran was found in the primary and

terciary sides of the substation transformer.

The main benefit o f the proposed T C R model is that the system's matrix is not affected by

the T C R switching, and, as a consequence, the simulation times are considerably diminished.

The simulation times per simulated second for the example presented above are summarized in

Table 5-2.

MicroTran New T C R Model

18.61 8.73

Table 5-2. Simulation time per simulated second-step in seconds for the S V C substation of Fig . 5-21.

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6. C H A P T E R 6

C O N C L U S I O N S A N D R E C O M M E N D A T I O N S

Two approaches to model H V D C converters are proposed in this thesis which permit

considerable reductions in the solution times as compared to traditional E M T P solutions.

The first model, denominated the H V D C Object, presents the best solution times for the

cases tested. The savings in computational time are obtained when all possible equivalent

matrices presented by the Object are precalculated and prestored in the computer memory before

the starting of the transient solution loop. If the H V D C Object contains 6 valves, then the number

of combinations to be prestored is only 64. The use of four H V D C Objects allows the simulation

of a 24-valve converter substation by prestoring only 4x64=256 combinations, instead of trying

to prestore over 16 mil l ion combinations.

If the H V D C Object is programmed as an O O P object, the model's structure allows the

programmer to plug it into O O P electromagnetic transient circuit simulators. This

transportability was demonstrated by programming this model as an A D A 95 object and

connecting it to an electromagnetic transients stand-alone program written in A D A 95. The real­

time performance was demonstrated by M r . Luis Linares in a C++ simulator of the O V N I family.

In addition, M r . Yasushi Fujimoto of Mitsubishi, incorporated the H V D C Object into their

electrical networks' simulator, and successfully tested it for real-time performance on a Cray

supercomputer.

The second H V D C model presented uses the Mult i -Area Thevenin Equivalent algorithm.

This approach also permits the prestoring of the 64 combinations existing in a 6-valve converter.

The network is subdivided by links into independent areas that are solved separately, then the

122

system solution is obtained after calculating the links' currents. Even though the solution times

obtained when programming this model in the A D A 95 circuit simulator were considerably

better than using MicroTran, they were inferior to the timings obtained with the H V D C Object

model.

Both tested approaches include a detailed modelling of the H V D C converter components.

The proposed modelling brings out the advantages of E M T P simulators in providing a highly

efficient and sufficiently accurate representation of semiconductor valves. The individual

modelling of each valve also allows the detailed simulation and analysis of internal bridge faults

(such as commutation failure, misfiring, fire-through, etc.).

Another advantage that both proposed converter models share is that there is no delay

between the system solution and the H V D C converter solution. This is consistent with the E M T P

and O V N I ' s modelling philosophy, and assures an accurate and numerically stable solution

under all system conditions. Other approaches that allow a time step decoupling between

network and converter cannot guarantee high accuracy and robustness under all system

conditions.

The zero crossing detection algorithm proposed in Chapter 3 improves the accuracy of the

simulations when modelling power electronic converters. The program solves the network for the

exact instant at which any semiconductor changes its state. Because it is important for

applications in real-time simulators to have output values at fixed time intervals, this

interpolation scheme includes a resynchronization to the original time increment.

The problems originated by forced commutations of G T O thyristors have been solved with

the exploratory solution algorithm proposed in Chapter 5. Combining this algorithm with the

123

H V D C Object model, it is possible to simulate the behaviour of GTO-based forced commutated

inverters, commonly used in F A C T S applications (inverters feeding passive loads and Advanced

Static Var Compensators - S T A T C O M s ) .

When modelling S V C substations, the T C R antiparallel thyristors' pair in series with the

reactor is combined in an equivalent element with a constant conductance and a varying history

source. This proposed implementation avoids the need to recalculate the system's matrix when

the only switching events are originated by the thyristors.

The following list presents some aspects that I visualize as recommendations for future

developments:

1. The H V D C Object model needs to be interfaced to a generalized digital controller. This

w i l l permit a simulation of H V D C substations with complete control schemes.

2. The problem of a time-step delay between the controller and the network simulation in

the E M T P has not yet been solved. Further research needs to be done to simultaneously

solve the electrical network and the controller equations efficiently without substantially

affecting the computational speed improvements already gained.

3. The zero crossing detection algorithm needs to be combined with the exploratory

solution algorithm. Both algorithms were not tried together. A careful analysis is required

for switching events where both algorithms (an interpolation to find the zero crossing

instant and an exploratory solution) need to be invoked at the same time.

124

4. The models developed in this thesis have been aimed at permitting their implementation

in real-time simulators. In fact, one of the models (the H V D C Object) has already been

coded for real-time performance in a companion Ph. D . project. It is believed that it w i l l

also be possible to implement other F A C T S devices in the context of real-time

simulators. For example, the S V C substation can be programmed as an S V C Object with

the same principles used in the H V D C Object model.

This concludes this thesis work. Hopefully this research can be useful in the future

development of computer modelling of power electronics applications in power systems, and in

particular for the further development of real-time power system simulators.

125

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135

APPENDIX A

T H E M U L T I - A R E A T H E V E N I N E Q U I V A L E N T A L G O R I T H M

This appendix describes the Mult i -Area Thevenin Equivalent ( M A T E ) formulation [62]. The

M A T E concept is based in the hybrid approach for networks solution. M A T E is also used in

O V N I [52] to subdivide a complex network into independent subnetworks interconnected by

links.

A . l Two Areas Interconnected by One Link

Let us illustrate the very simple case of F ig . A - l , where one link divides an electrical

network into two areas A l (n nodes) and A 2 (m nodes), with admittance matrices Y A 1 and Y A 2 ,

respectively.

F ig . A - l . One link dividing a network into two areas.

136

The link terminals are nodes j and k, and from the circuit the link current is:

hink =8lmk(Vj ~ V k )

Eq. A - 1

where gunk is the link conductance. For an ideal link gljnk can be either 0 or co.

The right-hand side vector in the nodal admittance solution of equation (3-2) in Chapter 3

includes all currents, except the link current k . To consistently apply nodal analysis to each

subsystem of F ig . A - l , k needs to be included in the nodal equations as follows:

Link's j-row

Link's k-row

Link's j-column Link's k-column

yAl Ml

yAl yA\ • • -Mil

yA\ 1j\

yA\ '" ii

yAi 0 jf

yA\ ill

yAl "j

yAl mi

1 yAl -Ml

yAl •• Ik

yAl • • 1lm

v,f ViA1

= Jn Jl

0 yAl xkl

yAl •• 1kk

yAl • • Ikm v f J k

yAl i -Sni

yAl Imk

yAl mm JA2

+

-I link

0 0

Uink

Eq. A - 2

137

Combining Eq . A - 1 with Eq . A - 2 we get:

yA\ Ml

yA\ - L\j

yA\ • I\n 0 " V 1 "

yA\ Jj\

yA\ jj

yA\ j» 0 + 1 < J?

yA\ -Mil

yA\ "J

yA\ nn

1 yA2 Ml

yA2 •• 1\k

yA2 • Mm

0

0 n

J A 1 J \

0 yA2 1k\

yA\ •• 1kk

yA2 • 1km - 1 <2 = Jk

yA2 I M«l

yA2 Imk

yA2 mm

0 III J m

0 • Slink 0 0 .. ~ Slink ... 0 - 1 llink 0

Eq. A - 3

In Eq . A - 3, the third partition row corresponds to Eq . A - 1. The final solution is obtained in

two steps. When gljnk = 0, il{ k =0, leaving the first two rows with a decoupled solution. After

obtaining the decoupled solution, we close the l ink 4 by letting g l i n k ->oo. Eq . A - 3 is solved again

in the way described below.

The link current can not be determined from this equation when g,. , -> oo. Its value will be evaluated by other means.

138

Both sides of the first two rows in Eq . A - 3 are premultiplied by the inverse matrices

ZA1=(YA1)"' and ZA2=(YA2)"' respectively, yielding:

Slink ~ Slink

,A\

7A\

7A\ _>y__

7A1 'kk

-z Al mk

~,A2

1

»k

.Al

'link

fz A ' l \ 0 \ 0

0 ; | z A 2 | \ o 0 ; 0 i o

- jA\-

JM JJ Ef

J? 7* E\I2~

jA2 Jk = e- Al

Ek

°m

0 0

Eq. A - 4

where the first two submatrices on the third column contain the j-th and k-th columns of the

inverse matrices Z A 1 and Z A 2 , respectively.

The first two submatrices on the right hand side of Eq . A - 4 are of the form Y' 1 J and contain

the voltages' decoupled solution or Thevenin voltages.

139

Applying row elimination, the first two submatrices on the third row can be expunged,

producing:

yAl z u Ef

1 0 yAl

^Ji

yA\ ^nj

yAl ^lk

< Ef

Ef Ef2

0 1 yAl ^kk

yAl ^mk m

= Ef

Ef

0 0 zM+zA2+ 1

*jj +^kk +

Slink

hink Ef-Ef

Eq. A - 5

Now, i f in Eq . A - 5, gl{ k ->oo we obtain:

hink ~

Ef~Ek

Al Al

y A \ y A l

^jj + Z j k k +

1

hink ~ yAl yAl

Ajj + Akk

Slink

-1

Ef~Ek

yAl yAl ^ ii +^kk

<Al 'Al

Eq. A - 6

Eq. A - 6 may be visualized by the Thevenin equivalents of each area interlaced by the link as

illustrated in F ig . A - 2.

140

Area 1 Thevenin equivalent

l _

Area 2 Thevenin equivalent

Slink ~

0 w h e n o p e n

oo w h e n c l o s e d

Fig . A - 2. Thevenin equivalents interconnected by the link.

Finally, Eq . A - 5 is used to calculate the actual values of the node voltages when the link

current is obtained from Eq. A - 6:

V ~Ef~ yA\

< Ef yAl

CM

Ef yA\

Ef2' yAl A\k

Ef yAl ^kk

K . yAl

m k .

Eq. A - 7

141

The impedances Zf and Zf can be directly found from the impedance matrices Z A 1 and

Z A 2 , and the voltages Ef and Ef from an open circuit solution of the networks. The algorithm

is summarized in Table A - 1 .

1. Divide any given network in 2 areas Al and A2 at any node-i. This will split node-i in 2 nodes. Name resulting nodes: node-j (the one in Al) and node-k (the one in A2). In the final solution the voltages for both nodes must be the same since they represent the same original node-i.

2. Interconnect A1 and A2 with a link as in Eq. A-1.

3. Form admittance matrices Y A 1 and Y A 2 and obtain the corresponding inverse matrices Z A 1

and Z A 2 (of particular interest are the j-th column o / Z A 1 and the k-th column ofZX2).

4. Solve Al and A2 separately using (3-2) with link opened. This produces the Thevenin vector voltages E A 1 andEA2 ofEq. A- 5.

5. Interconnect the Thevenin equivalents to form a circuit as the one in Fig. A- 2. Solve for innk with the link on its closed state using Eq. A- 6.

6. Inject ilink into Al and A2 using Eq. A- 7 to obtain the vectors V A 1 and V A 2 containing the final solution. To verify the result check if vf = vf (this is the voltage of the original node-i).

Table A - 1. M A T E algorithm for two areas connected by one link.

A.2 Generalizing M A T E

To generalize M A T E , an iV-node network can be subdivided into M areas interconnected by

L links as shown in F ig . A - 3. The same algorithm presented in the previous section can be

applied to the general case.

142

Fig. A- 3. An electrical network subdivided by links.

The starting point again is to build a nodal formulation as the one presented in Eq. A- 3, that

can be simplified to equations analogous to Eq. A- 6 and Eq. A- 7. Due to the fact that there are L

links, Eq. A- 7 takes the matrix form:

Minks = ^ links links

Eq. A- 8

where: i, i n k s : L-order vector containig links' currents Z, i n k s : LxL-order links impedance matrix containing appropriate Thevenin impedances AE n n k s : L-order vector containing Thevenin voltages across each link (from the decoupled solution)

143

whereas Eq . A - 7 becomes:

V = E - Z i links

Eq . A - 9

where: V Z E

N-order vector containig all the system's voltages NxL-order impedance matrix containint appropriate Thevenin impedances N-order vector containing Th6venin voltages obtained from the decoupled solution

For completeness, Table 3-9 is repeated here as Table A - 2 , presenting the generalized M A T E

algorithm.

1. Divide any given network in M areas Al, A2, ...AM.

2. Interconnect areas with L links with a link as in Fig. A- 3.

3. Form admittance matrices Y A 1 , Y A 2 , . . . , Y A M and obtain the corresponding inverse matrices Z A 1 , Z A 2 , . . . , Z A M . Form matrices Z | i n k s and Z by row elimination as for the 2 areas example in Eq. A- 4 and in Eq. A- 5, or by direct inspection.

4. Solve areas separately using Equation 3-2 with links opened. This produces the Thevenin vector voltage E h n k s needed in steps 5 and 6.

5. Obtain matrix Z l i n k s and solve for link currents using Eq. A- 8.

6. Inject vector i l i n k s using Eq. A- 9 to obtain the final solution.

Table A - 2. Generalized M A T E algorithm.

144

A.2.1 Two links connecting two areas

Area A l

node-i •-

node-j*-

LINK-1

llinkl

LINK-2

I Unk2

(a)

node-p

-* node-q

Area A 2

Area A l

node-i •-

node-j*-

LINK-1

llinkl

LINK-2

Unk2

(b)

-• node-p

-* node-q

Area A 2

Fig . A - 4. Two areas joined by two links: (a) L ink currents flowing from A l to A 2 . (b) First link current from A l to A 2 , second link current from A 2 to A l .

If we apply M A T E formulation to the circuit o f Fig . A - 4(a), the elements of Eq. A - 8 and

Eq. A - 9 become:

Z = 0

0

7A\ -a 7A\

^ links —

7 A \ + ZA2 7 A \ + ZA1

pq 7 A \ + ZA1 7 A \ + ZA1

A E l i n k s = R A X _ E A 2

I P A2

7A\ Jji 7A2

0

0

0

0

7A1 Jpp 7A2 'IP

7A2 'PI 7A2

0

0

Eq. A - 10

145

The definition of current direction in the links deserves especial attention. For example, i f we

reverse the current direction of one link, some elements in Eq . A - 10 must change sign. For the

current direction shown on Fig . A - 4(b) the changes in signs give:

Z„ links

Ci\ + ^pp 7 A \ 7A2

^ij ^Pl 7 A \ 7A2

Cj> ^Pl 7 A \ , 7 A l ^ii + Zjqq

AE links

A2

- EM + EA1

Z = 0

0

r/fl

- z , A\

rAX

-z A2 + zf

pp _ 7A2

^qp

+ ZA2

pq _ 7A2

^qq

0

0

Eq . A - 11

146

A.2.2 Two links connecting three areas

Area A l

node-i •-LINK-1

link!

Area A 2

-• node-p node-q *-LINK-2

llink2

Fig . A - 5. Three systems connected by two links.

For F ig . A - 5, the new set of equations is:

'links

Z = 0

ZM +ZA1 -z A2

II PP PI

- z A2

Z A 1 + Z L IP

Ef •"links —

£A2 p

-Ef_ 1

p

-Ef_

_ Z A 2 _ Z A 2

PP qp yA2

PI qq

rAl

Area A3

-• node-x

-Z A3

Eq. A - 12

Again, reversal of the current of any link changes the signs of some elements. In Chapter 3

section 3.3 presents an example of how to use this section to generalize M A T E .

147

A P P E N D I X B

T R A N S F O R M E R D I S C R E T E - T I M E E Q U I V A L E N T

This appendix presents the derivation of the discrete-time equivalent for a two-winding,

single-phase transformer using the trapezoidal integration rule [63]. The discrete-time

equivalents for multiphase, multi-winding transformers can be easily obtained using these

concepts. The use of a different rule of integration is also straightforward.

n=Nl/N2

Fig . B - 1. Two-winding single-phase transformer with leakage inductance Lt .

For the two-winding single-phase transformer shown in F ig . B - 1, using Kirchhof f s Voltage

law, we can write:

di. v,(t) = Lt-^ + nv2

Lt di2

nv2(t) = — -TT+v, n dt

Eq. B - 1

expressed in matrix form,

1 ' 1 -n ~vxdt~

di2 ~ Lt - n n \ v2dt

Eq. B - 2

148

Using the trapezoidal rule to discretize Eq . B - 2,

i"i(0- ' i ( ' - At) At ' 1 -n v,(0 + v,( / -At)

*2 C O - i2(t- At) ~ 2Lt -n n2 _v2(t) + v2(t -At)

Eq. B - 3

Equation Eq . B - 3 is now rearranged:

w . '2<0. _G 2 , G22

v , (0

v 2 ( 0

A(o" h2(o

G l l G12 "v,(r-A/)" _i_ "/,(/- AO" — 9 "G„ G 1 2 " v , ( f - A 0 " _l_ ~hx(t-At) G 2 1 G 2 2 _ _v2(/-A/)_ i i2(t-At) — z, . G 2. G 2 2 _ _ v 2 ( r - A 0 . 1 h2 {t - At)

Eq. B - 4

where:

A M _ _ ( A M 2 f A M . . . . JVI Gu=V2LtJ' ° n = ° 2 ] =~" V2Lt)' ° 1 2 = n VHJJ' and «: is the transformer ratio ^ 2

Eq. B - 4 can be rewritten in compact form:

i(t) = [G]v(t) + h(t)

h(t) = 2 [G] v(t - AO + h(t - AO

Eq. B - 5

149