MGPA design review architecture overview and specifications detailed architecture

January, 2003 CMS Ecal MGPA Design Review 1

MGPA design review

architecture overview and specificationsdetailed architecture

•top level functional block diagram•CSA stage•VI stage•Differential O/P stage•CAL circuit

noise: sources and simulationsprocess simulations – whole circuit (including power supply – 10%, temperature variations)

•linearity•pulse shape matching•gain•noise

I/P interface•input APD, VPT (transmission line effects)

power and PSRmiscellaneous issues: bond lead inductance, protection, layoutspecifications reviewoutstanding issues


MGPA specifications

Parameter Barrel End-Cap

fullscale signal 60 pC 16 pC

noise level [electrons] 10,000 electrons 3,500 electrons

noise level [C] 1.6 fC 0.56 fC

input capacitance ~ 200 pF ~ 50 pF

output signals to match ADC differential 1.8 V, +/- 0.45 V around Vcm = (Vdd-Vss)/2 = 1.25 V

gain ranges 1, 6, 12

gain tolerance (each range) +/- 10 %

linearity (each range) 0.1 % fullscale

pulse shaping (impulse response) 40 nsec CR-RC

channel/channel pulse shape matching

< 1 %

Vpk

Vpk-25ns

Vpk-25ns/Vpk matches to 1%across gain ranges


externalcomponentsdefine CRand CSA gain

externalcomponentsdefine RC

V/I gainresistors

offset &CAL pulsegeneration

I2Cinterface

offsetadjust

MGPA – architecture overview

diff. O/P


CSA I/P stage

conventional folded cascodemaximise use of available dynamic range resistor to VDD -> I/P device Vs ~ 1V => I/P and O/P as close as poss. to VSS note output -> PMOS source followers with ~0.5V VGSext. components define gain and O/P decay time (40 ns) choose to suit barrel/endcap Cpf/Rpf = 33pF/1.3k (barrel) or 10pf/4k (endcap) => max signal accommodated (~ 1V) with min. pile-upinput device dimensions big gm needed for low O/P risetime (Cdet~200pF) 30,000/0.36 -> Cgs ~60 pF, gm~.3A/Vbias current magnitudes (externally defined) for big I/P device gm (see above) slew rate at output nodebias transistor dimensions avoid minimum length keep gm low (noise) but need low Vdsat


CSA O/P simulation (barrel case)

nominal process parameters

Cpf/Rpf = 33pF/1.2k

input capacitance 200 pF

signal injected at 25 ns

0 -> 60 pC in 2pC steps 10 ns arrival time to simulate scintillation decay time

resulting pulse peaks at 47 ns (22ns injection -> pk)

~ 1.1 Volt max amplitude swing


CSA O/P simulation (end-cap case)

Cpf/Rpf = 10pF/4k

input capacitance 50 pF

signal injected at 25 ns

0 -> 16 pC in 1pC steps 10 ns arrival time to simulate scintillation decay time

resulting pulse peaks at 48 ns => 23ns injection -> pk

~ 1.0 Volt max amplitude swing

CSA O/P pulse shape ~ independent of whether barrel or endcap


VI stage design choices governed by:

linearity, noise considerations, supply current requirements (not excessive),need to produce current output (high O/P impedance)to drive diff. O/P stage

Rgain gives good linearity acceptable noise (later)

s.f. and cascode currents all derived from one current sourcecascode gate voltage derived from preamp I/P ensures minimum DC voltage across Rgains.f. and cascode widths and drain currents for large gm (note Rgain values relatively small) IDS different for different gain stages chosen to get linearity within spec. trade-off linearity/power

range Rgain [ohms] Ibias [mA]

high 17 22

mid 41 16

low 240 9

RC coupled(external)


VI stage simulation waveforms

(nominal process parameters)

low gain channel

signal: 0 -> 60 pC in 6 pC steps

source follower O/P

cascode I/P

cascode O/P

1.1V

2.2V


ADC I/P signal range: +/- 0.45 V around Vcm (1.25V)

O/P RC termination sets shaping time const. 200 ohms compromise between “low-ish” O/P impedance and DC quiescent current

40 nsec requires 100 pF differential (2.5 pF/nsec) or 200 pF each O/P to Vcm (5 pF/nsec)

programmable offset adjust to each channel

Differential O/P stage

single ended current in -> differential current out


Lowest gain channel – differential O/P stage signals

signals: 0 – 60 pC, 2 pC steps

VCM = 1.25 V


Higher gain channels – saturation effects (still 0 – 60 pC, 2 pC steps)

highest gain range middle gain range


MGPA output: (out+) – (out-)

0 – 60 pC, 2 pC steps

highest (red) and mid (blue) gain ranges saturatelowest (green) well-behaved


CAL circuit


CAL circuit simulation

10pF

1nF

DAC valuee.g. 100mV

MGPA I/P

10k RtcRtc:0 ->10

Highest gain channel O/P for 1 pC input signal

Can use Rtc to simulate real signal risetime

external components


Noise

CIN

vFET2

vRpf2

Rpf

charge amp.

s.f. RG

diff. O/P gain stage

Cpf

VCM

CI

RI

transconductancegain stage

ENC due to charge amp. noise sources:

Rpf : note: Rpf constrained by Cpf (RpfCpf= = 2RICI = 40 nsec. )

-> 4900 electrons (barrel)-> 2700 electrons (endcap)

I/P FET: (CTOT = CIN + CFET + Cpf)

-> 1800 electrons (barrel, CIN=300pF (200 + 60 + 40))-> 660 electrons (endcap, CIN=112pF (40 + 60 + 12))

=>no strong dependence on CIN

K1 Rpf

1/2

K2vFETCTOT

1/2

iCFET2

iRG2


Noise

CIN

vFET2

vRpf2

Rpf

charge amp.

s.f. RG

diff. O/P gain stage

Cpf

VCM

CI

RI

transconductancegain stage

ENC due to transconductance stage sources:

RG -> Cpf dependence because relative magnitude depends on charge amp gain. Keep RG as small as poss. but has to vary for different gain stages

Cascode FET -> Cpf and RG dependence

V/I stage noise sources become more important for lower gains (bigger RG)

iCFET2

iRG2

RG

1/2K3Cpf

gm

1/2K4CpfRG


Simulated noise dependence on gain

these results are for final gain range spec. (1, 6, 12), nominal process parameters and VDD, Tgain resistor noise dominates for lowest gain rangenumbers in red exceed 10,000 (3500) but signal size means relative contribution to overallenergy resolution less significant (see http://www.hep.ph.ic.ac.uk/~dmray/pptfiles/Ecalprog2.ppt)

Gain RG signal range (barrel) [pC]

Noise (barrel) [electrons]

signal range (endcap) [pC]

Noise (endcap) [electrons]

12 14 0 – 5 6200 0 – 1.33 2700

6 34 5 – 10 8200 1.33 – 2.67 3073

1 240 10 - 60 35,400 2.67 – 16 9800


Process and environment simulations

Process parameters: sigma (length,VT): 0, +/- 1.5np mismatch: nom, +/- 3 sigma values

Supply Voltage: (+/- 5%) 2.375, 2.5, 2.625(not yet done)

Temperature: -10, 25, 75

simulation results here for 1, 5, 10 gain ratios (not latest 1, 6, 12)

simulations:

transient: signals: 0 -> fullscale in 10 steps, for each gain range look at:

linearity |linearity|< 0.1% fullscale

pulse shape matching V[pk-25ns]/V[pk] matches to 1% for all signals within gain rangesacross gain ranges

noise & gain


simulation example

signals: 0 -> ~ fullscale in 10 steps for all 3 gain ranges

for a given set of process parameters andenvironment variables (VDD, T) look for:

linearity within gain ranges (+/- 0.1% fullscale)6 pC, 12 pC, 60 pC

pulse shape matching for all sizes of signals within gain ranges and across gain ranges (+/- 1%)


Linearity results: VDD = 2.5V, T=25

Linearity definition:

peak pulse ht. – fit (to pk pulse ht) X100 fullscale signal

results here for:

sigma = -1.5, 0, 1.5np mismatch = -1, 0, 1

27 curves: 9 for each gain range


Linearity results: VDD = 2.375V (- 5%), T=25

results here for:

sigma np mismatch

0 0-1.5 -1+1.5 -1-1.5 +1+1.5 +1



Linearity results: VDD = 2.375V (- 5%), T=75

results here for:

sigma np mismatch

-1.5 -1+1.5 -1-1.5 +1+1.5 +1



Linearity results: VDD = 2.375V (- 5%), T=-10

results here for:

sigma np mismatch

-1.5 -1+1.5 -1-1.5 +1+1.5 +1



Pulse shape matching results: VDD = 2.5V, T=25

Pulse shape matching definition:

Pulse Shape Matching Factor

PSMF=V(pk-25ns)/V(pk)

Ave.PSMF = average for all signal sizes and gain ranges, for a particular set of process parameters

Pulse shape matching =

[(PSMF-Ave.PSMF)/Ave.PSMF] X 100

results here for:

sigma = -1.5, 0, 1.5np mismatch = -1, 0, 1



Pulse shape matching results: VDD = 2.375V (- 5%), T=25

results here for:

sigma np mismatch

0 0-1.5 -1+1.5 -1-1.5 +1+1.5 +1



Pulse shape matching results: VDD = 2.375V (- 5%), T=75

results here for:

sigma np mismatch

-1.5 -1+1.5 -1-1.5 +1+1.5 +1



Pulse shape matching results: VDD = 2.375V (- 5%), T=-10

results here for:

sigma np mismatch

-1.5 -1+1.5 -1-1.5 +1+1.5 +1



gain dependence on process params

histogram peak pulse heights for fullscale (6 pC) signal for highest gainrange

other gain ranges behave similarly

VDD=2.5V, T=25

VDD=2.375V, T=25

VDD=2.375V, T=75

VDD=2.375V, T= -10

peak pulse height for 6 pC signal [V]


histogram noise dependence on process params, VDD &T


End-cap VPT interface

coax

CdetI(t)MGPA

CSA O/P

chip O/P

I(t) current source with 10 ns decay time

Cdet = 5 pF (2 pF + stray)

coax = RG 179 (thin 50 ohm) 75 cm long

some ringing observable at CSA O/P

smoothed out at chip O/P


Barrel APD interface

coax

CdetI(t)MGPA

CSA O/P

chip O/P

I(t) current source with 10 ns decay time

Cdet = 160 pF (2 APDs)

coax = RG 179 (thin 50 ohm) – 30 cm long

some ringing observable at CSA O/P

once again smoothed out at chip O/P

would be better to have more accurate interconnectionmodel


Power consumption @ 2.5 V

Stage current [mA] bias cct no. power[mW]

CSA 40 4 1 110

High gain VI 44 2.2 1 116Mid-gain VI 32 1.6 1 84Low gain VI 18 0.9 1 47

Diff O/P 18 1.5 3 146

Total 503


PSR rejection - preliminary

0 dB

-20 dB

-40 dB

-60 dB

1 100 10k 1M

swept frequency sine-wave superimposedon VDD

resulting output on high gain channel O/P[(out+) – (out-)]

high frequency rejection due to RC filteringof power rail (RC = 1 x 10F)

some rejection at DC but gain at ~ 100 Hz

Hz


PSR rejection improvement

0 dB

-20 dB

-40 dB

-60 dB

1 100 10k 1M

replace “resistor to rail” biasing by ideal currentsources (CSA and VI stages)

100 Hz “bump” removed

DC rejection the same

more detailed study needed here – hope forfurther improvement

Hz


Any effect of bond-wire inductance? model by inserting inductances between external decoupling and internal circuit nodes

L=0,2,4,6 nH

high gain rangesignal = 5 pC

effect just visible

no sig. effectson performance


Conceptual layout

80 pin package – may -> 100

CAL circuit included

spare pins available for I2C test & reset extra power

segmented approach minimise crosstalk between different gain stages

multiple power pads

all bias lines decoupled

diff. O/Ps separated layout (chip and hybrid) needs care different stray capacitance -> different pulse shapes/gain range)

internal gain resistor +/- 10 % tolerance


MGPA specifications review

Parameter Barrel End-Cap

fullscale signal 60 pC 16 pC

noise level [electrons] 10,000 electrons 3,500 electrons

noise level [C] 1.6 fC 0.56 fC

input capacitance ~ 200 pF ~ 50 pF

output signals differential 1.8 V, +/- 0.45 V around Vcm = (Vdd-Vss)/2 = 1.25 V

gain ranges 1, 6, 12

gain tolerance (each range) +/- 10 %

linearity (each range) +/- 0.1 % fullscale

pulse shaping (filtering) 40 nsec CR-RC

channel/channel pulse shape matching

< 1 %

technology spec. for resistors used

need to tweak

OK for mid and high gain ranges(low gain not a problem)

OK

OK


Outstanding issues

tweak the gain resistor values (trivial - don’t expect any adverse consequences)

choose CAL circuit DAC resistor values (trivial)

PSR – could adjust CSA, VI stage bias cctry to improve (needs some thought)needs to be supply independent – use bandgap or VT referenced current sources

(existing designs)

channel offset generationmake supply independent

check O/P stage in conjunction with ADC I/P stage (should be done)

MGPA design review architecture overview and specifications detailed architecture

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