MGPA test results first results presented 25 th June – repeat here + some new results

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9th July, 2003 CMS Ecal MGPA test results 1 A test results t results presented 25 th June – repeat here + some new results ing begun 29 th May on bare die (packaging still underway) chips looked at so far – both working (all results here from one only) INE introduction test setup description analogue performance gain linearity matching noise (barrel and endcap) 5 Mrads irradiation results I2C offset adjust calibration feature power consumption summary

description

MGPA test results first results presented 25 th June – repeat here + some new results testing begun 29 th May on bare die (packaging still underway) two chips looked at so far – both working (all results here from one only) OUTLINE introduction test setup description - PowerPoint PPT Presentation

Transcript of MGPA test results first results presented 25 th June – repeat here + some new results

Page 1: MGPA test results first results presented 25 th  June – repeat here  + some new results

9th July, 2003 CMS Ecal MGPA test results 1

MGPA test results

first results presented 25th June – repeat here + some new results

testing begun 29th May on bare die (packaging still underway)

two chips looked at so far – both working (all results here from one only)

OUTLINE

introduction test setup description analogue performance

gainlinearitymatching

noise (barrel and endcap)5 Mrads irradiation results

I2C offset adjust calibration feature power consumption summary

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MGPA target specifications

Parameter Barrel End-Cap

fullscale signal 60 pC 16 pC

noise level 10,000e (1.6 fC) 3,500e (0.56 fC)

input capacitance ~ 200 pF ~ 50 pF

output signals(to match multi-channel ADC)

differential 1.8 V, +/- 0.45 V around Vcm = (Vdd-Vss)/2 = 1.25 V

gain ranges 1, 6, 12

gain tolerance (each range) +/- 10 %

linearity (each range) +/- 0.1 % fullscale

pulse shaping (filtering) 40 nsec CR-RC

channel/channel pulse shape matching

< 1 %

technology spec. for resistors used

OK for mid and high gain ranges(low gain not a problem)

OK

OK

simulation results

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Rf

charge amp.

RG1

diff. O/P stages

Cf

VCM

CI

RI

transconductancegain stages

RI

DAC

I2C andoffset

generator

ext.trig.

MGPA main features

3 gain channels 1:6:12

differential outputs -> multi-chan. ADC

pulse shaping (external components) RfCf = 2RICI = 40 nsec.

choose RfCf for barrel/endcap

calibration facility prog. amplitude (simple DAC) needs external trigger

I2C interface to programme: output pedestal levels enable calibration feature cal DAC setting

CCAL

RG2

RG3I/P

VCM

CI

RI

RI

VCM

CI

RI

RI

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MGPA photo

die size ~ 4mm x 4mm

for packaging in 100 pin TQFPI2C

charge amp

VI stage

diff. O/P stage

offset gen.

hi

mid

lo

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RAL test board

packaged chips not yet available but RAL boardcan take bare die

dual purpose design 1) standalone–used here 2) interface to standard DAQ system

bias components fixed – no adjustment possible (without changing 0402 components)

most results here for barrelfeedback components to first stage (except whereindicated)

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Test setup for pulse shape measurements

diff. probe or single-ended buffered signal

note: very fast risetime charge injection -> pulse shape distortion on rising edge due to slew rate limitation at O/P of first stagecurrent source magnitude OK for 10 nsec exponential edge

Scope averaging -> 16 bit resolution. Multiple waveforms captured with different DC offsets to remove scope INL effects.

I/P

O/P

first stageamplifier

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Pulse shapes – low gain channel

signals up to 60 pC (feedback components for barrelapplication: 1.2k//33pF)

steps not equally spaced (log attenuator)

2 active probes on +ve and –ve outputs (before anybuffering)

linear range +/- 0.45 V around Vcm (1.25 V nom.)

note: Vcm defined by external pot’l divider (5% resistors)so not exactly 1.25 V

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Pulse shapes – all 3 gain ranges

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Differential pulse shape – low gain channel

differential probe on chip outputs (before buffering)

60 pC fullscale signal as before

differential swing +/- 0.45 V around Vcm corresponds to ~1.8 Volt linear range

pedestal subtracted

no “obvious” pulse shape distortion due to higher gainchannels saturating

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Differential pulse shapes – all 3 gain channels compared – gain ratios 1 : 5.6 : 11.3 (cf 1 : 6 : 12)

no obvious interchanneldistortion effects

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Linearity and pulse shape matching – high gain channel

fullscale signal 5.4 pC

pulse shape matching in spec., linearity outside by factor ~2

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Linearity and pulse shape matching – mid gain channel

smallest signals show slower risetime – needs further investigation

fullscale signal 10.8 pC

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Linearity and pulse shape matching – low gain channel

similar (but worse) effect as for mid-gain channel

fullscale signal 61 pC

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Pulse shape matching between gain channels

Pulse shape matching definition:

Pulse Shape Matching Factor PSMF=V(pk-25ns)/V(pk)

Pulse shape matching = [(PSMF-Ave.PSMF)/Ave.PSMF] X 100

Ave.PSMF = average for all signal sizes and gain ranges

systematic discrepancies between channels can be due to mismatch in diff. O/P termination components or (more likely here) difference in stray capacitance from PCB layout

spec.

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1st stage of buffering

differential O/P termination components(1% tolerance)

mismatch of stray O/P capacitancelikely due to signal routing on test card

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effect of input capacitance on pulse shape

pulse peak shifts by only ~ 3 nsec. => robust to variations in stray capacitance

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Barrel (33 pF // 1.2k) Endcap (8.2 pF // 4k7)

Cstray(~20 pF)

Cstray+ 180 pF

simulation200 pF

Cstray(~20 pF)

Cstray+ 56 pF

simulation50 pF

high 7,000 7,850 6,200 2,900 3,050 2,700

mid 8,250 9,100 8,200 3,300 3,450 3,073

low ~ 28,000 ~ 28,000 35,400 ~ 8,500 ~ 8,500 9,800

Noise measurements

use wide bandwidth true rms meter (single ended I/P)

=> need diff. to singled ended buffer circuitry

=> extra noise contribution to subtract

will also add extra noise filtering

weak dependence on input capacitance as expected

estimated errors: ~ 10% high and mid-gain ranges, ~ 20% low gain range (buffer circuitry dominates here)

endcap results NEW

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10 keV X-rays (spectrum peak) , dosimetry accurate to ~ 10%, doserate ~ 1 Mrad/hour, no anneal as yet

~ ½ fullscale signal injected for each gain channel

~ 3% reduction in gain after 5 Mrads

low mid high

pre-rad5 Mrads

Radiation results: pulse shape

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Radiation results: noise

Cstray+ 180 pF

Cstray+ 180pF+5 Mrads

simulation(200 pF)

high 7,850 7,250 6,200

mid 9,100 8,700 8,200

low ~28,000 ~32,000 35,400

no significant change (within errors) after irradiation

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Radiation results: linearity & pulse shape matching

high gain channel shown here linearity degraded slightly at extreme edge of range

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I2C offset setting 0

I2C offset setting 105

linearrange

I2C pedestal offset adjustment

high gain channel shown here(other channels similar)

offset setting 0 -> 105 in steps of 5 (decimal)

~ optimum baseline setting herecorresponds to I2C setting ~70

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Calibration circuit functionality (1)

10pF

1nF8 – bitDAC value0 – 2.5 V

MGPA I/P

10k

Rtc

on-chipexternal

derived fromexternal pulse

high

mid low

distortion on risingedge for low gainchannel – somehowrelated to external 1 nF cap.

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Calibration circuit functionality (2)

10pF

1nF8 – bitDAC value0 – 2.5 V

MGPA I/P

10k

Rtc

on-chipexternal

with 1 nF without 1 nF

calibration pulse shapes with/withoutexternal 1 nF show improvement ifremoved

effect needs further investigation

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main concern so far:

high frequency instability (~ 250 MHz) can be introduced on first stage O/P when probing

not clear whether problem on chip (no hint during simulation)

or could be test board related decoupling components around first stage not as close in as would like

VDDP, VS in particular

test board for packaged chips should help withdiagnosis decoupling closer in (may be cure?) bias currents easy to vary (should give clues)

new version of this board also in pipeline will also take test socket

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Power consumption

Current measured in 2.5 V rail supplying test board -> ~ 245 mA

-> chip current + Vcm divider (4mA) + power LED (3mA)

chip current = 238 mA

measuring bias currents and multiplying by mirroring ratios -> 235 mA

may change if further testing indicates changing bias conditions -> performance improvements worth having

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Summary

all results so far for one unpackaged chip, barrel feedback components to first stage

gains close to specification (1 : 5.6 : 11.3)

pulse shapes goodlinearity ~ +/- 0.2% (~ 2 x spec.)pulse shape matching within spec. apart from lowest end of mid and low gain rangesno obvious distortion introduced on lower gain channels by higher gain channels saturating => good chip layout

noise close to simulation values (< 10,000 (3,500) e for mid and high gain ranges for barrel (endcap))

I2C features (channel offsets, calibration) fully functioning

5 Mrad radiation results – small effects only

for more detailed studies need packaged chips

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externalcomponentsdefine CRand CSA gain

externalcomponentsdefine RC

V/I gainresistors

offset &CAL pulsegeneration

I2Cinterface

offsetadjust

MGPA – architecture overview

diff. O/P

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