Metal-Oxide-SemiconductorField-EﬀectTransistors(MOSFETs) ·...

Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs)

Introduction.The figure below illustrates schematically the MOSFET structure (an n-channel MOSFET or nFET - isshown. p-channel devices or pFETs are doped in a complementary manner): Heavily n-doped source anddrain regions are separated by a p-type region. An insulating layer (the oxide, SiO)2 in the most commonimplementation of the device) separates the p-type substrate from the third electrode, the gate, typically eithera metal or heavily-doped n-type polycrystalline Si.

When the gate is grounded or negatively biased, the p-substrate is accumulated. The application of a voltagebetween the source (taken as grounded) and the drain (under a positive bias VDS) contacts cannot result in

ECE609 Spring 2010 170

any current, because of the built-in potential (possibly enhanced by a negative gate bias). If, however, we applya positive gate bias, VG, the effect is that of a forward bias applied to the source-substrate n-p junction. Inother words, as the p-type substrate is being inverted by the positive gate bias, a conductive channel is formedat the substrate-oxide interface and current flows from the source to the drain. A higher postive gate bias willincrease the electron density in the inversion layer, thus enhancing the source-drain current.


It is this ability to control the conductivity of the channel with a third terminal, the gate, which renders thisdevice a resistor whose resistivity is modulated by the gate. As an analog device, it is an amplifyier, since asmall signal on the gate can be amplified by applying a large source-to-drain bias. As a digital device, it canbe toggled between conduction and no-conduction, thus performing the function of a switch (0 or 1 logicalstates). The figure below shows the result of a Monte Carlo simulation: Electrons indicated by little spherescolored according to their kinetic energy pool up in the source (at the right) and spill over into the channel,dropping to the drain. The surface on which they move is the potential energy as seen from the top. Thepotential barrier of the SiO2 insulator has been deleted from the figure.

Drain current: Drift-diffusion analytic model.


The figure above shows the potential energy for electrons in an n-channel MOSFET. The drain current is due toelectrons wich exit the source region and drift along the channel towards the drain at the right. Lets considerthe x axis along the channel and the y axis pointing downward, the interface being located at y = 0. Letsstart by viewing the channel as a resistor, and let V (x) be the potential at y = 0 at the point x along thechannel. The current density along the interface will be:

jnx(x, y = 0) = e n n(x, y = 0) Fx = en n(x, y = 0)dV (x)

dx. (532)

The total inversion charge in the channel at position x along the channel will be

Qinv(x) = e

0n(x, y) dy . (533)

Thus, from these equations, the total drain current will be

ID = W

0Jnx(y) dy = WQinv(x) n

dV (x)

dx. (534)

This expression can be viewed as Ohms law: In a small element of the channel of length dx we have

dV (x) = ID dR(x) , with resistance dR(x) =dx

WnQinv(x). (535)

In order to estimate how the total inversion charge Qinv varies along the channel, lets recall that V (x) = 0near the source, while V (x) = VD, the drain voltage, near the drain. When the semicondcutor surface is instrong inversion, we have s = 2B near the source and s = 2B + VD near the drain. Generalizing thisalong the entire channel,

s(x) = 2 B + V (x) . (536)

Now, since the charge in the gate at x will be the sum (with opposite sign) of the inversion and depletioncharges in the sustrate:

QG(x) = Qd(x) + Qinv(x) , (537)


and since the total voltage drop in the oxide is given by

Vox(x) = VG [VFB + s(x)] = VG [VFB + 2B + V (x)] =QG(x)

Cox, (538)

we have from Eqns. (537) and (538):

Qinv(x) = Cox{VG [VFB + 2B + V (x)]} Qd(x) . (539)Since the surface potential varies along the channel as described by Eq. (536) above, the width of the depletionregion also varies and so also the depletion charge (denoted here as WD to avoid confusion with the width ofthe device, denoted by W ):

Qd(x) = NAWD(x) = {2esNA[2B + V (x)]}1/2 . (540)Integrating now Eq. (534) from source to drain:

L0

ID dx = ID L = Wchannel

Qinv(x) ndV (x)

dx= W n

VDVS

Qinv(x) dV , (541)

where L is the channel length. Using Eqns. (538) and (540) to express the inversion charge and recalling thatID is constant along the channel:

ID = n CoxW

L

VDVS

{VG [VFB+2B+V ] (1/Cox) [2esNA(2B+V )]1/2} dV . (542)

Setting = (2esNA)1/2/Cox and VDS = VD VS we have:

ID = nCoxW

L

{(VG VFB 2B VS

VDS

2

)VDS

2

3[(2B + VD)

3/2 (2B + VS)3/2

(543)


0 2 4 6 8 100

2

4

6

8

10

ID,sat

VD,sat

saturation

VFB = 0, VG = 5.0 V, W=L

tox = 10 nm, NA=1016 cm3, n = 200 cm2/Vs

VDS (V)

I D (

104

A)

This equation describes the drain current correctly up to the drain bias at which ID reaches a maximum, thatis, dID/dVD = 0. This voltage,

VD,sat = VG VFB 2B +2

2

[VG VFB +

2

4

]1/2, (544)

is called saturation voltage. When this happens, one can see that Qinv(x = L) = 0, that is, the inversionlayer is not formed at the drain-end of the channel. The analysis leading to Eq. (543) is not valid any longer: Thedrain current does not decrease, as predicted by that equation, but remains pinned at its value at VD = VD,sat,value called saturation current and indicated by ID,sat. At any drain bias above VD,sat the channel is said


to be pinched-off and the portion of the channel in which there is no inversion layer is called the pinched-offregion.Note that even in pinch-off the channel remains conductive. A simple argument can be given why the currentmust saturate: The voltage-drop across the pinched-off region of the channel is VD VD,sat, while in therest of the channel the voltage drop is always VD,sat, irrespective of the drain bias applied. Therefore, theconduction properties of the channel do not change and the current saturates.The threshold voltage will be the total voltage (drop in the oxide + drop in the substrate) needed to set up stronginversion, s = 2B. Since VG = s+Vox = s+QG/Cox, noticing that at the onset of strong inversion

most of the charge in the semiconductor will be due to ionized impurities, eNAWD,max = [2esNA2B]1/2,

and that this must be equal (and opposite) to QG, we have, also accounting for the shift VFB :

VT0 = VFB + 2B +(4NAesB)

1/2

Cox= VFB + 2B + (2B)

1/2 , (545)

where the subscript 0 indicates that this is the threshold voltage when the source is grounded. When thesource is not grounded, we must shift this expression by VS (since it is the threshold at the source-end of thechannel which controls the flux of carries towards the drain):

VTS VFB + 2B + VS + [VS + 2B]1/2 , (546)

Drain current: Simplified model. The model developed so far can be simplified by linearizing the dependenceof the depletion region on the local surface potential V (x):

Qd(x)Cox

=[2seNA(2 B + V (x))]

1/2

Cox (2B)1/2 + V (x) , (547)

where is the linearization constant (equal to /[2(2B)1/2]). Now, from Eqns. (545) and (546):

VTS = VT0 + VS + [(2B + VS)1/2 (2B)1/2] VT0 + VS + VS , (548)


while from Eqns. (539) and (540) the inversion charge becomes:

Qinv(x) Cox{VG [VT0 + (1 + )V (x)]} . (549)

Lets now define the body factor n = 1 + , so that the expression above becomes:

Qinv(x) Cox{VG [VT0 + nV (x)]} . (550)

In order to extract the drain current in this approximation, we proceed as before, integrating the current fromsource to drain: L

0ID dy = W n

VDVS

Qinv(x) dV (x) , (551)

so that, since ID does not depend on x by current continuity:

ID =W

Ln Cox

VDVS

[VG (VT0 + nV )] dV . (552)

Re-writing the linearized version of Eq. (548) as VTS VT0 + n VS, we have:

ID W

Ln Cox

[(VG VTS)VDS

1

2nV

2DS

]. (553)

Once more, this equation describes a parabolic dependence of ID on VDS, but it is physically meaningfullonly untill the channel is pinched-off. This occurs when VDS = VD,sat, where the saturation drain voltage already seen in Eq. (544) above is now approximated as:

VD,sat 1

n(VG VTS) + VS . (554)

The region for which Eq. (543) holds true (i.e., for VD VD,sat) is called the linear region. The bias-regionVD > VD,sat is called the saturation region. Lets consider separately these two regions.


In the linear region, lets consider Eq. (543) for small VD (so that we can neglect terms of order V2D).

Setting VS = 0 so that VDS = VD we can write the drain current in the following form (see Eq. (553)which is fully equivalent after having introduced the linearization parameter ):

ID = nCoxW

L

[(VG VT0) VD

(1

2+

(seNA/B)1/2

4Cox

)V

2D

], (555)

or, ignoring terms non-linear in VD:

ID nCoxW

L(VG VT0) VD , (556)

for VD

conductance and transconductance are now given by:

gD,sat 0 , (560)

and

gm,sat nCoxW

L

1

n(VG VTs) . (561)

Velocity Saturation. We have to consider two corrections to the model developed so far: The first correctiondeal with quantization effects in inversion layers and we shall deal with it below. The second correctionconcerns electron-heating effects. We know that the electron mobility decreases as electrons become hotter(see Eq. (296), page 86):

n n,th

(1 + cen,thF2/T )1/2

=n,th

(1 + F 2/F 2c )1/2

, (562)

where we have defined a critical field F 2c = T2/(ecn,th). Therefore, in the saturated region, when the

large VDS applied will cause the carrier velocity to saturate, the drain current will be reduced with respectto the value we have estimated ignoring velocity saturation. To see how this happens, note that in Eq. (562)

F = Fx = dV (x)/dx. Thus, we can multiply both sides of Eq. (541) by (1 + F 2/F 2c )1/2. In so doingthe righ-hand side will remain unchanged, but the left-hand side will become

L0

ID

[1 +

(F

Fc

)2]1/2dx = Csat(VDS) ID > ID , (563)

where Csat(VDS) a function of the applied bias is always larger than 1, approaching unity only when VDSapproaches zero. Thus, under velocity saturation, the drain current will be reduced by a factor Csat(VDS).Besides this reduction of ID, velocity-saturation also implies a linear dependence of ID on VG, unlike the


quadratic dependence predicted by Eq. (559). This dependence is of the form

ID,sat Cox W (VG VT ) vsat . (564)

Physically, this can be obtained from Eq. (556): When velocity saturation occurs we must replace nVD/L inthat equation with the saturated velocity vsat. However, note that this is not a derivation of Eq. (564), sinceEq. (556) is valid only for small VDS. A proof of Eq. (564) relies on more sophisticated arguments. In thislimit the transconductance becomes:

gm,sat =ID

VG Cox W vsat , (565)

expression which replaces Eq. (561). Note that the transconductance per unit width divided by the oxidecapacitance, gm,sat/(CoxW ), has dimension of a velocity and can be interpreted as some average carrier-velocity in the channel.

Operation in sub-threshold.So far we have considered the device above threshold, ignoring what happens for a gate bias which leaves theinterfacial region depleted (so, when the channel hasnt been yet formed). Yet, the operation of the device underthese conditions is quite interesting for low-power applications because it is associated with the way the deviceswitches on or off. This is called the subthreshold region.In subthreshold the electrons diffuse over the source/channel barrier, so that the drain current will be given by:

ID = eADnn(0) n(L)

L, (566)

where A is the cross-section across which the electrons flow,

n(0) = np0 es (567)


andn(L) = np0 e

sVD , (568)where, as usual, = e/(kBT ). We can estimated the cross-section A by noticing that the electronconcentration drops exponentially away from the interface. Lets assume that the concentration is a constantup to a distance ykT away from the interface at which the potential has dropped by kBT/e, so thatykT = kBT/(eFs), where the surface field is Fs = eNA/CD. Then, recalling Einsteins relationDn = n(kBT/e), setting A = WykT and recalling also that np0 = n

2i /NA:

ID = eW

L

(kBT

e

)2n

n2iNA

es

Fs[1 eVD ] . (569)

Since s depends linearly on the gate bias VG in substhreshold, the drain current increases exponentiallywith gate bias. It is customary to express this exponential behavior by the inverse subthreshold slope (orsubthreshold swing or simply subthreshold slope) S: By definition this is

S =dVG

d log ID=

ln(10)

d(ln ID)dVG

. (570)

Sinced(ln ID)

dVG=

1

ID

dID

ds

ds

dVG, (571)

and, from Eq. (569):

dID

ds= ID

d

ds

(ds

dy

) (ds

dy

)1, (572)

we have

d ln ID

dVG=

dds

(dsdy

)dsdy

dsdVG

. (573)


Now recall that the depletion capacitance CD is just CD = dQd/ds = s(dFs/ds), so that, sinceFs = ds/dy:

d

ds

(ds

dy

)= CD

s. (574)

Also, from this equation and the fact that Fs = eNA/CD (by Gauss law) we have:

dds

(dsdy

)dsdy

=C2DeNAs

=1

2s. (575)

Finally, inserting this equation into Eq. (573) and neglecting 1/(2s) compared to = 2/(kBT ), we have

S =ln(10)

d(ln ID)dVG

ln(10) kBTe

ds

dVG. (576)

Since VG = Vox + VFB + s = Qd/Cox + VFB + s, we have

ds

dVG=

1

1 +CDCox

, (577)

so that

S =kBT

eln(10)

(1 +

CD

Cox

)= n

kBT

eln(10) , (578)

where n is the body factor. Note that, from the definition of the subthreshold slope S, Eq. (570), we haved ln ID = dVG/S, so that

ID exp(qVG

nkBT

), (579)


where we recall that n = 1 + CD/Cox.

If interface states are present, then the associated capacitance Cit is in parallel with the depletion capacitanceCD and the subthreshold slope takes the form:

S =kBT

eln(10)

(1 +

CD + Cit

Cox

). (580)

At room temperature S 60 meV/decade. This is the minimum inverse swing we can expect. Deviationsfrom ideality only worsen (that is, increase) this number, as shown by the effect of interface traps in Eq. (580).Clearly, smaller inverse slopes (and so higher slopes 1/S and so a faster dependence of ID on VG) are preferablesince they imply that the device will turn on and off more abruptly with gate drive.

Surface mobility and transport in inversion layers.We saw before that quantization effects in inversion layers modify the transport properties (see Lecture Notes,Part 2, pp. 160-167). In this section we shall be a little more quantitative.

Carrier mobility in inversion layers.The Boltzmann Transport Equation (BTE) has been derived assuming that all quantities change slowly onthe length-scale of the electron wavelength. In inversion layers this assumption is clearly violated alongthe direction normal to the interface (which well assume is the z-direction). Indeed, this is the origin ofquantization effects in inversion layers. However, on the plane of the interface the electrostatic potential stillvaries slowly (at least in sufficiently long devices). Therefore, having accounted for the confinement along thez-axis, we can still describe transport on the (x, y) plane of the interface with a two-dimensional BTE.The carrier mobility can be computed by linearizing the BTE for small electric fields, obtaining the Kubo-Greenwood expression we have seen before (see Lecture Notes, Part 1, pp. 79-80). There are two majormodifications: First, several subbands (or even ladders of subbands) will be populated, so that we mustconsider separately the mobility ,j for each subband j in ladder . The total mobility will then be expressedas the average of the mobilities in each subband weighted by the fractional occupation n,j/ns of each


subband:

=,j

n,j

ns,j , (581)

where n,j is the carrier population in the subband (, j) and ns is the total carrier sheet densityns =

,j n,j. The second modification is caused by the two-dimensional nature of transport. The

mobility ,j will be given by (assuming for simplicity the diagonal element (xx) of the mobility tensor):

,j =e

mx,,jkBTn,j

E,j

dE (EE,j) ,j(E) (p,x),j (E) f,j(E)[1f,j(E)] , (582)

where f,j(E) = {1 + exp[(E E,j EF )/(kBT )]}1 is the Fermi function for the subband j inladder , E,j is the bottom of the subband, ,j(E) = m

(d),j/(h

2) is the density of states, m(d),j the

DOS mass in the subband, and (p,x),j (E) is the relaxation time for the x-component of the momentum.

This expression is fully analogous to the 3D Kubo-Greenwood expression, Eq. (273) on page 81 of the LectureNotes, Part 1. Like in the bulk, 3D case, complications related to the anisotropic nature of the dispersion (thatis, the presence of different transverse and longitudinal effective masses on the (x, y) plane for the unprimedvalleyes in Si) have been ignored.

Scattering processes.Dealing with carrier mobility in bulk semiconductors we considered two major scattering processes: Scatteringwith phonons (both acoustic and optical) and Colomb scattering with charged impurities (ionized dopants).The same scatterers should be considered in inversion layers, with the addition of another scattering processdue to the presence of the Si-SiO2 interface, namely scattering with interfacial roughness (often called surfaceroughness, SR).The scattering rate for a carrier in subband j in ladder (lets use the Greek letters , , etc. to indicatethe pair of indices (, j) and lets also employ upper case symbols the 2D electron wavector K, scattering


wavevector Q, etc.) can be evaluated with the 2D Fermi Golden Rule:

1

(K)=

2

h

Q

|H(Q)|2 [E(K) E(K + Q) E(Q)] , (583)

where E(Q) is the energy exchanged in the collision (phonon energy for phonon scattering, zero for elasticprocesses such as Coulomb or SR scattering). The term

H(Q) =

0dz (z) VQ(z) (z) (584)

is the matrix element of the scattering potential V (r) = V (R, z) (where

VQ(z) =1

(2)2

eiQR V (R, z) (585)

is the 2D Fourier transform of the potential V ) between the initial state (z)eiKR/A (where A is the

normalization area) and the final state (z)ei(K+Q)R/A. The momentum relaxation rate (along the x

axis, for example) will be:

1

(p,x) (K)

2h

Q

|H(Q)|2(Qx

Kx

)[E(K) E(K + Q) E(Q)] , (586)

which is just the expression for the scattering rate with the extra factor Qx/Kx = Kx Kx/Kx =1 K cos/K, the fractional change of momentum along the x axis. In the case of scattering withphonons an additional integration over the z-component of the phonon wavevector qz must be accounted for.Phonon scattering.Lets consider in detail the case of scattering with acoutic phonons since the matrix element exhibits an


interesting dependence on the strength of the quantum confinement. In this case the matrix element has theform:

H(ac) (q) =(

h

2q

)1/2ac|q|

AdR

0

dz (z) eiKR eiQR eiqzz (z) eiKR =

=

(h

2q

)1/2ac|q|(K K Q)

0

dz (z) e

iqzz (z) . (587)

Therefore, squaring and integrating over q as demanded by Eq. (584) or (586) (recall that the relaxation rateequals the scattering rate for isotropic and elastic processes):

dQ

dqz |H(ac) (q)|2 2ackBT

2c2s

dqz

0dz

(z) e

iqzz (z)2

, (588)

having used the elastic, equipartition approximation (nq kBT/(hq, the phonon energy ignored in theenergy-conserving delta-function) and having approximated hq as hcsq. Now lets consider the integral inEq. (588). Lets write it as:

dqz

0

dz (z) e

iqzz (z)

0dz

(z

) e

iqzz(z

) =

=

0

dz

0

dz(z

)(z)

(z)(z

)

dqz eiqz(zz) . (589)

Since dqz exp[iqz(z z)] = 2(z z), the term above becomes:

F = 2

0dz |(z)|2 |(z)|2 . (590)


Note that for a quantum well of width L this term behaves as L2. In inversion layers we can have an ideaof how this term behaves by using the Stern-Howard ground-state variational wavefunction

0(z) (b3

2

)1/2z e

bz/2. (591)

The parameter b can be obtained by minimizing the expectation value of the energy over this wavefunction:

b =3

z0 n1/3s , (592)

where z0 is the centroid of 0. Using this approximation, the momentum relaxation time for scattering withacoustic phonons behaves like:

1

(p) 3mzb

64h32acc2s

ph b1 n1/3s . (593)

Similar expressions hold in the case of scattering with optical (inter-valley) phonons. Note that both inthe case of a quantum-well (F 1/L2) as well as in the case of inversion layers (F 1/z0), thescattering (or momentum relaxation) rate increases with increasing confinement. In particular, in inversionlayers the phonon-limited component of the mobility, ph, behaves as:

ph n1/3s . (594)

Coulomb scattering.The squared matrix element for Coulomb scattering with NC charged centers per unit area (ionized dopants


in the semiconductor, interface traps, and oxide charges) has the form:

H(C) (Q) e2N

1/2C

Q2G(Q) , (595)

where G(Q) is a more complicated matrix element involving the initial and final wavefunctions (of course)and the Greens function for Poisson equation in the semiconductor/insulator geometry. Dielectric screening,somewhat more complicated than in bulk semiconductors, may be accounted for in a perhaps oversimplifiedway by replacingQ2 in the denominator of Eq. (595) withQ2+22D, where 2 is the 2D screening parameter.Note that the component C of the mobility limited by Coulomb scattering behaves as:

C n

4/3s

NC. (596)

Surface roughness.In the 70s Ando proposed a simple model for the effect of surface roughness on the mobility. He assumed thepresence of steps at the interface, caused by the existence of terraces in the semiconductor surface (see thefigure illustrating the qualitative atomic configuration of the Si surface with terraces).


(1x2) TERRACE(2x1) TERRACE

(100)surface [110]section

As seen in the figure below, each steps causes a shift of the wavefunction. Mathematically this correspondsto a change in the boundary conditions (z = 0) = 0 [z = (R)] = 0, where (R) is the heightof the step occurring at the position R on the plane of the interface. The scattering rate is proportional tothe matrix element of the free-electron Hamiltonian H between the shifted and the unshifted wavefunctions:

H(SR) =

0

dr (r) H (r) . (597)

It can be shown that in the case of inversion layers

H(SR)

dR

2ei(KK)R

(R)h2

2m

ddz

d

dz

z=0

, (598)

so that, introducing the 2D Fourier transform of the roughness, S(Q):

H(SR) (Q) = S(Q)h2

2m

ddz

d

dz

z=0

. (599)


The form of S(Q) to be employed can only be known either from experiments or from fitting procedures(theoretical calculations of the structure of the interface are only now beginning to yield tentative results).Ando assumed the only possible reasonable form based on a random correlation, a Gaussian auto-correlationspectrum:

|(R)|2 =

dQ

2eiQR |S(Q)|2 , (600)

where:

|S(Q)|2 = 22 exp[

2Q2

4

]. (601)

The parameter is the correlation length among steps (a sort of average distance between adjacent steps),while is root-mean-square (rms) height of the steps.Note that carriers at the Fermi energy contribute mostly to the mobility. Therefore, SR-scattering will haveits most significant effect when the Fermi wavevector of the 2D carriers will approach the peak of Eq. (601),roughly of the order of 1. Since is usually short (of the order of a few nm), SR-scattering dominates athigh carrier densities. Indeed the SR-limited mobility decreases as the carrier density (and so the confinement)grows:

SR 22n2s . (602)


SiO2 Si

(R) (R)

There are other components of the SR scattering Hamiltonian which have been considered by Ando: Theyarise from dipoles present at the steps and from their image charges. In addition, dielectric screening affectsthe perturbing potential. Nevertheless, while important from a quantitative point of view, these Coulombterms do not alter the qualitative features of the SR scattering processes, which are well captured by Eq. (599).Thus, we shall not discuss these additional terms.Using Matthiessens rule and the qualitative bahavior of the phonon-limited, Eq. (594), Coulomb-scattering-limited mobility, Eq. (596), and SR-limited mobility, Eq. (602), we obtain the qualitative behavior of the totalmobility (for electrons) shown in the figure below.


1011 1012 1013

103

104

4

56789

2

3

4

56789

2

3

C

ph

SR

tot

ns0.3

ns1.3

(nD+ns)2

ns ( cm2 )

eff

( cm

2 /

V s

)

We see that the electron mobility depends on the electron density ns, and so both on the confining field Fsas well as on the substrate doping (since this affects both the surface field, Fs, as well as the shape of thepotential in the depletion region).About 20 years ago it observed that if one expresses the mobility as a function of whats been called theeffective field

Feff =Qd + |Qinv|

s, (603)

(where = 1/2 for Si n channels (electrons) and = 1/3 for p channels (holes)), the mobility measuredin channels with various (uniform) substrate doping follows a universal curve, shown in the figure below, aslong as Coulomb scattering with the dopants is not dominant. The universal mobility curve is now widely


used in the device-modeling community. But we should keep in mind that this picture lacks any rigorousphysical justification and deviations from the universal behavior can be seen in the case of susbstrateswith non-uniform doping (case always true in todays VLSI technology demanding retrograde doping forshort-channel devices, as we shall see).

1011 1012 1013 1014101

102

103

2

3

4

56789

2

3

4

56789

ns (cm2)

(c

m2 /

Vs)

104 105 106 107101

102

103

2

3

4

56789

2

3

4

56789

NA = 1015, 3x1015, 1016,..., 3x1018 cm3

Feff (V/cm)

(c

m2 /

Vs)

Effective mobility.From the discussion above regarding the electron mobility in inversion layer, we see that a complication arises:If we look back at Eq. (541), we see that we performed the integral over the channel by taking n as aconstant. However, we have just seen that the electron mobility varies along the channel, since the confiningfield Fs also varies along the channel, usually decreasing from source to drain. Thus, the integration performedin Eq. (541) becomes impossible (unless one does it numerically). An approximated way to deal with thisproblem analytically is to approximate the carrier mobility with empirical expressions, function of the vertical


field Fs, of the density, of the effective field Feff , of the doping density, or more complicated expressionsfunctions of all of these variables. As an example, lets consider the simplest possible case of a mobilitymodulated by the effective field:

n(x) =n0

1 +KFeff (x)=

n0

1 + (K/s)[Qd(x) + |Qinv(x)|/2], (604)

where K is some fitting parameter with dimension of inverse field. We know that Qd + Qinv =Cox(VG VFB s), so that |Qinv| = Cox(VG VFB s) Qd. Also, Qd = NAW =(2esNAs)

1/2 = 1/2s (see Eqns. (539) and (540) replacing 2B + V (x) with s here), so that

n(x) =n0

1 + [KCox/(2s)][Coxs(x)1/2 + VG VFB s(x)]. (605)

Lets now go back to our starting point, the integration in Eq. (541). Before carrying out the integration, wehave in each infinitesimal element of length dx along the channel:

IDdx = Wn(x)Qinv(x) dV (x) (606)

From Eq. (605) we have:

IDdx =WQinv(x)n0

1 + [KCox/(2s)][Coxs(x)1/2 + VG VFB s(x)]dV (x) . (607)

Lets rewrite it as:

ID {1+[KCox/(2s)][Coxs(x)1/2+VGVFBs(x)]} dx = WQinv(x)n0 dV (x) . (608)

Lets define an effective mobility, constant along the channel, such that

ID dx = WQinv(x)eff dV (x) , (609)


so that, inserting this expression for ID into Eq. (608) we get:

WQinv(x)effdV (x)

dx{1 + [KCox/(2s)][Coxs(x)1/2 + VG VFB s(x)]}dx =

= WQinv(x)n0 dV (x) , (610)

which can be written as:

{1 + [KCox/(2s)][Coxs(x)1/2 + VG VFB s(x)]}dx =n0

effdx . (611)

Lets now integrate along the channel:

L0

{1 + [KCox/(2s)][Coxs(x)1/2 + VG VFB s(x)]}dx = Ln0

eff. (612)

Lets recall that s(x) = 2B + V (x) and lets assume a linear voltage drop along the channel, so thatdV/dx (VD VS)/L. Then, integrating the left-hand side with a change of variable x V we get:

n0

eff= 1+

KCox

2s

{(VG VFB 2B)

V 2D V 2S2VDS

+2

3

VDS

[(2B + VD)

3/2 (2B + VS)3/

(613)Lets now assume that the source is grounded (so, VS = 0) and consider only the case of small VD, whichis appropriate when considering the low-field concept of mobility. Thus, we can ignore the third term in the

equation above, notice that the last term is approximately (2B)1/2 and we get, finally:

eff n0

1 + KCox2s [VG VT0 + 2(2B)1/2], (614)


recalling that VT0 = VFB 2B (2B)1/2. This shows that the effective mobility is depressed atlarge gate bias, mainly because of the physical effects described above: The growth of the electron-phononmatrix element with increasing confinement and the effect of SR-scattering.

Short-channel effects.Devices have been made smaller and smaller since the dawn of ICs in the 70s because this scaling affordsincreased perfomances and reduced costs: The availability of smaller FETs mean one can pack more functionalityper unit area of Si wafers. Since the cost of Si real estate has remained constant, this translates into reducedcost per function. The availability of smaller devices also means improved performance of a single device, thusincreased speed of operation and, so, reduced cost per operation performed. However, as devices are scaled tomaller dimensions, several problems arise. We shall now discuss problems related to the degraded electrostaticbehavior of small devices (the proper short-channel effects, namely VT -shift, channel-length modulation, andthe associated increase of the subthreshold current) as well as transport issues: Non equilibrium transport (whichrenders concepts like n and vsat meaningless, so undermining the derivation of the ID VD characteristicswe have discussed so far) and hot-electron degradation effects. These have been a dominant concern in the lastdecade, but their importance is waning (albeit not completely), as the supply voltage is being reduced in thepresent VLSI technology. We shall later discuss how to circumvent (or, at least, minimize at the best of ourability) these short-channel effects by following proper scaling rules or, if this is not a technologically feasibleoption, how to modify the structure of MOSFETs to achieve our goals.

Electrostatic short-channel effects.The figure in the net page illustrates the electrostatic problems we must face when shrinking the device:At left we see a MOSFET at VDS = 0. The depletion regions due to the source, drain, and gate areschematically sketched. Note that the area of the depletion region controlled by the gate has a trapezoidalshape. For very long devices, one may assume that the top and bottom length of the depletion region, Land L1 respectively, are approximately equal. But as L is reduced to dimensions approaching the width ofthe source/drain depletion widths, we see that the area of the trapezoidal depletion region is reduced. Simplegeometrical arguments show that the underhang x is given by

x = rj [(1 + 2WD,max/rj)1/2 1] , (615)


where rj is the S/D junction depth. Thus, the total depletion charge controlled by the gate Qd will bereduced from the long-channel value Qd0 = WD,maxNA by the amount:

Qd

Qd0=

1

2

(1 +

L1

L

)= 1 rj

L[(1 + 2WD,max/rj)

1/2 1] . (616)

OXIDE

GATE

rj

rj

WD,max

x

rj+WD,max

L

L1

OXIDE

GATE

WD,max

WSWD

yS yD

L

L1

Since the threshold voltage depends on Qd (see Eq. (545) and discussion preceeding it), this reduction ofdepletion charge will result in a reduction of VT0:

VT0 = VFB + 2B +eWD,maxNA

Cox{1 rj

L[(1 + 2WD,max/rj)

1/2 1]} . (617)

This is a serious issue regarding yield: The drawn channel length (that is, the length of the channel asspecified in the lithographic mask set) will always be translated into a real channel length subject to statisticalprocessing errors (mask misalignement, variations in etching rates, fluctuations of doping profiles, etc.). Thebest tolerance control thus puts a limit to the minimum L one can emply without sacrificing too many deviceswith VT0 outside the specification.


The figure on the previous page illustrates another problem: The modulation of the channel length caused bythe drain bias: Comparing the drawing at left (VDS = 0) with the drawing at right (VDS = 0), we see thatas VD increases, so does the width of the depletion region at the drain, WD = [2es(2B+VD)/NA]

1/2.This, in turn, modifies both the threshold voltage (the quantity VT,sat mentioned above) as well as thechannel which, at the surface, shrinks by an amount L(VD) yS + yD. From any of the expressionsfor the drain current considered above (such as Eq. (543) or Eq. (553)), replacing L with L+ L(VD) wesee that the current will increase. In saturation (see Eq. (559) or Eq. (564)), this dependence of ID,sat onL(VD) will result in a nonzero output conductance gD. In most cases the ID VD characteristics ofthe device in saturation can be approximated by a linear saturation behavior, characteristics at different VGconverging to ID = 0 at a common voltage VA known as the Early voltage (as shown in the figure belowin which we compare the ideal long-channel behavior - left with the short-channel behavior right). In thiscase the output conductance in saturation will be approximately gD,sat = ID,sat/VA.

0 2 4 6 8 100

2

4

6

8

10

VG = 5.0

VG = 4.0

VG = 3.0

VFB = 0, W=L

tox = 10 nm, NA=1016 cm3,

n = 200 cm2/Vs

VDS (V)

I D (

104

A)

10 5 0 5 100

2

4

6

8

10

VA

VG = 5.0

VG = 4.0

VG = 3.0

VFB = 0, W=L

tox = 10 nm, NA=1016 cm3,

n = 200 cm2/Vs

VDS (V)

I D (

104

A)

An alternative way to look at the problem is to consider the effect of the drain bias on the height of the barrierat the source-channel junction. This barrier controls the flow of electrons injected into the channel from thesource. Ideally, in an electrostatically long-channel device, only VG controls the height of this barrier. But


as the width of the depletion region near the drain grows and approaches the source-region, drain-inducedbarrier lowering (DIBL) may occur. As VD grows, the barrier-height shrinks. This results in the undesirednon-zero output conductance of electrostatically short-channel devices.When the channel becomes sufficiently small, the effective channel length L yS yD may approach zeroat large VD. In this case the gate does not have any more control of the charge (and so, of the conductivity)of the channel: Carriers may flow directly from the source depletion-region to the drain depletion-regionregardless of gate bias. This situation in which the source and dran depletion-regions merge is calledpunch-through. It is a catastrophic failure of the device, since it cannot be turned-off any more by the gatebias.Finally, as seen in the figure on page 196, the VD-induced modulation of the channel-length will also cause anincrease of the subthreshold current. Indeed, when the width yDS of the depletion region at the body-drainbecomes comparable to the channel-length L, Eq. (569) becomes:

ID = eW

L yS yD

(kBT

e

)2n

n2iNA

es

Fs[1 eVD] . (618)

Simply put, coupling this observation with the onset of punch-through, when the channel becomes too shortthe device does not turn-off as well.The three phenomena we have just discussed VT shift, channel-length modulation (and punch-through),and degradation of the subthreshold current are purely electrostatic effects. As we shall see below discussingscaling laws, they have to do mainly with the design of the device: A device may be made short while mantaininglong-channel electrostatic behavior if scaled properly. Conversely, relatively long devices may exhibit badshort-channel problems if poorly designed. Thus, we may talk of electrostatic long-channel or short-channelbehavior. Dimitry Antoniadis of MIT has coined the term well tempered MOSFET (paraphrasing J. S. Bachswell tempered clavier discovery in musical theory) to describe well-designed devices exhibiting electrostaticlong-channel behavior.

Hot electron effects.A second set of short-channel-related problems is related to transport issues. The first of such problem isrelated to the length of the channel relative to the mean-free-path of the carriers in the channel itself. In


this section we have made ample use of the drift-diffusion equatins (DDE) to derive approximate expressionsfor the drain current ID. Lets recall that we assumed implicitly that the (drift) velocity is a function ofthe local electric field Fx = dV/dx via vdrift = nFx. In using the concept of mobility we have alsoassumed that the electric fields are small enough to keep carriers at kinetic energies near the thermal value,so that n is a well-defined concept. (An exception to this approximation was discussed when dealing withvelocity saturation). All of these assumptions are valid when carriers scatter many times along the channel,so that these many collisions keep them cool and in local equilibrium with the field. Thus, we must requireL >> . When, on the contrary, the channel-length shrinks to such an extent that L , several problemsarise:

1. Off-equilibrium effects. With only few collisions occurring as the carriers transit along the channel, theequilibrium concept of mobility ceases to be valid. Carrier entering the high-field region of the channel atthe source end, past the source/body barrier, will be accelerated to velocities larger than vsat in a timeshorter than the scattering time. Only later will they scatter, but their velocity will be given neither bythe mobility-field product nor by vsat. This velocity overshoot effect had resulted in effective velocitiesgm/(WCox) larger than vsat at low temperature (77 K) in 0.1 m channel-length devices in experimentsperformed at IBM and MIT as early as 1986. The results of these experiments is shown in the figure below.Note how the transconductance in saturation increases as the channel length is reduced, in sharp contrastwith the predictions of Eq. (565). Only considering higher moments of the BTE or, better yet, obtainingexact solutions of the BTE via Monte Carlo methods (used to obtain the simulation result in the figureabove) one can account for these strong non-equilibrium effects.


0.00 0.10 0.20 0.30200

400

600

800

1000

1200Experiments

(SaiHalasz et al.)Simulation

77 K

300 K

METALLURGICAL CHANNEL LENGTH ( m )

TRA

NS

CO

ND

UC

TAN

CE

(S

/m

)

2. Electron heating. As a result of the small number of collisions in the channel, the carrier energy will increaseabove the thermal value. In addition to invalidating the assumptions behind the DDE, the excess carrierenergy may cause real (as opposite to theory-related) problems: Electrons (which tend to get hotter moreeasily than holes) can impact-ionize as they gain enough energy approaching the drain-end of the channel.The generated holes can damage the Si-SiO2 interface. Similar damage can be caused by hot-electronshitting the interface. Or, for VD large enough ( 3.2 eV), electrons may be injected into the SiO2 conductionband. The net result will be the generation of interface traps and/or oxide charge due to electron trappedin the insulator. These charges will cause VT shifts (via VFB shifts we have considered before (see LectureNotes, Part 2, pp. 156-159) and/or degradation of the sub-thresold slope S (see Eq. (580). These effectswill change with time, as the devices operate, and will depend on the history of each device. Eventually, thecircuits will stop operating correctly, as a number of devices will fail to turn on or off at the specified gatebias.


Experimentally the presence of hot electrons in the channel can be monitored by measuring the substratecurrent (due to holes generated by impact ionization and diffusing to substrate contact) and the gate current(due to electrons injected into SiO2 and collected by the gate contact. The letter at first grows withincreasing VD at a given VG. But as VD grows larger, along an increasingly larger fraction of the channelthe surface electric field Fs decreases, thus preventing electron injection into the insulator. Usually, themaximum gate current is observed for VD VG/2.

Scaling laws.So, having seen that short channel-length pose all sort of problems, how do we circumvent these difficulties inour attempts to scale devices? The severity of hot-electron-degradation problems are clearly reduced as theapplied bias is reduced. For many years IC and system manufacturers had been reluctant to move away fromthe standard supply voltage of VDD = 5V. This depended manily on the practical considerations of retainingthe same power supplies without wasting precious Si-wafer area populated by voltage-reduction circuits. Butin the late-80s the electric fields present in devices became untolerably high with serious-to-catastrophic hotelectron issues (even felt in Wall Street!). Thus VDD was reduced to 3.3 V. Once the standard of 5 V hadbeen abandoned, it was only a matter of time to see it dropping even more. Clearly, it will be driven as low asnoise and tolerance margins will allow (probably down to 0.6 V at 300 K, maybe less if low-T operation willbe considered).Off-equilibrium effects are a problem for those trying to understand device operations, but do not hamperdevice operation.Electrostatic problems can be solved (to some extent, we shall discuss these limits) by reducing the lineardimensions of the device while at the same time mainting the same aspect-ratio and reducing the junctiondepth rj and the width of the depletion regions. Two basic strategies can be considered, requiring slighltydifferent scaling criteria: Constant-voltage and constant-field scaling.Constant-voltage scaling, as the name suggests, was of interest when the holy value VDD = 5 V wasemployed. We shall not discuss it, although historically it has dominated the scene for a couple of decades.Constant-field scaling requires shrinking the device while at the same time reducing the applied bias by thesame factor, so that the electric fields inside the device remain roughly unchanged. Lets call this scalingfactor 1 (called 1/ by Fritz Gaensslen and Bob Dennard in their pioneering 1974 paper). So, for example,


for = 21/2, we want to reduce the channel-length by 40% and so the device area by a factor of 2, thusincreasing device-density on chip also by a factor of 2 (which, according to Moores law, happens every 18months). The first two columns of the table below are taken from the literature (and the Colinge-Colinge text)and tell us how to increase doping, reduce oxide thickness and junction depth in order to maintain long-channelelectrostatic behavior. They also tell us how the performance will be affected in the DDE-context, but itshould be taken with a grain of salt, given the approximate (to say the least!) validity of the DDEs forsmall devices: For example, according to the DDEs, the current is expected to scale as , according to theexpression ID,sat (W/nL)Cox(VG VT )2. But we know that this is not necessarily true (at leastfor channel-length longer than about 50 nm): From the figure on page 200 (experiments in which Cox waskept constant rather than being scaled as ) we expect ID/W gm/W , when accounting for anincreasing Cox and a compensating reduction of VDD, thanks to the reduction of the channel lengthL, so that ID constant, as W is also reduced. Thus, in the third column we see what would happen ifthe drain current remained constant as we scale the channel length. The gate capacitance is WLCox, so itis reduced by a factor 1. The power consumption goes as VDDID. The gate delay is VDDCox/ID.The scaling of the doping concentration is a little tricky: A reduction of the depletion regions by a factor of requires an increase of doping concentration by 2. But since built-in potentials do not scale and VT isreduced with VDD, the issue is more subtle and a factor of shows how we attempt to reduce the width ofthe depletion regions.


Parameter Scaling factor (DDE) Scaling factor (BTE)

Dimensions L, W , tox 1 1

Applied voltage VDD 1 1

Threshold voltage VT 1 1

Current ID 1 1

Doping concentration NA, ND Oxide capacitance Cox

Gate capacitance WLCox 1 1

Power density IDVDD/(WL) 1

Current density ID/(WL) 2

Power consumption IDVDD 2 1

Gate delay WLCoxVDD/ID 1 2

Power-delay product WLCoxV2DD

3 3Integration density (transistors/unit-area) 2 2

Scaling limits.If we could follow the recepies of the table above to the letter we would be able to scale MOSFETs endlessly.Clearly, something is going to give at some length scale. The search for the ultimate limits of device scalinghas always fascinated researchers worldwide. Often, papers have appeared in scientific journals forecastingdoomsday scenarios: The one-micrometer barrier will put a halt to scaling, then it was the 0.25 m barrier,then the 0.1m. Now (having changed units) we argue about whether 80 or 40 nm will mark the end.What limits scaling? Several factors. We list here only the most obvious ones:

1. Doping cannot be increased without limits: For every dopant impurity there is a solid solubility limit forthe concentration. Above this limit no more impurities can go substitutional and so be electrically active.


For n-type Si, this limit is around 1021 impurities per cm3. Thus, depletion regions will not shrink forever.2. Processing requires several high-temperature treatments. The total thermal history (usually referred to as

thermal budget) causes dopant diffusion. This, in turn, results in less and less sharp junctions, so inexcessively wide depletion layers.

3. The energy gap and the thermal energy kBT cannot be scaled as VDD is reduced. This has a wide rangeof effects. For example: The built-in potential between source and channel must be overcome, so we cannotreduce endlessly VDD; noise and tolerances issues put a realistic limit of about VDD 0.6 V for Si at300 K.

4. As the doping increases, Zener tunneling at the drain-body junction will cause untolerable leakage.5. The oxide thickness cannot be reduced below 1 nm (maybe even slightly more): The quantum-mechanical

tunneling current across the insulator causes unwanted power dissipation (and also loss of drain current, inthe limit of extremely thin oxides, as electron travel from the source to the gate instead of ending up in thedrain).

6. Fluctuations: Reducing the area WL of the device implies a reduction of the total number of dopants.For L = 10 nm, W = 100 nm and NAWdepl,max = 10

13 cm2, we have only 100 impurities in thechannel. Thus we expect an rms fluctuation of 1/

100 10% on VT , which is unacceptably large. Also,

as the oxide thickness shrinks, thickness fluctuations of only a single atomic layer become relatively huge,causing again VT fluctuations and mobility reduction.

7. Ultimately, the barrier present between source and drain below threshold could be penetrated by quantum-mechanical tunneling for small-enough L. In this case the device will not turn off (or it will do so atunreasonable high VT ).

Each of these issues has been receiving considerable attention and there ideas about how to bypass them, atleast in part:

1. Novel device structures may reduce electrostatic short-channel effects: Silicon-on-insulator (SOI) and theuse of retrograde doping put a limit to the depth of the depletion region controlled by the gate, so that theshort-channel effects of on page 190 are reduced or eliminated. Double-gate devices constitute the ultimate


implementation of these ideas and have been proven (theroretically) to be scalable at least down to L 30nm, possibly even smaller.

2. Ion implantation (more precise and controllable then the diffusion processes originally employed) is nowstandard, replacing gas-phase diffusion. Larger dopant ions (As instead of P for n doping, In instead B forp doping) are now employed, to make use of their reduced diffusion constants. Rapid thermal annealing (orspike anneals) are employed to reduce the thermal budget as much as possible.

3. Low-T operation can provide functionality at reduced VDD. Lower-gap materials will also exhibit smallerbuilt-in potentials (however, this is bad from the point of view of issue 4 below).

4. MOSFET structures with undoped channels (fully-depleted SOI, double-gate FETs) will reduce this problemby reducing Vbi at the junctions.

5. Alternative insulators with higher dielectric constant (high- or high-k insulators) are being investigated aspossible substitutes for SiO2: If ox is increased, we can increase the capacitance Cox = ox/tox withoutreducing tox excessively. This will reduce significantly the tunneling-induced gate-leakage problem. Metalgates (replacing poly-silicon gates, employed to simplify VT problems for pMOSFETs and nMOSFETs in theCMOS technology) ) are being also considered to avoid the poly-depletion problem: In inversion, the gatewill be depleted. This depletion effectively increases the oxide thickness and reduces the gate capacitance.

6. Double-gate and fully-depleted SOI FETs can be designed with undoped channels. Thus, dopant fluctuationswill be minimized. There is no solution for thickness fluctuations, though.

7. There is no known solution to this problem, which may be the ultimate stumbling block.

We could keep going discussing these issues, since each solution presents its own drawbacks. We shall discussbelow in slightly more detail the alternatives to conventional scaling which are being investigated at present.

Terminal capacitances and other parasitic elements.A note on resitivity and effective channel length: For an isotropic conductor, we define the conductivity such that j = F,

where j is the current density and F the electric field. The resistivity (measured in cm) is defined as 1/. For a conductor (or

semiconductor) with mobility and carrier density n = en. If the conductor of length L has a cross section A = Wd, then the

resistance of the conductor is R = L/A = (/d)(L/W ) = RshL/W , where Rsh = /d is called the sheet resistance of the

conductor, often measured in /square (since for a square L = W the resistance is independent of the size of the square).


The channel length L we have used so far is a vaguely defined quantity: We can talk of the gate length LG, of the metallurgical

channel length Lmet, or of the actual (effective) channel length Leff = L yS yD. A correct way to define it would be tosee how long is the region along the channel over which the electron (for n channels) or hole (for p channels) concentration deviates

significantly from the equilibrium unbiased situation.

The characteristics of an ideal devices do not tell us the whole story about the performance of a device. Ingeneral, devices have to charge loads (capacitive, resistive, inductive, or mixed). Typically the load is dominatedby wires (that is, interconnects among devices on the chip) or, more often by another gate. Thus, as devicesswitch, the speed of operation is controlled by the amount of charges which must be moved to fill the channel,charge the gate, modify the width of depletion regions. Thus it is important to know the capacitances associatedwith various junctions in a MOSFET. In addition, the source and drain regions will be connected to the S/Dcontacts via a series resistance due to the finite resistivity of the source and drain regions themselves.

Regarding the devices capacitances, the figure above, left frame, illustrates the various components:

Cj, the junction (or diffusion) capacitance, exists at the S/D junctions when the transistor is on. Thedepletion capacitance CD can be thought as part of Cj, but its contribution is small. Cj is given by theusual expression:

Cj =s

WDj=

[esNA

2(Vbi + Vj)

], (619)

where Vbi is the built-in potential of the junction, WDj is the width of the depletion region at the junction


and Vj is the voltage applied across the junction (so, VS or VD). The total capacitance CJ will be

CJ = WdCj , (620)

where d is the diffusion width. Cov is the overlap capacitance. The right frame of the figure above shows its components: 1. A direct

overlap component

Cdo = WlovCox = oxWlov/tox , (621)

where lov is an equivalent overlap length; 2. An outer fringe component

Cof =2oxW

ln

(1 +

tgate

tox

); (622)

3. An inner fringe component

Cif =2sW

ln

(1 +

xj

tox

), (623)

which exists only below threshold (VG < VT ) since when the channel is formed the 2DEG screens the gatefield.

To analyze the series resistance, lets consider the source side with reference to the figure below.


Looking at the path of the current from the source contact to the channel, the resistance can be subdivided inthe following form:

Rsource = Rac + Rsp + Rsh + Rco , (624)

where:

Rac is the accumulation resistance, that is, the resistance of the accumulation layer in the overlap region. Itdepends on VG and, thus, it is usually lumped into the channel resistance.

Rsp is the spreading resistance given by:

Rsp 2j

WSln

(0.75

xj

xc

), (625)

where j = 1/(enSS) is the resistivity of the source region with depletion depth WS characterized bya (bulk) electron density nS = ND with mobility S. Typically xj/xc 40 and Rsp 2j/WS .Since the doping concentration is never uniform, this equation is just a rough approximation. The carries will


follow a spreading path such that Racc + Rsp is minimized. Only 2D transport simulation can accuratelyestimate the values of these resistances in a 2D highly-inhomogeneous situation. For abrupt junctions, theinjection point is close to the metallurgical end of the channel, so that the effective channel length Leff isapproximately Lmet. For the more realistic graded horizontal profiles, the injection moves to the left, sothat Leff > Lmet. These are the dominant components of the total series resistance.

Rsh is the sheet resistance of the source/drain diffusions, given by

Rsh SDS

WS, (626)

where SD is the sheet resistivity of the source/drain regions. Rsh is typically negligible compared to thechannel resistance, provided the length S of the source diffusion is not excessively large.

Rco the contact resistance approximately given by:

Rco (SDc)

1/2

WScoth

[lc

(SD

c

)1/2], (627)

where lc is the width of the contact window and c is the interfacial contact resistivity. Note that for a short

contact (lc > (c/SD)1/2), instead:

Rco (SDc)

1/2

WS, (629)

independent of lc since the current flows mainly at the edges of the contact.


A similar analysis can be done for the drain resistance. The experimentally measured characteristics (ID VD,ID VG, gm, etc.) are called extrinsic characteristics. When corrected for parasitic effects (mainly seriesresistances for dc characteristics) they are called intrinsic. Typically, RS and RD are extracted by obtainingthe extrinsic channel resistance (proportional to L) as a function of channel length for a given technology.Extrapolating to L = 0 one obtains the series resistance (assuming that nothing else changes as L is varied...)

Various MOSFET structures and some advanced concepts.

OXIDE

GATE

high NA

low NA

RETROGRADE DOPING

OXIDE

GATE

BURIED OXIDE

SOI

OXIDE

GATE

BURIED OXIDE

FULLYDEPLETED SOI

OXIDE

GATE

BOTTOM GATE

OXIDE

DOUBLE GATE

The figure above shows some MOSFET structures designed in order to minimize short-channel effects. All of


these designs put a limit to the maximum depth of the depletion region, thus pushing the threshold-voltageroll-off to smaller channel lengths. Retrograde substrate doping achieves this goal with very heavy dopingof the substrate. Since this damages transport via Coulomb scattering, the doping profile is minimized nearthe semiconductor/insulator interface, but is increased at an optimum depth. However, there are limits to themaximum doping gradient which can be mantained during the thermal cycles. An insulating layer at the bottom(silicon-on-insulator, SOI) also achieves the same effects, while also reducing the junction capacitances CJ .Fully depleted SOIs (also called thin body or thin Si SOIs) push this idea to the limit and have the advantageof allowing an undoped substrate (provided some other way of adjusting VT is found), thus improving carriertransport. The ultimate device design is the double gate FET (DG MOSFET): A bottom gate not onlyminimizes short-channel effects, but it can provide higher current (at the expense of a larger gate capacintance)and, if the two gates are controlled independently, dynamic VT control. DG FETs come in the planar designillustrated (hard to fabricate) or in the FINFET (Stanford U) or Trigate (Intel) versions.In the search for even faster devices, as conventional scaling becomes harder, not only alternative device designbut also alternative materials are being considered. We have seen high- insulators as possible replacements forSiO2. Strained Si, SiGe alloys, or even III-V compund semiconductors are being considered. In class we will havea brief discussion of these attempts.


Other FET structures.

In addition to the MOSFET, it is worth considering at least briefly two other types of field-effecttransistors: The Junction FET or JFET, the MEtal-Semiconductor FET or MESFET, and the High Electron-Mobility Transistor, or HEMT (also called Modulation-Doped FET, or MODFET).

JFETs.

The JFET (illustrated above in the original drawing by Shockley having Shottky barriers at thegate/semiconductor interface; often, as we shall consider here, thin p+ regions are added under the gate


contacts) is essentially a resistor (n-type in the figure) whose resistivity is controlled by squeezing the crosssection of channel by modulating via an external bias applied to top/bottom gate contact the width of thedepletion regions of the p+-n junctions.When the gate is grounded and a small gate bias, VD, is applied, the drain current will be given by the expressionvalid for a resistor of length L, cross section (2a 2xdepl)W , where W is the device width, and conductivityeNDn:

ID = eNDn2(a ydepl)W

LVD . (630)

The width of the depletion region at equilibrium is, as usual,

ydepl =

(2sVbi

eND

)1/2, (631)

where Vbi = (kBT/e) ln(NAND/n2i ) is the built-in potential of the p

+-n-regions under the gates (or ofthe Shottky contacts, if metal gates are put in direct contact with the channel). Applying now a negative gatebias, VG < 0, the depletion width grows to

ydepl =

[2s(Vbi VG)

eND

]1/2, (632)

so that the cross section of the channel shrinks and the drain current drops according to Eq. (630). The channelwill by completely squeezed when ydepl = a, or for a gate bias (which well call the thrshold voltage):

VT = Vbi eNDa

2

2s. (633)

If we now apply a larger drain bias, we cannot ignore anymore the variation of the depletion-width along the


channel (along, say, the x axis). Then:

ydepl(x) =

{2s[Vbi VG + V (x)]

eND

}1/2. (634)

We can now proceed more or less following the path we have followed dealing with the drain current of aMOSFET: In a small element of the channel of length dx we have a resistance

dR(x) =dx

2enND[a ydepl(x)]W. (635)

Then by Ohms law the voltage drop dV (x) across this channel-element will be dV (x) = IDdR(x).Integrating along the entire length of the channel and recalling that ID is independent of x we have:

ID L = 2enNDW

VDVS

dV

{a

[2s

eND(Vbi VG + V )

]1/2}, (636)

so that, for VS = 0:

ID = 2enNDW

La

{VD

2

3

[2s

eNDa2

)1/2 ((Vbi VG + VD)3/2 (Vbi VG)3/2

]}.

(637)Note that when the drain voltage increase beyond the value such that ydepl(L) = a, the channel becomespinched-off. This occurs for:

VD,sat =eNDa

2

2s (Vbi VG) = VG VT . (638)

For VD > VD,sat the current, similarly to what happens in a MOSFET, saturates as well. Inserting the value


for VD,sat of Eq. (638) into Eq. (637) we have:

ID,sat = 2enNDW

La

[eNDa

2

6s (Vbi VG) +

2

3

(2s

eNDa2

)1/2(Vbi VG)3/2

]. (639)

As we saw for the MOSFET, the output conductance in saturation is zero, according to this model. In practice,this is never the case, mostly because the presence of series resistances. Also in saturation the transconductanceis

gm,sat = 2enNDW

La

[1 +

(2s

eNDa2

)1/2(Vbi VG)1/2

].. (640)

The performance of JFETs (as well as MESFETs below) is limited by the fact that the gate has less controlover the channel-conductance than in a MOSFET. In the latter, the inversion charge is very close to the gatecontact, resulting in a large gate capacitance Cox = ox/tox. On the contrary, in JFETs the conductanceis modulated via the depletion width, which means that the gate must control charges farther away. This resultsoften in a lower dc or large-signal performance.

MESFETs.


The MESFET can be viewed as a JFET longitudinally split in half. As in a JFET, the gate controls theconductance of the channel by modulating the width of the depletion region, and so of the channel.Usually MESFETs are fabricated on compound III-V semiconductors (GaAs, AlInAs, etc.), since it has beenhistorically very difficult to grow or deposit a good insulator on these materials and Shottky contacts are thepreferred way to go. Because of the high low-field mobility of these semiconductors, MESFETs have beentraditionally preferred microwave devices, thanks to their low-signal speed. For large signal, the poor control ofthe channel-charge by the gate (as we saw above for JFETs) and the need to move a large amount of chargein-and-out of the depletion region hampers their performance.The operation of a MESFET is very similar to the operation of a JFET: If Vbi is now the Shottky potential, inanalogy with Eq. (635) we can write:

dV = IDdR =IDdx

enND[a ydepl(x)]W. (641)

so that:

IDL = enNDW

VDVS

dV

{a

[2s

eND(Vbi VG + V )

]1/2}, (642)

or

ID = enNDW

La

[VD

2

3

(2s

eNDa2

)1/2(Vbi VG + VD)3/2 (Vbi VG)3/2

]. (643)

Pinch-off occurs for VD > VD,sat where, exactly as in Eq. (638):

VD,sat =eNDa

2

2s (Vbi VG) = VG VT . (644)


In saturation we have:

ID,sat = enNDW

La

[eNDa

2

6s (Vbi VG) +

2

3

(2s

eNDa2

)1/2(Vbi VG)3/2

].. (645)

The transconductance is given by an expression identical to Eq. (640).

5.4 5.6 5.8 6.0 6.2 6.4 6.61.5

1.0

0.5

0.0

0.5

1.0

1.5

2.0

Ev ()Ec ()Ec (X)Ec (L)

AlP

AlP

Si

Si

GaP

GaP

Ge

Ge

GaAs

GaAs

AlAs

AlAs

InP

InP

InAs

InAs

GaSb

GaSb

AlSb

AlSb

InSb

InSb

LATTICE CONSTANT ( )

BA

ND

ED

GE

ALI

GN

ME

NT

TO A

u (

eV )


HEMTs (or MODFETs).

Before introducing HEMTs, we must recall what hetero-structures are. We have seen previously paged 128-135 of Lecture Notes,

Part2 what heterojunctions are. Typically, a III-V semicondcutor can be alloyed to form a ternary compound such as AlxGa1xAs.This can be viewed a GaAs lattice in which a fraction x (the mole fraction) of Ga ions is replaced substitutionally by Al ions. The

structure of the lattice remains qualitatively unchanged. Its properties lattice constant, band-gap, deformation potential, etc. can

be linearly interpolated between AlAs and GaAs, at least in the simplest approximation called the virtual crystal approximation, in

which the distribution of Al and Ga ions is seen as a regular sub-lattice, without fluctuations.

The attractive features of heterojunctions and structures based on them, called heterostructures is the ability to control them

during growth at the level of single atomic layers via molecular-beam epitaxy and the possibility of designing almost arbitray

configurations of band discontinuities the so-called band-gap engineering. The figure above shows how the conduction and valence

bands of many cubic semiconductors line up as a function of their lattice constant.

HEMTs or MODFETs are basically MOSFETs based on III-V semiconductor devices. Two are the majordifferences between HEMTs and Si MOSFETs:

1. Because of the lack of a good insulator for III-V materials (as we have mentioned above), the insulator(typically, SiO2) is replaced by a larger band-gap III-V material. For example, AlxGa1xAs on GaAs. Thismaterial acts as a sort of insulator albeit with a reduced barrier.

2. A high carrier mobility is obtained by leaving the channel undoped. Electrons are induced in the channel by amethod called modulation doping: During the growth of the AlxGa1xAs layer (usually carefully controlledat the mono-layer level using molecular-beam epitaxy, MBE), the growth is interrupted, a monolayer of dopantis deposited, and the growth of AlxGa1xAs is resumed. This thin sheet of dopants (called delta-doping,since its profile approximates a Dirac delta-function) causes an excess of electrons in the otherwise undopedlayer. Because of the potential barrier at the AlxGa1xAs -GaAs interface, these electrons spill over intothe GaAs channel (as we have seen when considering hetero-junctions at equilibrium) and constitute theconductive charge in the channel. The fact that the channel remains undoped enhances the electron transportproperties, since Coulomb scattering is highly reduced. Only scattering with the remote ionized impuritiesremains.


These devices operate very much like a MOSFET, but have extremely large mobilities (up to 1.5 106 cm2/Vsat a temperature of 4.2 K, 8,000 at room temperature for GaAs channels) and are well suited to high-frequencyapplications. (Here at UMass Sigfrid Yngvesson has used the properties of GaAs 2DEG to design ballistichot-electron bolometers). The high quality of MBE-grown interfaces also minimizes surface-roughness and therelated mobility reduction. Their major drawback is due to the low values of the semiconductor-insulatorinterfacial barrier, typically only a few tenths of an eV. The large gate current prevents large signal applications.Also, an additional scattering process is present in alloyed channels (as in InxGa1xAs channels): The virtualcrystal approximation ignores fluctuations of the distributions of In and Ga ions. But these fluctuations, alwayspresent, cause the electrons to feel a random potential due to the substitution of Ga ions by In ions at randomlocations. This causes an additional scattering process whose rate is proportional to V x(1 x)(E), where(E) is the DOS at energy E and V is an average difference between the ionic potentials of In and Ga (or,in other words, the conduction-band discontinuity between InAs and GaAs). For alloys with high mole fractions(x 0.5), this process may be significant in depressing the mobility.The figure on the next page shows schematically the HEMT structure and the band-edge configuration.


Frequency response of FETsLets now briefly mention two figure-of-merits usually employed to gauge the frequency response of MESFETs.A similar characterization may also be made regarding MOSFETs.The fundamental characteristic time scale of intrinsic devices (that is, ignoring parasitic effects) is the transittime of carriers across the channel. Depending on whether we are in the linear region (velocity controlled bythe mobility times the drain-to-source field F ) or in velocity saturation, this is given by:

=L

F L

2

VD, (646)


and

=L

vsat, (647)

respectively. In saturation most semiconductors have vsat 107 cm/s, so that 1011 s for L 1m.Therefore, the maximum frequency at which the device is able to repond to the ac signal by filling and emptyingthe channel is:

fT =1

2=

vave

2L=

gm

2CGS, (648)

recalling that gm/CGS gm/Cox is an average carrier velocity in the channel. Clearly, in saturationvave vsat. The frequency fT is called the threshold or cut-off frequency. Also commonly used is themaximum frequency of the oscillation:

fmax =fT

2r1 + fT3

, (649)

where r1 = (RG + Ri + RS)/Rch is the ratio between the input resistance (Ri = IG/VG is thegate input resistance, usually extremely large; RG is the resistance of the gate contact; RS is the S/D seriesresistance; Rch, usually low when the device is on, is the channel resistance) and 3 = 2RGCGD is yetanother time constant. (The definitions of fT and fmax are given in terms of unit maximum gain and unilateralgain, respectively, for forward power amplifiers.) Note that a reduction of gate-length L results in both areduction of the transit time as well as an increase of transconductance.


Bipolar Devices

So far the transistors we have considered have been field-effect devices in which the currents of interest werecarrier by only one type of carriers: Electrons in n-channel devices, holes in p-channels. They were unipolardevices. Now we shall consider transistors in which the relevant currents are carried by both electrons and holes,bipolar transistors. We shall consider bipolar junction transistors (BJTs) and heterojunction bipolar transistors(HBTs).

Bipolar Junction Transistors.BJTs are the first type of transistors actually made, in 1947, by Bardeen, Shockley, and Brattain, at BellLaboratories. (For this they received the Nobel Prize in 1956.) The first transistor, a rather gigantic discretedevice by todays standard, was essentially a pair of p-n junctions butted together. The essence of BJTs hasnot changed since. They have been and still are the preferred devices for high-power applications, thanks totheir ability to carry large currents at high voltage. However, up untill the late 1980s they were also used in thelogic circuits of large mainframe computers. It was only with the advent of CMOS technology and because ofthe incredibly fast performance-growth of MOSFETs that it became economically and financially preferable touse CMOS technology also in logic applications (read: computers). Also, BJTs are never fully off devices, asMOSFETs. They switch from strongly on to less strongly on. The high power dissipated by BJTs, comparedto MOSFETs, made them unstuitable for very large scale integration at the quarter-micron scale.The principles of operation of BJTs are a little less intuitive than that of MOSFETs. Indeed MOSFETs wereconceived already in the early 1930s. The first MOSFET was fabricated only some 30 years later because of thedifficulty in producing reliably a good gate insulator. BJTs, not having to depend on high-quality SiO2, camefirst, as we said above.The first BJT of Bardeen, Shockley, and Brattain was a discrete device. In its LSI version, a planar n-p-n BJTis illustrated in the figure below (at left). The n-p-n doping (at right) of the two back-to-back junctions is alsoshown. These figures show n-p-n BJTs. BJTs can also fabricated in a complementary arrangement, p-n-p.We shall now consider in detail an n-p-n devices. Obviously, p-n-p will behave in a fully symmetric way.


Current gain.The figure above shows the basic band-diagram of an n-p-n BJT. We now deal with the basic current-voltagerelationship of the BJT following the discussion of an ideal p-n junction (see Lecture Notes, Part 2, pages105 and ff.). Looking at this figure, the n region at left is called the emitter, the central, narrower pregion is called base, the n region at right is the collector. Often, a heavily doped n+ region at the farright is called subcollector. Basically, applying a bias VBE between the emitter and the collector, if theemitter-base junction is unbiased we prevent the electrons from flowing from left to right. The device is off,as for a MOSFET below threshold. If we now apply a positive bias, VBE, at the base, we forward-biasthe emitter-base junction and lower the barrier in the central base region and allow flow of electrons intoit. Simultaneously, holes flow from the base to the emitter. If both emitter and base are long that

is, Lbase > Ln = (DBnBn)1/2 and Lemitter > Lp = (DEpEp)

1/2 (where DBn, Bn, DEp,and Ep are the electron and hole diffusion constants and recombination lifetimes in the base and emitter,respectively), then electrons will recombine with holes in the base, holes with electrons in the emitter and wewill have just a base and emitter current. If, however, the base is short enough, not all electrons will recombinein the base and some may make it across it. Most modern BJTs are such that a vast majority of electronsactually cross the base and enter the collector. In this case we see that the higher VBE will be, the higherthe flux of electrons from emitter to collector will be (and so the current ICE from collector to emitter willincrease). A negative (reverse) bias across the base-collector junction will make sure that electrons are sweptinto the collector by a large field. The bias situation VBE > 0 and VBC < 0 is called forward operationand it the commonly used mode of operation of a BJT. In this mode of operation the base bias, in a way,behaves like the gate bias of a MOSFET. The major qualitative difference is that, unlike a well-temperedMOSFET which has negligible or no gate current, in the BJT there will be a significant hole current fromthe base to the emitter. Since this current will be generally much smaller then the electron current ICE, wecan have a large current gain IC/IB (where IB and IC are the total base and collector current. Also, ICcan be very large indeed. Hence, both the speed and power-handling capabilities of a BJT. From the usualconvention about the sign of the current (along the flow of positive charge, opposite to the electron flow, and


current being defined as positive when entering the contact), we have

IC + IB + IE = 0 . (650)

Since BJTs are designed so that IB

The BJT as an amplifier.To see how an n-p-n bipolar transistor may be used as an amplifier, lets look at the diagram above: Considera voltage source applying an input Vin between base and emitter. The output voltage Vout is measuredbetween collector and emitter. Looking at the figure above we obviously have:

Vin = RSIB + VBE , (654)

andVCC = RLIC + VCE . (655)

Since IC = FIB, we have:

Vout = VCE = VCC FRL

RS(Vin VBE) . (656)

For a small variation of the input voltage, VBE will not change significantly, since the voltage across a forward-biased p-n junction (the base-emitter junction) is almost constant (the curent grows exponentially, so a large


change in the current causes a negligibe change of voltage). For Si diodes, VBE 0.7 V. Therefore, we seethat a small variation Vin of the input voltage is converted into a variation Vout = F (RL/RS)Vin,so it is amplified by a factor F (RL/RS) with a phase-shift of .

Basic current-voltage relationship.Lets get into some detail following a model proposed by Ebers and Moll. This model is based on the sameset of assumptions we have employed to calculate the current-voltage characteristics of an ideal p-n junction,mainly: No generation/recombination in the depletion regions, low-level injection, and Boltzmann statistics.As we can see in the figure above showing the band diagram of a BJT, most of the voltage-drop occurs inthe depletion regions. The neutral base region is almost field-free and the equations controlling the transportof electrons (the minority carriers in the base) will be dominated by diffusion. If x is the coordinate along theaxis normal to the junctions, the electron continuity equation in the base at steady state will be:

0 =n

t=

1

e

Jn

x n(x) nB

Bn, (657)

where nB is the equilibrium concentration of minority electrons in the p-type base,

Jn = eDBnn

x, (658)

Jp = Jtot eDBnn

x. (659)

From Eqns. (657) and (658) we get

2n

x2=

n(x) nBDBnBn

. (660)

Recalling that L2Bn = DBnBn, the solution can be written as:

n(x) = nB + A exp

(x

LBn

)+ B exp

( xLBn

). (661)


The integration constants A and B are determined by the fact that at the edges of the base, x = 0 andx = wB, the electron concentration is fixed by the Boltzmann factors:

n(0) = nB exp

(eVBE

kBT

)n(wB) = nB exp

(eVBC

kBT

)(662)

(note that in the normal forward operation n(wB) 0, since VBC

+ AenBDnB

LBn tanh(wB/LBn){exp[eVBC/(kBT )] 1} , (664)

where A is the cross-sectional area of the device. Similarly, the electron current to the emitter will be theelectron diffusion current evaluated at x = 0:

IEn = eDBndn

dx

x=0

= A enBDnBLBn tanh(wB/LBn)

{exp[eVBE/(kBT )] 1} +

+ AenBDnB

LBn sinh(wB/LBn){exp[eVBC/(kBT )] 1} , (665)

The hole concentration in the emitter and collector can be found easily from the theory of p-n junctions:

p(x) = pE + pE

[exp

(eVBE

kBT

) 1]

exp

(x + lE

LEp

)for x < 0 , (666)

and

p(x) = pC + pC

[exp

(eVBC

kBT

) 1]

exp

(lC xLCp

)for x > wB , (667)

where pE and pC are the equilibrium minority-carrier (hole) concentrations in the emitter and collectorrespectively and lE and lC are the edges of the emitter-base and base-collector depletion regions,respectively. Therefore the emitter and collector hole currents can be calculated by taking the derivatives withrespect to x of these expressions at lE and lC , respectively:

IEp = AeDEpdp

dx

x=lE

= A eDEppELEp

[exp

(eVBE

kBT

) 1], (668)

ICp = AeDCpdp

dx

x=lC

= AeDCppC

LCp

[exp

(eVBC

kBT

) 1]. (669)


(Note that in the normal forward operation the base-collector junction is strongly reverse-biased (VBC

We have so far assumed implicitly constant doping in the base. Lets now consider a graded doping profile in the base, NB droppingfrom x = 0 to x = wB . Since the acceptor concentration varies in the base, the hole density will vary as

p(x) NB(x) = ni exp{

[Ei EF (x)]/(kBT )}, (672)

where Ei is the intrinsic Fermi potential and EF (x) the Fermi energy. Therefore, we have a built-in field

Fbi(x) = dEFdx

=kBT

e

1

NB

dNBdx

. (673)

Equation (658) expressing the electron current across the base will now become:

JBn = eBnn Fbi(x) + eDBnn

x, (674)

or, using Eq. (673):

JBn = eDBn

(n

x+

n

NB

dNBdx

)=

eDBnp

(pn

x+ n

p

x

)=

eDBnp

(np)

x, (675)


having assumed p NB. Ignoring recombination in base (OK if the base is thin enough), we can integrate this equation as follows:

JBn

xx

pdx

eDBn=

xx

d(pn)

dx= p(x

)n(x

) p(x)n(x) . (676)

Now,

p(0) n(0) = n2i exp

(eVBEkBT

)and p(wB) n(wB) = n

2i exp

(eVBCkBT

). (677)

Therefore, from Eqns. (676) and (677) we get:

JBn =en2i DBn wB0 pdx

[exp

(eVBCkBT

) exp

(eVBEkBT

)]. (678)

Lets now assume that the electron mobility, and so the electron diffusion constant DBn, do not depend on x. This ignoresthe effect of scattering with ionized impurities which, obviously, is position-dependent if the doping is non-uniform. Defining

QB = e wB0 NB(x) dx (the total charge per unit area due to dopants in the base, called the base Gummel number) and

JS = e2n2i DBn/QB , we have finally:

JCn JEn = JBn = JS[

exp

(eVBCkBT

) exp

(eVBEkBT

)]. (679)

Comparing this expression with the constant-doping expression, Eq. (671) when VBC and VBE >> kBT ,

IC AeDBnnB

LBn sinh(wB/LBn)exp

(eVBEkBT

), (680)

we see that the current is modified by a factor en2i LBn sinh(wB/LBn)/(nBQB) ewBNB/QB for a thin base. Asteep doping profile will reduce QB , so it will enhance the current adding to the diffusion of electrons across the base also a drift

term in Eq. (675). Such a base makes the device a drift transistor.

The Ebers-Moll model.Equations (670) and (671) are rather cumbersome expressions. In order to simplify them and shed some


light on their physical meaning, lets define the saturation current for the emitter/base junction, IES, as themagnitude of the saturation current we get when we reverse-bias in saturation the emitter-base junction whileshort-circuiting the collector to the base. From Eq. (670), setting VBC = 0 and letting VBE , IESwill be just the term inside the first square bracket at the right-hand side:

IES =AeDEppE

LEp+

AqDBnnB

LBn tanh(wB/LBn). (681)

Similarly lets consider the magnitude ICS of the saturation current for the reverse-biased base-collectorjunction when the base is short-circuited to the emitter. From Eq. (671), setting VBE = 0 and lettingVBC , ICS will be just the term inside the second square bracket at the right-hand side:

ICS =AeDBnnB

LBn tanh(wB/LBn)+AqDCppC

LCp. (682)

From the definition of F we have:

F =IC

IE

VBC=0

=AeDBnnB/[LBn sinh(wB/LBn)]

AeDEppE/LEp + AeDBnnB/[LBn tanh(wB/LBn)]=

=

{cosh

(wB

LBn

) [1 +

pEDEpLBn

nBDBnLEptanh

(wB

LBn

)]}1. (683)

Similarly, defining a reverse common-base gain R:

R =IE

IC

VBE=0

=

{cosh

(wB

LBn

) [1 +

pCDCpLBn

nBDBnLCptanh

(wB

LBn

)]}1, (684)


so that the Ebers-Moll equations (670) and (671) can be written in the more compact form:

IE = IES[exp

(eVBE

kBT

) 1]

+ R ICS

[exp

(eVBC

kBT

) 1], (685)

and

IC = F IES

[exp

(eVBE

kBT

) 1]

ICS[exp

(eVBC

kBT

) 1]. (686)

In matrix form, Eqns. (685) and (686) can be recast as:

[IEIC

]=

[ IES RICSFIES ICS

] [exp[eVBE/(kBT )] 1exp[eVBC/(kBT )] 1

]. (687)

These equations constitute the Ebers-Moll model. Supplemented by Kirchoff law, Eq. (650), they can be usedto calculate the current-voltage characteristics of a bipolar transistor for any arbitrary bias configuration. Themodel depends on four parameters, IES, ICS, F , and R, of which only three are independent thanks tothe reciprocity relationship:

F IES = R ICS =AeDBnnB

LBn sinh(wB/LBn), (688)

which can be immediately derived from the pair of Eqns. (681) and (683) and from the pair of Eqns. (682)and (684).We can interpret the Ebers-Moll equations as describing the current-voltage characteristics of a pair of diodes.In the common forward operation, the first diode is the forward-biased emitter-base n-p junction with forwardcurrent:

IF = IES[exp

(eVBE

kBT

) 1]. (689)


The second diode is the reverse-biased base-collector p-n junction with reverse current:

IR = ICS[exp

(eVBC

kBT

) 1]. (690)

Inserting Eqns. (689) and (690) into Eqns. (685) and (686) we get:

IE = IF + RIR and IC = IR + FIF (691)

This form of the Ebers-Moll model is more transparent than the expressions Eqns. (670) and (671), butit is seldom used, since the parameters IF and I

R cannot be measured. In order to reformulate the

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