memristorpaper

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AbstractNovel nonvolatile universal memory technology is essential for providing required storage for nano computing.As a potential contender for the next-generation memory, the recently found the missing fourth circuit element,

memristor, has drawn a great deal of research interests Thispaper discussesstartingfrom basicwhat is memristor,itsdesignequations,keyelectricalmemristor devicecharacteristicsrelevanttomemoryoperations.

Index TermsCharge-controlled memristance, flux-controlled memristance, zero-net charge injection, zero-net flux

injection.

I. INTRODUCTION

VERY recently, a new device with pinched hysteresis was demonstrated [1][2], which was recognized as thefirst real-life realization of the so-called missing fourth circuit element, memristor. As a new nanometer device,

memristor has drawn a significant interest from the research community [3][4]. Memristor was first theoreticallypredicted by L. Chua in 1971 [5]. The concept of memristor gained a broader scope in a series of works such as

those of L. Chua and S. M. Kang [6][8]. In late 2008, S. Williams et al. unveiled a two-terminal titanium dioxide

nanoscale device that exhibited memristive characteristics, thus igniting renewed interest in memristors. There exists

a great interest in searching for the next generation of universal memories, which are able to ubiquitously replace

traditional DRAM, SRAM. The nonvolatile nature of memristors makes them an attractive candidate for the next-

generation memory technology. Memristor memories may have greater data density than hard drives with access

times potentially similar to SRAMs. It has been shown that memristor devices can be scaled down to 10 nm or

below and memristor memories can achieve an integration density of 100 Gbits/ , a few times higher thantodays advanced flash memory technologies [9] [10].More broadly, research has been done aiming at employing

memristors in programmable logics [11][12], and analog circuit applications [13][14]. In the meantime,

researchers have found that LC electronic networks with memristors can model adaptive behavior of unicellular

organisms. Results have indicated that electronic circuits with memristors subjected to a train of periodic pulses

behave like brain functions, which are able to learn and anticipate. Such a learning circuit may find its valuable

applications in a variety of areas, e.g., neural networks and artificial intelligences [15][19]. In thispaperwe

systematically develop a rather complete set of properties and design equations for guiding the development of

memristor based memories. Then by utilizing these memristor properties as design guidance, we then investigate

the design of memory read/write schemes and peripheral circuits.

Well-understood basic circuit elements, resistance, capacitance, and inductance, describe the relations between

fundamental electrical quantities: voltage, current, charge, and flux [18]. Resistance relates voltage and current

(dv=R.di) capacitancerelateschargeandvoltage (dq=C.dv),andinductance relates flux and current (d=Ldi ) ,

respectively. As shown in Fig. 1, Chua argued that there is a missing link between flux and charge (d=M.dq) ,which he called memristance [5].By definition, a linear (constant) memristor acts like resistance. However, if

(-q ) relation is nonlinear, the device behavior is more complex. A charge-controlled memristor characteristics,referred to as memristance, can be described as [5]

MEMRISTOR

MEMRISTOR


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Fig. 1. Four fundamental circuit elements: Resistance (dv=R.di) , capacitance (dq=C.dv) , inductance (d=Ldi ) , and memristance

(d=M.dq) which is the missing link that Chua argued.

Fig. 2. (a) Memristor device structure. (b) Equivalent circuit model [4]. (c) Symbol for memristor.

Similarly, when the relation is flux-controlled and the element is called memductance

From (1) and (2), it can be also seen

The memristance in (3) M(q) is equal to voltage over current which is also known as the resistance in the linear

case. Therefore, memristance has the same unit (ohm) as resistance, and M(q) is logically a charge-controlled

resistance. Similarly in (4), the memductance has the unit of conductance. The inverse of memductance would be

memristance,


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Property 1: corresponds to memristor state w=D . corresponds to w=0 memristor state . The deviceresistance is bounded between: .

Fig. 2(a) and (b) show the physical structure of a memristor device alongwith its equivalent circuit model .

The device is an electrically switchable semiconductor thin film sandwiched between two metal contacts. There are

two layers in the titanium dioxide film. The semiconductor thin film has a certain length , and consists of two layers

of titanium dioxide films. One is highly resistive pure Ti

(undoped layer), and the other is filled with oxygen

vacancies, which makes it highly conductive (doped layer). The state variable w represents the width of the doped

region (Ti layer). The doped region has low resistance while that of the un-doped region is much higher. As anexternal voltage bias v is applied across the device, the electric field will repel positively charged oxygen vacancies

in the doped layer into the pure Ti layer resulting the length w changed . Hence, the devices total resistivitychanges. If the doped region extends to the full length D , that is ,w/D=1.0 the total resistivity of the device would be

dominated by the low resistivity region, with a value measured to be . Likewise, when the undoped regionextends to the full length D , i.e.,w/D=0 the total resistance is denoted as . According to [5], the memristor hasmemory effect since the device maintains its resistivity even if the power goes off. According to the reported device

characteristics [5], [7], oxygen vacancies donot move around by themselves. They become absolutely immobile until

voltage is applied again. This unique characteristic makes the memristor standout from other devices such as diode.

The mathematical model for memristive device resistance can

be described as

(6)

( ) Or it can be written as

Because of physical constraint 0 D,Property 1 is concluded.

Fig. 2(c) shows the memristor symbol used in a circuit schematic. The orientation of the symbol follows the

equivalent circuit in Fig. 2(b), where is at the left and is at the right. The polarity matters in memristorcircuits. If a bias condition excites the memristance to increase, the reverse connection of memristor would decrease

the memristance, which is also equivalent to reverse the polarity of the biasing source. Using this resistive

viewpoint, we have

v= R(w).i (8)

Referring to Fig. 1, (8) presents the relation of voltage and current.

Memristors can be charge controlled or flux controlled depending on the biasing condition [16][17]. More

specifically, when a memristor is connected to a current source, the current source will inject charges through the

memristor cell. It is convenient to treat such a memristor as charge controlled because the state of the memristor

changes according to the amount of charge injection, and the state causes memristance to change .On the other hand,

when a voltage source is added across a memristor, it is natural to consider the memristor as flux controlled. In this

case, the state of the memristor changes according to the amount of flux injection, and the state causes memristance

to change.

A. Charge-Controlled Memristance

For a charge-controlled memristance, the memristor state controlled by the charge through the cell, and the state of

memristor determines memristance.


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Property 2: The state (length of the doped region) is charge controlled and can be described as follows:

(9)where is the initial state, D is the memristor length, is the average ion mobility, and q is injected charges. is the upper limit of effective charge injection, and is the lower limit of effective charge injection.B. Flux-Controlled Memristance

For a flux-controlled memristance, the memristor state is controlled by the flux across the cell, and the state of the

memristor drives memristance.

Property 3: The state (length of the doped region) is flux controlled and can be described as follows:

[ ]

(10)Where denoted the off/on ratio, is the initial state, D is the memristor length, is the averageion mobility and is injected flux. is the upper limit of effective flux injection; is the lower limit ofeffective flux injection, and

Property 4: The memristor state is initially at . Suppose the state of memristor is desired to move to a feasiblestate w by a square-wave voltage pulse that has amplitude and width , the required width is

(11)Corollary 4.1: Suppose a voltage square-wave pulse has amplitude and width is applied to a memristor. Theduration needed for memristor state to move from w=0 to w = D is the same as what is required to move the state

from w=D to w=0 , and the required duration

is

(12)Property 4 addresses how much time is needed to move memristor state from an initial to any state w. Assumememristor state be initially at state .Based on (10) fromProperty3, suppose the state of memristor is desired tomove to an arbitrary state w, the applied flux needed across the memristor to do this job is

(13)


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Let the applied voltage be a square-wave pulse with amplitude and width , the flux across the memristor isdescribed as follows:

{

(14)When time is in between zero and , the voltage magnitude is and flux is accumulating in this time range.When time goes beyond , the voltage magnitude is zero, so no more flux increment beyond time . Hence, thetotal flux injection for a square-wave pulse is the amplitude times the width which is . in this case. The totalflux injection determines the change of memristor state. By utilizing (13) and (14), the required width needed to

move memristor state from to w is concluded inProperty 4. As a special case, the required time needed to movememristor state from w= 0 to w= D is the same as to move from w = D to w =0. This leads to Corollary 4.1.

Fig. 3. A voltage divider consisting of a constant resistor in series with a flux-controlled memristor. [21]

Property 5: For the circuit in Fig. 3, assume the voltage source is a square-wave pulse with amplitude and awidth . To move the state of the memristor from to w, the required width is (15)Corollary 5.1: For the circuit in Fig. 3, assume the voltage source

is a square-wave pulse with amplitude

and

a width

. The duration needed for the memristor state to move from w=0 to w=D is the same as what is needed

to move the state from w=D to w=0, and the required duration is (16)Property 5 specifies the time needed to move the memristor state from an initial tow for the divider circuit shownin Fig. 3. Note that the flux across memristor is , and ] = (17) [21]We then substitute into (17) and yield the following analytical form: (18)Equation (18) reveals the amount of flux injection needed to move the memristor state from to w . Suppose theapplied voltage is a square-wave pulse has amplitude and width , (15) follows directly from (18). As aspecial case, to move the state from to w requires the same as what is needed to move from state tow = D. This leads to Corollary 5.1.


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A memristor has an effective flux restriction due to finite length D. Property 3 demonstrates the effective rangefor a single memristor case. WithProperty 3 in mind, the total input flux-injection across memristor and aresistor should have a range as well. The upper bound of such effective range is the amount of flux that pulls initial

state to D. Thus, substituting w = D into (18) gives the upper bound. Likewise, substituting w=0 into (18) givesthe lower bound. This result is summarized inProperty 6.

Property 6: When a memristor is connected in series with a resistor as shown in Fig. 6, the effective range for across both memristor and resistor is (19)Where is integral of and,

Property 7: Consider the circuit in Fig. 3 and assume the voltage source has a zero-net-flux injection pattern.The memristor state will move back to the initial level provided that the applied input flux is within the effectiverange in (19).Finally,Property 7shows that a zero net-flux input voltage pattern will insure that the state of the memristor

comes back to the initial position for the circuit shown in Fig. 3. Note that here the zero-net-flux condition is

specified for the input voltage to the circuit of Fig. 3. Hence, it provides important design guidance for ensuring read

stability as discussed in detail in later sections. To prove Property 7, we set equal to zero in (18) and solve forpossible solutions for R(w) . Two possible numerical solutions exist: one is w= , and the other solution is outsideof the memristor physical range. Therefore, the first solution is the only valid solution, which also implies that the

state will be back to the initial level as w=. However,Property 7is true only when the effective flux rangecondition as inProperty6is satisfied.

III. MEMRISTORBASED MEMORY CIRCUIT

Using the results developed in the previous sections, we propose read/write schemes for memristor memories and

discuss circuit design issues associated with read write stability and data integrity.

A. Output Levels

For simplicity, we define a memristor is at logic zero when 0< w/D< 0.5 and logic one when 0.5 < w/D < 1 . The

corresponding ideal output low and high levels are w/D =0 and w/D =1 , respectively. In reality, to account for

possible noise injections, a safety margin is specified for each logic output: ) ,for logic zero, and

for logic one. The region in between

is an

unsafe region that should be avoided for read/write data integrity. Fig. 7 illustrates the situation where and =0.6 .B. Memristor Memory Write Operation

To write a logic value to a memristor cell, one simple way is to have a structure in Fig. 5, where the memristor is

considered as flux-controlled and flux injection will alter the memristor state. Assume initially the state is , and it is desirable to write logic one to the cell. For the write process, input voltage generates a square-wave


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Fig. 4. A memristor biased using voltage source

pulse that has magnitude + and width as shown in Fig. 6. Pulse width must be longer than the minimumrequired time to insure the state rest inside the logic one region after write .We determine the minimumrequired time usingProperty 4 by substituting and w = into (11) || (20)

Fig. 5. Memristor output levels. In the illustration above, the output low margin

is at 0.4 and output high margin is at 0.6 [21].

Fig. 6. Write signals (bottom) and corresponding memristor states (top).

If the initial state is not at but somewhere inside the logic 0 region, a successful write can beguaranteed as long as . Similarly to write logic zero, the input voltage is a negative square-wavepulse (- ) with duration as shown in Fig. 5(b). The minimum required time would be


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|| (21)

The write zero process would be successful if pulse width is at least greater than . Thus, a write signalthat has duration equal or larger than the derived minimum required time can insure a successful write.

Moreover, we refer to the memristor state w=0 and w=D as ideal logic zero and one states. Equation (12) fromCorollary4.1 specifies the required pulse widths to move a state from to w = D or move from tow = 0. Therefore, the write pulse is highly recommended to have the width in (12) so the state reaches the ideal logic

zero/one state.

C. Memristor Memory Read Operation

The read operation is not as simple as the write operation. In order to extract the information of the internal state, we

need to apply a voltage, which will perturb the memristor state. If the read mechanism is not well designed, the

memristor state may be perturbed; and soft error can occur after multiple read operations.

The proposed memristor based memory cell structure is in Fig. 7.Both the read and write operations are based on

such memory structure. In write, the R/W Enable (R/W) switches to ground. For a read, R/W switches to . A readis performed in two stages: convert stage and sense amplifier stage. The convert stage senses the memristor state andproduces a voltage signal, which is further amplified into a full -swing digital output by the sense amplifier.

The designed read signal pattern has a negative pulse followed by a positive pulse with equal magnitude and

duration as shown in Fig. 8. Based onProperty 7, this read pattern will enforce zero net flux injection over one

period to avoid altering memristor state after a read access.

FromProperty 7, the output is produced by the voltage divider from fig 3 is given by (22) [21]

When no input flux injection , (22) becomes


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Fig. 7. Circuit structure for a memristor based memory cell. Read/Write enable (R/W) switches to ground for write process; it switches onto for read process. The comparator in the Sense Amplifier stage compares with reference voltage . is half of . If , output is which represents logic 1. Similarly, is if .

Fig. 8. Graphical illustration for the read scheme . (top) Read pattern, memristor state, and output when memristor stored logic zero state.(bottom) Read pattern, memristor state, and output when memristor stored logic one state.It clearly shows that is a voltage output of divider formed by and R (). Due to the zero net flux injection,memristor state stays the same as the initial state, R(w) = R( ) at the end of each read cycle. needs properly designed to distinguish logic zero and one. is set so that the output level is at when thememristor state is at half of its length D . For that, designed to be the following:

is the reference voltage in fig 9. A memristor state below D/2 will result in a large resistance.Accordingly, will be below . The comparator in the sense amplifier stage will signal since .Similarly, the fact that the memristor state being higher than D/2 would result a smaller resistance. Because of that, voltage will be higher than , and would output . and are the logic one and zero voltage levels,respectively.

As shown in Fig. 8, when the memristor state is initially at logic zero, the negative pulse (from to ) woulddecrease the memristor state and the coming positive pulse (from to ) increases the state. Since the read signal


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has a zero net flux injection pattern, the state is back to the initial level after read. Because the state remains under

half of D for all the time, the memristor cell has a high resistance value. During the first half period ( to ), thelarge amount of negative voltage drop across the memristor results a less negative potential for . With respect to , would have a higher potential, so goes high during to . At the second half period ( to ), the voltage drop across is lower than due to low memristor state. Hence, output switches to during

to

. Similarly, when the memristor is at logic one, the zero net flux read signal pattern will insure the state comes

back to the initial high state, and memristor cell resistance would be low for all the time. Using a similar analysis,we can conclude that from to , the sense amplifier produces a low output while it produces a high output fromto , corresponding to logic one. As we can see, only the second half period reflects the correct logic state storedin the memristor. Therefore, the stored logic value should read out between to .V. CONCLUSIONS

In this paper, we systematically derive a comprehensive set of properties and analytical solutions for characterizing

the fundamental electrical properties of memristor devices. Using our derived properties, we investigate the design

of read/write circuits. In addition to memory applications, derived analysis can be further extended to provide a

basis for understanding the characteristics of memristor devices in a wider range of applications.

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