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Penn ESE370 Fall2012 -- DeHon 1

ESE370: Circuit-Level

Modeling, Design, and Optimization for Digital Systems

Day 28: November 16, 2012 Memory Periphery

Today

Memory Periphery •  Driving •  Decode •  Sensing •  Energy (time permitting)

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Bus Drivers

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Memory Bank

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Tristate Driver

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Tri-State Drivers

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Memory Bank

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Row Select

•  Logically a big AND – May include an enable for timing in

synchronous

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How tall is a row?

•  Side length for cell of size: – 1000 λ2

–  600 λ2

–  100 λ2

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How tall is an AND?

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2λ

6λ 6λ

3λ

2λ

λ λ

2λ

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Row Select

•  How can we do better? – Area – Delay – Match to pitch of

memory row

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Row Select

•  Compute inversions outside array – Just AND appropriate line (bit or /bit)

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Row Select •  Share common terms •  Multi-level decode

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Row Select

•  Same number of lines •  Half as many AND inputs

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Row Select: Precharge NAND

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Row Select: Precharge NOR

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Sensing

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SRAM Memory bit

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Simulation Waccess=20

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Sense Small Swings

•  What do we have to worry about?

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Sense Small Swings

•  Variation •  Common mode noise

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Differential Sense Amp

•  Goal: – Reject

common shift

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Differential Sense Amp

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What doe this do?

•  Output when: –  In=Gnd? –  In=Vdd? – Transfer curve?

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“Inverter”

•  Input high – Ratioed like

grounded P •  Input low

– Pulls itself up – Until Vdd-VTP

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DC Transfer Function

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Differential Sense Amp

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Diffamp Transfer Function

•  in=/in, looks like “inverter” •  Deliberately

low gain in mid region

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Differential Sense Amp

•  “Inverter” output controls PMOS for second inverter

•  Sets PMOS operating point – current

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Differential Sense Amp

•  What happens when o In=/in ? o /in > in? o /in < in?

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Differential Sense Amp

•  View: – Current mirror – Biases where inverter

operating

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Differential Sense Amp

•  View: –  adjusting the pullup

load resistance – Changing the trip

point for “inverter”

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DC Transfer /in with in=0.5V

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DC Transfer Various in

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DC Transfer Various in •  What is trip

point when: •  In=0.3V? •  In=0.4V? •  In=0.5V? •  In=0.6V? •  In=0.7V?

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After Inverter

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Ramp 50mV Offset

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Closeup 50mV Offset

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Connect to Column

•  Equalize lines during precharge

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Singled-Ended Read

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5T SRAM

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Single Ended

•  Given same problems – How sense small swing on single-ended

case?

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Single Ended

•  Need reference to compare against •  Want to look just like bit line •  Equalize with bit line

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Split Bit Line

•  Split bit-line in half •  Precharge/equalize both •  Word in only one half

– Only it switches •  Amplify difference

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Open Bit Line Architecture

•  For 1T DRAM •  Add dummy cells •  Charge dummy cells to

Vdd/2 •  “read” dummy in

reference half

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Memory Bank

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Energy

(Time Permitting)

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Single Port Memory

•  What fraction is involved in a read/write?

•  What are most cells doing on a cycle? •  Reads are slow

– Cycles long lots of time to leak

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ITRS 2009 45nm

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High Performance

Low Power

Isd,leak 100nA/µm 50pA/µm Isd,sat 1200 µA/µm 560µA/µm Cg,total 1fF/µm 0.91fF/µm Vth 285mV 585mV

C0 = 0.045µm × Cg,total

High Power Process

•  V=1V d=1000 γ=0.5 Waccess=Wbuf=2 •  Full swing for simplicity •  Csc = 0

–  (just for simplicity, typically <Cload) •  BL: Cload=1000C0 ≈ 45 fF = 45×10-15F •  WN = 2 Ileak = 9×10-9 A

•  P= (45×10-15) freq + 1000×9×10-9 W Penn ESE370 Fall2012 -- DeHon

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Relative Power

•  P= (45×10-15) freq + 1000×9×10-9 W •  P= (4.5×10-14) freq + 9×10-6 W

•  Crossover freq<200MHz •  How partial swing on bit line change?

 Reduce dynamic energy  Increase percentage in leakage energy  Reduce crossover frequency

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Consequence

•  Leakage energy can dominate in large memories

•  Care about low operating (or stand-by) power

•  Use process or transistors with high Vth – Reduce leakage at expense of speed

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Idea

•  Minimize area of repeated cell •  Compensate with periphery

– Amplification (restoration) •  Match periphery pitch to cell row/column

– Decode – Sensing – Writer Drivers

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Admin

•  Monday: in Detkin Lab – Read lab2 assignment before coming to class

•  Tuesday: Proj2 Milestone due •  Wednesday: Lecture •  Thursday/Friday: Thanksgiving Holiday

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