MCU Centric * Use Slides 2 through 5, * Then add ONE of … SAT uses an ultrasonic transducer to...

Renesas Electronics America Inc. © 2012 Renesas Electronics America Inc. All rights reserved.

Class ID:

Quality/Failure Analysis

Tom Siegel, Failure Analysis and Quality

OC12I

© 2012 Renesas Electronics America Inc. All rights reserved. 2

Tom Siegel: Senior Manager, Failure Analysis and Quality

Education

MBA: Indiana University (2004)

BSEE: Gannon University (1983)

Twenty-nine (29) Years Semiconductor Industry Experience

4 Yrs: Delco Electronics - Kokomo, IN

– Microprocessor and ASIC Development

3 Yrs: Elgin Electronics – Erie, PA

– Design Engineering for Telecommunications Power Products

– Purchasing Manager

18 Yrs: Delphi Delco Electronics – Kokomo, IN

– Microprocessor and ASIC Development Manager

– Materials Engineering Manager

– Failure Analysis Manager

4 Yrs: Renesas Electronics

– New Business Development Manager

– Mixed Signal Development Manager

– Failure Analysis and Quality Manager


Renesas Technology & Solution Portfolio


Glossary of Acronyms

Renesas quality performance

Automotive Industry Requirements

Requested timing for analysis

Renesas Global Quality Support Structure

Failure Analysis Flow

Mechanical inspection

Electrical testing

Fault isolation

Physical analysis

Requested information from customers to ensure successful analysis results

Minimize No-Trouble-Found (NTF) analysis results

Agenda: Automotive Quality/Failure Analysis



Renesas Quality Performance






Electrical testing

Fault isolation

Physical analysis






ATE – Automated Test Environment

BGA – Ball Grid Array

CAD – Computer Aided Design

DFM – Design for Manufacturing

DFR – Design for Reliability

DFT – Design for Test

FDT – Fault Diagnosis Tool

FIB – Focused Ion Beam

GDS – Graphic Database System

IR-OBIRCH – Infra Red - Optical Beam Induced Resistance Change

OBELISCH – Optical BEam induced LogIc State Change

SAT – Scanning Acoustic Tomography

STEM – Scanning Tunneling Electron Microscopy









Electrical testing

Fault isolation

Physical analysis





• Approval (same quality as Renesas)

• Continuous Quality Improvement

• Change Control

• Nonconforming Control

To prevent

defects

outflow

To prevent

defects in

each process

Fast Analysis and

Feedback

Zero Defects

P lan D o C heck A ction

Global Quality Leader – The Drive to Zero Defects

Subcontractors outside Renesas

• Unified Quality System

• Continuous Quality Improvement

Quality Management

Continuously improve the Quality of Products towards Zero Failure Target ･by expanding Best Practice for Company-wide Activities with Benchmarking

･by carrying out strict quality control of subcontractors with strong relationship


Continuous Auto MCU* Quality Improvement

Renesas realized less than 1ppm level of defects in 2009 – 2011!

Quality Control

Feedback to Design

Feedback for

Quality Improvement

DFT (Design for Test)

DFR (Design for Reliability)

DFM (Design for Manufacturing)

Failure Analysis

Stressed Test

High Fault Coverage

Failure Chip

Design

Production

Wafer Test

LSI Test

Shipment

Short Loop TEG

for Defect Density

reduction

*Flash MCU

Outlier

Screening

2.22ppm

1.86ppm

0.95ppm

0.94ppm

0.79ppm

0.0

1.0

2.0

3.0

4.0

0

100

200

300

400

2007 2008 2009 2010 2011

Fie

ld F

ailu

re R

ate

[P

PM

]

Sh

ipp

ing

Qty

[M

pcs]

MCU Quality Performance (Auto)

(FY)


FY’07 ‘09 ‘10 ‘11 ‘12 ‘08

Fie

ld f

ailu

re r

ate

Field failure rate trends

40ppb

30ppb

39ppb

20ppb

Target

<10ppb

300M

200M

400M

Num

ber

of ship

ments

(mill

ion

s p

cs p

er

ye

ar)

Renesas’s automotive PowerMOSFETs providing

outstanding quality result in the market

19ppb

Number of shipments









Electrical testing

Fault isolation

Physical analysis





Automotive FA Response Request

Initial report: 48 hours

Final report: 14 days

Includes 8D report format and irreversible corrective action









Electrical testing

Fault isolation

Physical analysis





Dusseldorf

Tamagawa

Roseville,CA Beijing

/ Suzhou

Musashi Kitaitami

Quality assurance and failure analysis network

Global design centers and manufacturing sites

Regional direct support to each customer

Quality Support Structure for Global Customers

Renesas Electronics

Europe GmbH

Quality Center Renesas Electronics

China Co, Ltd.

Quality Center

Renesas Electronics

America, Inc.

Quality Center Renesas Electronics

Corporation

Quality Assurance Division









Electrical testing

Fault isolation

Physical analysis





Roseville FA Lab Capability

The Roseville FA Lab is fully equipped for start to finish analysis.

FA Flow Available Techniques

1) Mechanical Inspection Optical Inspection X-Ray SAT (Scanning Acoustical Tomography)

BGA Rework

2) Electrical Testing Curve Tracer Flash Programmer & debugger tools ATE Tester (Teradyne J750 512pin) FDT (Fault Diagnosis Tool)

3) Fault Isolation Photon Emission IR-OBIRCH OBELISCH Columbo CAD GDS Analysis/Overlay

4) Physical/Destructive Analysis

Delayer (Polish, Plasma & Wet Etch)

FIB STEM









Electrical testing

Fault isolation

Physical analysis





Mechanical Inspection Techniques (Optical)

Optical Inspection is used to verify the correct sample has been received and no external mechanical damage exists.

Missing Corner Pin Verify Part Number & Lot Codes


Mechanical Inspection Techniques (Optical)

Often a customer will send a PCB board with the device still attached. Bent leads can cause soldering issues in their assembly line.

Lifted Pin not soldered Solder Bridge


Mechanical Inspection (X-Ray)

Using the X-Ray, we can see inside the device to check the internal bond structures and lead frame.


Mechanical Inspection Techniques (SAT)

SAT (Scanning Acoustical Tomography)

The SAT uses an ultrasonic transducer to produce sound energy in a tank of DI water.

The sound energy penetrates the sample and the reflections are detected.

An image of the inside structure is generated by using the reflected sound energy.


Mechanical Inspection Techniques (SAT)

From the images, we can determine internal package problems such as Delamination, Popcorn, and Die Crack.

Unlike the X-Ray, the die is visible.

Good

Device

Die Crack Popcorn

Delamination









Electrical testing

Fault isolation

Physical analysis





Electrical Testing Techniques (Curve Tracer)

Test package pin electrical contact to the die.

Small signal activates the ESD protection diodes.

Waveform shape indicates the health of the device pin.

Simple test can detect

Pin Shorts

Pin Leakage

Open Failures


Electrical Testing Techniques (ATE Test)

ATE (Automated Test Equipment) Test uses current production programs for verification

Roseville has test boards for many V850, K0 and K0R devices

Tests are performed over the guaranteed operating temperature range

Typically 25C, 85C, -40C

Uses a Thermostream.

If a failure is confirmed, additional information can be found

Example - Datalog, Shmoo Plots, IDDq Analysis)

The device is placed in

the test socket inside

the thermal stream

temperature chamber

Thermostream

Tester


Electrical Testing Techniques (FDT)

Fault Diagnosis Tool (FDT) system captures differences between a reference sample and a claim fail sample running the same evaluation code.

Code executing in both devices simultaneously.

When the code reaches a specified address (Breakpoint), execution is stopped.

FDT software compares the contents of internal registers of both devices

FDT Setup

Workstation PC

Debugger Interface 1

Debugger Interface 2

FDT Dual Device Breadboard

Reference Sample

Fail Sample









Electrical testing

Fault isolation

Physical analysis





Fault Isolation Techniques (Photon Emission)

Photons are emitted when current flows across junction of a transistor

Emission analysis captures this light

Differences between the claim sample and a reference sample identify the location of the abnormal current

Device is typically initialized to the failure point identified by the IDDq analysis.

Caveat

Often the emission point is only a side effect to the actual failure location. All of the signals associated with the emission point must be considered suspect.


Fault Isolation Techniques (IR-OBIRCH)

IR-OBIRCH Infra Red - Optical Beam Induced Resistance CHange

Laser Scan Image Overlay Image

Device Under Test

A

V

IR-Laser

Scan Pattern

IDD

Defect

Detects changes in IDD current as heat is introduced

by scanning the surface of the device with an infrared

laser.

Resistance: R = (L/A) where

Resistivity: = 0(T – T0) + 0

IDD Current: I = V/R

With a constant voltage(V) applied, current(I) will

fluctuate as resistance(R) changes with temperature

Useful in detection of shorts between metal lines

where no photon emission would occur


Fault Isolation Techniques (OBELISCH)

Optical BEam induced LogIc State CHange

Laser Scan Map Superimpose with

Optical Image

SEM Cross-section

Useful for localizing defects in marginal

devices that are sensitive to temperature

Other companies may refer to it as

DAL - Dynamic Analysis by Laser

Stimulation

SDL - Soft Defect Localization

Dynamic test where the failing test pattern is

run in a continuous loop on tester

Pass/Fail result of each test sent to OBELISCH

system

IR-Laser stepped pixel-by-pixel providing

localized heating

Temperature sensitive defect will shift:

PASS FAIL or

FAIL PASS


Fault Isolation Techniques (Columbo)

Many devices use test methodology known as “Scan” testing.

If device fails scan test, “Columbo” may help localize fail point.

Columbo uses the scan datalogs and device design files

Calculates failure probability at particular signal points inside the device.

Input

1

1

1

1

1

1

1 0

output


Fault Isolation Techniques (CAD Overlay)

If many hotspots are observed by Emission/OBIRCH analysis, using CAD Overlay can help find a common link

Use a Net Tracing tool in the CAD system to search for any common nets between the Emission/OBIRCH hotspots

OBIRCH Common Net

Emission Common

Net

Both Nets run parallel to each

other.

A short is suspected here.









Electrical testing

Fault isolation

Physical analysis





Physical Analysis Techniques (Delayer)

Layer-by-Layer Etch Back is a combination of mechanical polishing, chemical etching, and plasma etching methods to remove individual layers from the sample

When to Use?

When no visual confirmation of defect can be observed

Defect area is too large for FIB cross-sectional analysis

Best imaging orientation is unclear due to feature obstruction.

– Once the defect is exposed, it may be desirable to return to FIB cross-sectional analysis method.

Pin hole damage

Top View 2nd Metal Removed 1st Metal Removed Gate Removed


Physical Analysis Techniques (FIB)

Focused Ion Beam (FIB) FIB performs precision cutting and milling

Allows a cross sectional view of the defect area.

Uses Gallium ION for the beam

Beam energy controlled to drill precise location

“Micro Sampling” system lifts out the defect area

Place in specimen holders for high magnification

SEM and TEM analysis.

Resolution: 180,000x


Physical Analysis Techniques (Delayer)

Similar to layer-by-layer Etch Back, however the FIB is used to open a window to the lower layers

Why Use?

Faster when fault area is more localized

Grounding properties of the FIB can be used to find a floating node and isolate a failure point

Much less destructive to surrounding die than layer-by layer etch back

Small defect area, unobstructed by large metal features

A window is being milled

into the die Al structures appear

after the SiO2 is milled


Physical Analysis Techniques (FIB)

Step 1 – Deposit Tungsten

Step 3 – Mill Away

Under Side

Step 4 – Attach Manipulator Step 5 – Sever Micro-

Bridge

Step 2 – Mill Away

Surrounding Area

Step 6 – Lift Away

Sample

Micro Sampling Lift-Out Technique


Physical Analysis Techniques (STEM)

Sample mounted to the specimen holder by FIB, STEM provides high resolution imaging.

Resolution: 5,000,000X

Capable of imaging in Secondary Electron (SE) and Transmitted Electron (TE) modes.

Sample thickness required to be <1um but preferred <500nm.

Image quality improves as the sample gets thinner.

Sample can be transferred between the FIB and STEM in a cycle of sample thinning and imaging.

Scanning Transmission Electron Microscope (STEM)

Ti Short between two metal lines



Once the defect is confirmed, the EDX system is used to determine the elemental composition.

Each color represents

the presence of a

different element



3D Pillar Holder

FIB is used to lift out the sample and mount it to the tip of the micro pillar.

The sample can now be rotated 360.

200kV accelerating voltage of the STEM, electron beam penetrates the surface of the sample

3D image can be created by positioning the sample off axis.

Sample Mounted

Here









Electrical testing

Fault isolation

Physical analysis





REA ABU Claims by Root Cause (12 month)

80% of FA Claims have root cause: NTF and EOS/ESD


Improving FA Results

The most challenging FA item: NTF (No Trouble Found)

Typically result from:

Production test hole

Mis-application of device

Another failed component in the system

Resolution of NTF’s can be time consuming

Understanding of customer application is essential to resolve NTF

– Customer applications are very different from production IC tester

Proper customer diagnosis is critical

– ABA swap of suspect device to known good module to verify the failure follows the device

Detailed failure information is extremely beneficial for timely resolution

– The probability of finding a failure increases as more specific details are provided for the failing device


Questions?


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MCU Centric * Use Slides 2 through 5, * Then add ONE of … SAT uses an ultrasonic transducer to...

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