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Probabilistic Soft Error Rate Estimation from Statistical SEU

Parameters

Fan Wang*Fan Wang*Vishwani D. AgrawalVishwani D. AgrawalDepartment of Electrical and Computer Engineering

Auburn University, AL 36849 USA*Presently with Juniper Networks, Sunnyvale, CA

17 th IEEE North Atlantic Test Workshop

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OutlineOutline BackgroundBackground

Problem StatementProblem Statement

AnalysisAnalysis

Results and DiscussionResults and Discussion

ConclusionConclusion

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Motivation for This WorkMotivation for This Work With the continuous downscaling of CMOS With the continuous downscaling of CMOS

technologies, the device reliability has technologies, the device reliability has become a major bottleneck.become a major bottleneck.

Sensitivity of electronic systems can Sensitivity of electronic systems can potentially become a major cause of soft potentially become a major cause of soft (non-permanent) failures.(non-permanent) failures.

There is no comprehensive work that There is no comprehensive work that considers all factors that influence soft error considers all factors that influence soft error rate. rate.

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Strike Changes State of a Single BitStrike Changes State of a Single Bit

Logic orMemoryDevice 01

Definition from NASA Thesaurus:Definition from NASA Thesaurus: “Single Event Upset (SEU): Radiation-induced errors in

microelectronic circuits caused when charged particles [also, high energy particles] (usually from the radiation belts or from cosmic rays) lose energy by ionizing the medium through which they pass, leaving behind a wake of electron-hole pairs.”

α-particleor high-energy neutron

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Impact of Neutron Strike on a Silicon TransistorImpact of Neutron Strike on a Silicon Transistor

Neutron is a major cause of electronic failures at Neutron is a major cause of electronic failures at ground level.ground level.

Another source of upsets: alpha particles from Another source of upsets: alpha particles from impurities in packaging materials.impurities in packaging materials.

Strikes release electron & hole pairs that can be absorbed by source & drain to alter the state of the device

+- ++ +-- -

Transistor Device

source drain

neutron strike

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Cosmic RaysCosmic Rays

Earth’s Surface

p

n p

p

n

n

p

p

n

n

n

Neutron flux is dependent on altitude, longitude, solar activity etc.

Source: Ziegler et al.

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Problem StatementProblem Statement Given background environment data

Neutron flux Background energy (LET*) distribution*These two factors are location-dependent.

Given circuit characteristics Technology Circuit netlist Circuit node sensitive region data*These three factors are circuit-dependent.

Estimate soft error rate in standard FIT** units.

*Linear Energy Transfer (LET) is a measure of the energy transferred to the device per unit length as an ionizing particle travels through material. Unit: MeV-cm2/mg.

**Failures In Time (FIT): Number of failures per 109 device hours

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Measured Environmental DataMeasured Environmental Data Typical ground-level neutron flux: 56.5cm-2s-1.

J. F. Ziegler, “Terrestrial cosmic rays,” IBM Journal of Research and Development, vol. 40, no. 1, pp. 19.39, 1996.

Particle energy distribution at ground-level: “For both 0.5μm and 0.35μm CMOS technology at ground

level, the largest population has an LET of 20 MeV-cm2/mg or less. Particles with energy greater than 30 MeV-cm2/mg are exceedingly rare.” K. J. Hass and J. W. Ambles, “Single Event Transients in Deep

Submicron CMOS,” Proc. 42nd Midwest Symposium on Circuits and Systems, vol. 1, 1999.

Linear energy transfer (LET), MeV-cm2/mg

Pro

bab

ilit

y d

ensi

ty

0 15 30

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Proposed Soft Error ModelProposed Soft Error Model

Occurrence rate

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Pulse Widths Probability Density PropagationPulse Widths Probability Density Propagation

1

X

Y

We use a “3-interval piecewise linear” propagation model We use a “3-interval piecewise linear” propagation model

1)1) Non-propagation, if DNon-propagation, if Din in ≤≤ττp.p.

2)2) Propagation with attenuation, ifPropagation with attenuation, ifττp p << D Din in << 22ττp.p.

3)3) Propagation with no attenuation, if DPropagation with no attenuation, if D in in 22ττp.p.

WhereWhere DDinin: input pulse width: input pulse width

DDoutout: output pulse width: output pulse width

ττp p : gate input output delay: gate input output delay

τp 2τp0 Din

Dout

fX(x)

fY(y)

Delayττpp

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Validating Propagation Model Using HSPICE Validating Propagation Model Using HSPICE SimulationSimulation

Simulation of a CMOS inverter in TSMC035 technology with load capacitance 10fFSimulation of a CMOS inverter in TSMC035 technology with load capacitance 10fF

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Pulse Width Density Propagation Through a CMOS InverterPulse Width Density Propagation Through a CMOS Inverter

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Soft Error Occurrence Rate Calculation Soft Error Occurrence Rate Calculation for Generic Gatefor Generic Gate

i

gcontrollinnonjPP iPEMRmaskingic

maskingelectrical

SEUSEU

2

)1( )]([_log

_

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Comparing Methods of AnalysisComparing Methods of Analysis

FactorsConsidered

LETSpec.

ReconvFanout

Sens. region

Occurance rate

Vectors ?

AltitudeCktTech.

SET degrad

Our work YesYes NoNo YesYes YesYes NoNo YesYes YesYes YesYes

Rao et at. [1] YesYes NoNo NoNo NoNo YesYes YesYes YesYes YesYes

Rajaraman et al. [2] NoNo NoNo NoNo NoNo YesYes NoNo NoNo YesYes

Asadi-Tahoori [3] NoNo NoNo NoNo YesYes NoNo NoNo NoNo NoNo

Zhang-Shanbhag[4] YesYes NoNo YesYes YesYes YesYes YesYes YesYes NoNo

Rejimon-Bhanja [5] NoNo NoNo NoNo YesYes YesYes NoNo NoNo NoNo

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Experimental Result ComparisonExperimental Result Comparison

Ckt#PI

#PO

#Gates

Our approach Rao et al. [1]Rajaraman et al[2]

CPU s

FITCPU s

FITCPU min

Error Prob.

C432 36 7 160 0.04 1.18x103 <0.01 1.75x10-5 108 0.0725

C499 41 32 202 0.14 1.41x103 0.01 6.26x10-5 216 0.0041

C880 60 26 383 0.08 3.86x103 0.01 6.07x10-5 102 0.0188

C1908 33 25 880 1.14 1.63x104 0.01 7.50x10-5 1073 0.0011

Computing Platform Sun Fire 280R Pentium 2.4 GHz Sun Fire v210

Circuit Technology TSMC035 Std. 0.13 µm 70nm BPTM*

Altitude Ground Ground N/A

*BPTM: Berkley Predictive Technology Model

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More Result ComparisonMore Result Comparison

Measured DataLogic Circuit SER Estimation Ground Level

Devices SER*(FIT/Mbit)

Our Work Rao et al. [1]

0.13µ SRAMs[6]10,000 to 100,000

1,000 to 10,000

1x10-5 to 8x10-5

SRAMs, 0.25μ and below [7]

10,000 to 100,000

1 Gbit memory in 0.25µ [8]

4,200

* The altitude is not mentioned for these data.

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DiscussionDiscussion We take the energy of neutron to be the key factor to We take the energy of neutron to be the key factor to

induce SEU. In real cases, there can also be secondary induce SEU. In real cases, there can also be secondary particles generated through interaction with neutrons.particles generated through interaction with neutrons.

Estimating sensitive regions in silicon is a hard task. Estimating sensitive regions in silicon is a hard task. Also, the polarity of SET should be taken into account.Also, the polarity of SET should be taken into account.

Because on the earth surface, typical error rates are Because on the earth surface, typical error rates are very small, their measurement is time consuming and very small, their measurement is time consuming and can produce large discrepancy. This motivates the use can produce large discrepancy. This motivates the use of analytical methods.of analytical methods.

For example, a circuit may experience 1 SEU in 6 For example, a circuit may experience 1 SEU in 6 months (4320 hours), equals 231,480 FIT. It is also months (4320 hours), equals 231,480 FIT. It is also likely that the circuit has 0 SEU in these 6 months, so likely that the circuit has 0 SEU in these 6 months, so the measured SER is 0 FIT. the measured SER is 0 FIT.

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Fan-out stems should be considered. Two Fan-out stems should be considered. Two situations can arise:situations can arise:

When an SET goes through a large fan-out, the large load When an SET goes through a large fan-out, the large load capacitance can eliminate the SET, orcapacitance can eliminate the SET, or

If it is not canceled by the fan-out node, it will go through If it is not canceled by the fan-out node, it will go through multiple fan-out paths to increase the SER.multiple fan-out paths to increase the SER.

It is highly recommended to have more field It is highly recommended to have more field tests for logic circuits.tests for logic circuits.

None of these SER approaches consider the None of these SER approaches consider the process variation effects on SER. process variation effects on SER.

Without consideration of electrical masking, SER will be Without consideration of electrical masking, SER will be overestimated by 138% for a small 5-stage circuit overestimated by 138% for a small 5-stage circuit [Wang et al., [Wang et al., VLSID’07VLSID’07]]

Intra-die threshold voltage variation can result in a peak Intra-die threshold voltage variation can result in a peak to peak SER variation of 41% in a small circuit to peak SER variation of 41% in a small circuit [Ramakrishnan et al., [Ramakrishnan et al., ISQED’07ISQED’07]]

Discussion ContinuedDiscussion Continued

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ConclusionConclusion SER in logic and memory chips will continue to SER in logic and memory chips will continue to

increase as devices become more sensitive to increase as devices become more sensitive to soft errors at sea level.soft errors at sea level.

By modeling the soft errors by two parameters, By modeling the soft errors by two parameters, the occurrence rate and single event transient the occurrence rate and single event transient pulse width density, we are able to effectively pulse width density, we are able to effectively account for the electrical masking of circuit.account for the electrical masking of circuit.

Our approach considers more factors and thus Our approach considers more factors and thus gives more realistic soft error rate estimationgives more realistic soft error rate estimation. .

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ReferencesReferences[1] R. R. Rao, K. Chopra, D. Blaauw, and D. Sylvester, “An Efficient Static

Algorithm for Computing the Soft Error Rates of Combinational Circuits," Proc. Design Automation and Test in Europe Conf., 2006, pp. 164-169.

[2] R. Rajaraman, J. S. Kim, N. Vijaykrishnan, Y. Xie, and M. J. Irwin, “SEAT-LA: A Soft Error Analysis Tool for Combinational Logic,", Proc. 19th International Conference on VLSI Design, 2006, pp. 499-502.

[3] G. Asadi and M. B. Tahoori, “An Accurate SER Estimation Method Based on Propagation Probability,” Proc. Design Automation and Test in Europe Conf.,2005, pp. 306-307.

[4] M. Zhang and N. R. Shanbhag, “A Soft Error Rate Analysis (SERA) Methodology," Proc. IEEE/ACM International Conference on Computer Aided Design, ICCAD-2004, 2004, pp. 111-118.

[5] T. Rejimon and S. Bhanja, “An Accurate Probabilistic Model for Error Detection," Proc. 18th International Conference on VLSI Design, 2005, pp. 717-722.

[6] J. Graham, “Soft Errors a Problem as SRAM Geometries Shrink, http://www.ebnews.com/story/OEG20020128S0079, ebn, 28 Jan 2002.

[7] W. Leung; F.-C. Hsu; Jones, M. E., "The Ideal SoC Memory: 1T-SRAMTM," Proc. 13th Annual IEEE International on ASIC/SOC Conference, 2000, pp. 32-36.

[8] Report, “Soft Errors in Electronic Memory-A White Paper," Technical report, Tezzaron Semiconductor, 2004.

[9] F. Wang and V. D. Agrawal, “Sngle Event Upset: An Embedded Tutorial,” Proc. 21st International Conf. VLSI Design, 2008, pp. 429-434.

[10] F. Wang and V. D. Agrawal, “Soft Error Rate Determination for Nanometer CMOS VLSI Logic,” Proc. 40th Southeastern Symp. System Theory, 2008, 324-328.

[9] F. Wang, “Soft Error Rate Determination for Nanometer CMOS VLSI Circuits,” Master’s Thesis, Auburn University, May 2008.

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Thank You Thank You . . .. . .