Mark Raymond - [email protected] - 16/12/051 Trip-t & TFB Trip-t schematics signals and...

Mark Raymond - [email protected] - 16/12/05 1

Trip-t & TFB

Trip-t schematics signals and registers operation

SiPM connection

TFB block diagram functionality (slow control and FE-FPGA)


Trip-t schematics - overview

SKIPB

PROG_IN

PROG_CTRL

PROG_RESET

PROG_CLOCK

PROG_OUT

Q_TEST [0:32]

Q_IN [0:32]

DACOUT

ProgInterface

Front End

A-Pipeline48 x 32 chan

t-Pipeline48 x 32 chan

Dummy OUT [33]

AnalogMUX

AnalogMUX

MUX_CLK

MUX_RESET

DISCRIM [0:31]

DIG_EN_U

DIG_RESET

DIG_EN_L

DigitalMUX

A OUT

t OUT

DISC_OUT[0:15]

from “Bench test of TRIP-t”Leo Bellantoni & Paul Rubinov


Trip-t schematics – front end

Q_IN

A OUTPUT

200fF

IBP

1.0 pF

3.0 pF

GAIN[3]

RESET

Z

IFF

IBOPAMP

GAIN[2]

160fF

GAIN[1]

80fF

GAIN[0] 40fF

40fF

+

-

IBOPAMP

V_REF

IFFP2

+

-

IBOPAMP

V_REF

IFFP2

x10

+

-

IB_T

IBCOMP

DISCRIM_OUT

V_TH

PLN_CLK

t OUTPUT

80fF

+

-

only 2 gain settings to preamp (1 & 4) preamp output goes straight to discriminator (global threshold) could be awkward if widely varying SiPM gains other gain settings only affect signals to pipeline

from “Bench test of TRIP-t”Leo Bellantoni & Paul Rubinov


128 pin 14 x 14 mmQFP

analog I/Psdigital disc O/Psdigital control I/Psanalog test I/Panalog bias (dec.)analog O/Ptest I/P only+2.5Vgndnot used

Trip-t pinout


Trip-t control signals

PrgReset resets programming interfacePrgCtrl defines whether programming the chip or running the output MUXPrgIn serial programming info or MUX reset (depending on PrgCtrl)PrgOut serial output to read back programmed register valuesPrgClk shift in serial programming data or MUX clock (depending on PrgCtrl)

PR1 Triggers pipeline readoutPlnClk Pipeline clockPlnReset Resets the pipelineMoveData Clears triggered pipeline column (allows timeslice to be overwritten)SkipB Triggers the pipeline (stops timeslice of interest being overwritten)PR2 Pipeline pedestal acquisition (not used – left over from SVX)

PreReset Switches preamplifiers between integrate/resetPre2aReset complement of PreResetPre2bReset complement of PreReset

DigenL enables one bank of 16 discriminator outputs off-chipDigenU enables the other bankDigResetB resets the discriminators

dual fast/slowfunctionality here


Trip-t registers

programming

chip ID: 01010register address: 5 bitsoperation: 3 bits (read/write/set/reset/default)1 bit spacevalue: 8/10/34 bits


Trip-t operation during spill

discriminator fires

PlnClk

PreReset

beam bunches end ofspill

SkipB

programmed bunch latency

PlnReset

need to continue clocking pipeline beyond end of spill until latency has elapsed (might be an event in last bunch)

event

PlnClk transfers preamp output to pipeline at end of integration period Pipeline internal write (and trigger) pointer then advances to next timeslicePipeline trigger pointer points to timeslice that was written the programmed bunch latency beforeWhen SkipB applied the timeslice that the trigger pointer is pointing to is marked to not be overwritten

(the write pointer will skip over it the next time it comes round)and its address is stored in a fifo (only 4 deep)

only 4 timeslices can be triggered in a particular spill

(you can return triggered timeslices to normal operation by applying MoveData signal after the timeslice datahave been MUXed out, so could continuosly trigger and read out chip, but taking care not to have more than4 triggered timeslices in the pipeline at any one time)


At end of spill

run the MUX MUX reset, and then MUX clocksimultaneously control ADC clock and ADC output MUX (2 ADC channels share 10 bit O/P parallel data bus)

specified (D0) ADC can run at 20 MHz =>1 timeslice can be read out in 32 x 50 ns = 1.6 usec (+ a bit for MUX reset)

don’t necessarily have to wait till end of spill, could run MUX and Preamp/Pipeline simultaneouslyjust have to take care not to overtrigger (fifo depth)

but may be preferable to have separate acquisition/readout phases


SiPM connection

connection method Vbias

1 M

50

thin coax

SiPMLED

trip-t

3p3

330p

SiPM -> Tript cable: have used coax mostly up to nowSiPM connected between core and coax sheath (core carries bias voltage)Coax provides signal shielding, twisted pair doesn’t – could we use shielded twisted pair?50 provides some kind of termination for the cable (-> 100 for twisted pair)charge split between two tript channels using different capacitor values to get high/low gain

feed in smallcurrent here to tune Vbias for

individual SiPM’s

or twisted pair


10.5x103

10.0

9.5

9.0

8.5

AD

C u

nits

14121086420

Qin [pC]

IBT=80 IBT=0

low gain channel

high gain channel

SiPM connection (analogue issues)

Tript with high preamp gain setting (1pF feedback)high gain saturates at ~ 1pC, low gain at ~ 15 pC (for charge splitting cap. values on p. 10)

can we use SiPM HV trim to tune individual SiPM gains to match these ranges?how well will final SiPM gains have to match?how well do SiPM gains really have to match?


TFB

TripTSiPMx16

FE-FPGA

controller

ADC

ADC

HVTrimDAC

8

HVTrimDAC

8

TripTSiPMx16

HVTrimDAC

8

HVTrimDAC

8

TripTSiPMx16

HVTrimDAC

8

HVTrimDAC

8

TripTSiPMx16

HVTrimDAC

8

HVTrimDAC

8

local power conditioning

slow serial I/F

fast serial data

timing

temperature monitoringlow voltage monitoringhigh voltage monitoringcalibration


micro-controller functionality (slow control)

•looks after programming of front end chips (internal LUT contains operational values)at power on, and on external requestneeds to communicate with FE-FPGA

- Tript programming inputs share pins with MUX control signals•monitor local (TFB) low and high (for TFB, not for every SiPM) voltage levels using internal, multi-input ADC•monitor local environment (obviously temperature but anything else…?)

may need external sensors

•Trip-t & electronic chain calibration (independent of SiPM)using Tript input channel mask register and external DAC can inject programmable amplitude test pulses into individual channelsneed to synchronize with FE-FPGA

•slow interface to outside – could be custom, could be commercial (e.g. I2C?)

•generate alarm (e.g. over-temperature)

•will we want to be able to re-program micro-controller in TFB production version?

•clearly this functionality could be implemented in FE-FPGAwould then need extra service chips (at least a multi-channel ADC)keeping data and control paths separate usually considered good thing


FE-FPGA functionality (fast control)

•Synchronization to accelerator (spill structure and bunch clock) (how?)

•Tript operation during spillprovide clocks (preamp integrate/reset and pipeline)timestamp discriminator outputs and return trigger (SkipB) to mark pipeline timeslices to

be subsequently read out (max 4 per spill (depth of Tript FIFO))•At end of spill (after pipeline latency elapsed)

Run Tript MUX and ADC to read out triggered timeslicesacquire digitized datatime required = 32 x no. of triggers x mux clock period (50ns say)

= 1.6 usec x no. of triggersformat data and transmit (later slide)

•During spill gap (~ 3 secs.) look for cosmicsfree run Tript – continuous pipeline cyclingtrigger in same way as during spill, but also pass triggers off board

(do we need to construct local track trigger?)(do we need to wait for return of trigger accept signal from outside?)

Run MUX and ADC for every trigger, format data and transmit

should be able to be live for high percentage of time (trigger rate << 1 per 1.6 usec)


What to do with spill (and cosmic) data in FE-FPGA? – some options here

1) minimal processingattach timestamp, bunch no., individual TFB ID, raw data and transmit everything

(will want option to operate in this mode for debugging)

2) more processingpedestal subtract, suppress channels with no signal (vast majority), attach timestamp, bunch no, individual SiPM no., individual TFB ID, signal amplitude, and transmit

Where / how / how often to construct s.p.e. spectra for SiPM gain calibration?

does this need to be done in FE-FPGA? - complicated thing to have to do

comes with raw data anyway - s.p.e. noise hits in channels without signal

could insist on raw data transmissionoutside spill time (make this an off-detector task?)

could locally generate dummy triggers at some rate but may conflict with cosmicevent acceptance

1500

1000

500

0

sign

al c

ount

s

10.0x103

9.59.08.5

ADC units

60x103

40

20

0

noise

counts

R1 (0509-023)39.0 V bias11/11/05

led noise only

Mark Raymond - [email protected] - 16/12/051 Trip-t & TFB Trip-t schematics signals and...

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