Mark Raymond - 5/10/061 TFB hardware status – 5/10/06 update including mods discussed at previous...

Mark Raymond - 5/10/06 1

TFB hardware status – 5/10/06

update including mods discussed at previous meeting (7/9/06)

connectors (power and signals)LV powerHV switchLM92 temperature monitoringlayout status and ECAL mountingtimescale


power connector

20 way, dual row, 0.1” pitch MOLEX connector, 3A/pin rated

HVHV1.21.22.52.53.33.3

55

HVgndHVgnd1.2gnd1.2gnd2.5gnd2.5gnd3.3gnd3.3gnd5gnd5gnd

some questions (some answers)

who provides the cabling – do we make it ourselves?someone else48 TFBs per power group – how/where do we split the incomingpower lines to feed individual TFBs?at a distribution modulehow can we make use of regulator shutdown to disable individual TFBs?can’tfuses? (regulators include overcurrent/overtemperature protection)could fuse at distribution module?Shorted SiPM will draw HV current but series resistance will limit to < 1mAcan switch off HV (to whole board) and monitor HV current

voltages after regulation – actual incoming levels will be higheruse 2 pins/supply


signal connectors

datascreened RJ45 - 4 twisted pairs

data indata out100 MHz clocktriggering line (spill start, spill no., cosmic, calibration?)

trigger outonly one twisted pair/TFB neededuse second RJ45 but only one pairmerge signals into RJ45 cable to GTM using an intermediate board


TFB onboard LV power regulators

supply after reg. component current [A] circuitry supplied power on TFB [W]

1.5 -1.7 1.2 LP38843ES-1.2 < 3 FPGA core 5.1

2.5 A <0.5 trip-t 1.62.95 - 3.1 LP3856ES-2.5

2.5 D ~1.05 FPGA 2.5 3.3

3.8 3.3 D LP3856ES-ADJ ~0.95 FPGA I/O 3.6

5.5 5 A LP3856ES-5.0 <0.2 ADCs / HVtrimDACs 1.1

5.7 return 14.7

all TO263-5 packages (not proposing to use shutdown I/Ps)

two other small regulators on board to supply PROM (1.8V), slow control cct. (precision 5V), but low power requirements and can take inputs from above supply levels

dropout depends oncurrent – should prob.take worst case

incuding regulatorpower (hopefullyworst case)


HV switch

HV in

HV on TFB (to all SiPMs)

FPGA

GND

100k

1M1M

47k

1M

47k

100 ohms

100k ADC I/P ADC I/P 0.1uF

BSP225

BSS131

prototyped and works OK

monitor HV either side of 100 ohms -> crude current measurement 1mA -> 100mV, but resistive division -> only 5mV difference at ADC I/Ps(ADC resolution 1.2 mV)

go with this for now, but maybe DC-DC conversion on TFB possible?


LM92 temperature sensor

SO8

SDA

SCL

T_CRIT_A

GND

VS

A0

A1

INT

I2C bus

up to 4 I2C addresses (one on board – 3 ext.)

3.3V

active when T outside programmable window

acitve when T > programmable limit

+/- 0.33 deg. accurate around 25 deg. region

can mount on small external PCBs for up to 3 external monitoring points6 wire connector for IDC cable (3.3/GND/SDA/SCL/T_CRIT_A/INT) now on TFB

T_CRIT_A and INT open drain so connect all devices in parallel to 2 FPGA I/Ps


slow control (monitoring)

single channel AD5321 DAC 0 -> 5V, 12 bit resolution, for trip-t electronic calibration

8 channel AD7998 ADC, 0 -> 5V (power and Vref provided by REF195), 12 bit resolution

both chips with I2C interface controlled by FPGA

allocation of AD7998 inputs

1 1.2V supply2 2.5V supply3 3.3V supply4 5V supply (divided down)5 HV before 100 ohms (divided down)6 HV after 100 ohms (divided down)7 front end cal voltage8 spare


TFB PCB layout status

coaxial connectors on top surface

trip-t, FPGA, HVtrimDACs on bottom (can be thermally coupled to cooling)

ADCs, regulators, connectors on top surface

I2C connector for externaltemperature sensors (up to 3)

6 routing layers top, bottom + 4 internal

+ power and ground layersso maybe 10 layers overall?

signal routing completework still to do power and ground planes

board is now 16 cm in the long direction, 9cm in the short

2RJ45’s


cooled Al mounting plate

thermal gap filler

TFB

TFB mounting for ECAL

TFB mounted on cooled Al plate with cutouts through which SiPM cables are fed

min. coax connectors (and other connectors) on top surface

chips to be cooled on bottom surface, in thermal contact with platethermal gap filler allows for differences in chip thicknesses

power regs. on top side – dissipating heat to board – so will need to provide good thermal pathwayto mounting plate in this area of TFB

to SiPM

coax socket~2 mm dia.

terminated coax cable (1.3 mm dia.)


16 cm

9 cm

power

data+

trig.

cutouts tofeed mini-coax’s thruto SiPMs

TFB mounting for ECAL

6 x 3mm mounting holes


timescale

still ~1-2 weeks work left on layout

most components procured for up to 25 boardsonly FPGA and PROM (both BGA) non RoHS compliant => 2 step manufacture process

still plan to produce 2 boards quickly - hopefully by ~ end October

produce more, on slower timescale, after no major (electrical) problems identified

testing needs some thought….


Trip-t and TFB status

Trip-t brief description of internal architecture and interfacesproposed Trip-t operation at T2KSiPM connection, gain and discriminator threshold considerations

Results from latest Tript versionlinearity and discriminator measurements

TFB prototype statusresults from prototyping elements

ADC functionality and test results HVtrim functionality and test results Calibration circuitt description and test results

TFB layout statusTFB firmware status

future plansDRAFT TALK – NOT YET FINISHED


Trip-t single channel front end architecture

preamp

very simplified – neglecting features not relevant to ND280 operation

integrate/reset

gain 1 or 4

gain adjust1,2,3,…8

x10

Vth

analogue pipeline

disc. O/P

Qin

only preamp gain affects signal feeding discriminator – no fine control (x1 or x4)Vth common to all channels on chipanalog bias settings, gain, Vth, programmable via serial interface

discriminator

1pF

3pF

reset


Trip-t full chip

32 channel chip -> 1 serial output, 48 deep analogue pipeline to store sampled front end outputs (note: pipeline operated using 2 timeslices/preamp integration period, so length reduced to 23

see http://www.hep.ph.ic.ac.uk/~dmray/pdffiles/FIFOtalk_1_3_06 for detailed explanation)

have to select either top or bottom 16 disc. O/Ps to transmit off-chip

~ 12 digital control/programming inputs, 16 disc. outputs => ~ 30 I/O lines/chip (2.5 V CMOS)

32front end

chans

top16 IP/s

bottom16 I/Ps

analogue memory(pipeline)

48

3232 analogoutputs

top 16 disc. O/Ps

bottom 16 disc. O/Ps

top or bottom16 disc. O/Ps

32

32:1analogMUX

serialanalogoutput

dig.MUX32:16

bias, control, reset control

control control

serial programminginterface, bias gen.,control interface, …

dig.control

simplified and neglecting features not relevant to operation in ND280


Proposed mode of Trip-t operation for beam spill data acquisition is as follows

during spillintegrate signal for each bunch and store result in pipeline* (15 timeslices for 15 bunches)timestamp high gain channel discriminator outputs that fire

after spillcontinue running in same way, for a while, to catch late signals ( decay)readout entire contents of pipelineassemble data block containing hit timestamps and all digitized analogue data and transmit

transmitting all info in this way allows histogramming of single p.e. events to monitor SiPM gainvast majority of data is pedestal + single/double p.e. hits only

Trip-t operation at T2K

5.25 sspill period

2.8 safter spill

active period

74 s (23 cell) readout period(if O/P mux running at 10 MHz)

start of spill end of spillat this time trip-t switches

to inter-spill operational mode(cosmic trigger)


Tript for ND280, gain considerations

need ~ 500 p.e. dynamic range, while simultaneously discriminating signals at the ~ 1p.e. levelcan’t be done with one gain range => split signal between high/low gain ranges (channels)Signal shared between Cadd, Chi and Clo (also some strays), Chi/Clo = high/low gain ratio

HVglobal

1 M

50

thin coax

SiPM

trip-tChi100pF

Clo10pF

Cadd330pFHVtrim

Choose Cadd to match final SiPM gain (330pF about right for 5x105)Cadd also helps with gain discontinuity when hi gain channel saturates(see http://www.hep.ph.ic.ac.uk/~dmray/pdffiles/tript_talk_1_3_06)

don’t know what final SiPM gain will be, but assume production devices will be quite well matchedin any case will have individual channel gain adjustment by HVtrimDACs

simplified single SiPM channel schematic


Discriminator threshold (Vth) considerations

x10

1pF

reset

Vth

disc. O/P

analoguepipeline

Qin

Vth only relevant to the 16 high gain channels - remember only 16 channels can be selected for transmission off-chip, so just arrange for these to be the high gain channels

(Vth also applied to low gain channels, but we don’t need to look at the outputs of these)

Vth needs to be set high enough to prevent single p.e. events triggering discriminator (otherwise single p.e. triggers will dominate and will lose ability to timestamp real signals)

uncertainty in threshold setting given by spread in discriminator turn-on curves across chip

can choose high gain channel value (external capacitor division ratio) but trade-off between threshold adjustment range and uncertainty in threshold value


x10

1pF

reset

Vth

disc. O/P

analoguepipeline

Qin

~ 1V dynamic range available at preamp O/P ~ similar voltage range

at x10 amp O/P~ similar disc. thresh.

voltage adjustment range

2.5 V CMOS so can assume dynamic ranges of internal circuits ~ 1V

this has implications for discriminator threshold range

if want 0 – 5 p.e. adjustment range then 5 p.e. ≡ 1V at x10 O/P=> 1V ≡ 50 p.e. at preamp O/Pso high gain channel will saturate at ~ 50 p.e.

this translates to threshold uncertainty ~ +/- 0.5 p.e. (measured – see later)

Gain and gain ratio considerations (1)

single triptchannel


So discriminator threshold range adjustment 0 -> 5 p.e.

High gain channel saturates at 50 p.e.

Choose Chi/Clo so low gain channel saturates at 500 p.e.

Note: These values are examples and can change, but need to take care withthreshold adjustment range/uncertainty trade-off

Gain and gain ratio considerations (2)

HV(TFB)

1 M

50

thin coax

SiPM

Trip-tChi100pF

Clo10pF

Cadd330pF

HVtrim

simplified single SiPM channel schematic


Latest Trip-t test results from final version

2nd (final) tript version very similar to 1st

minor architecture change to improve O/P stage linearity

version 2 linearity clearly better but still some gain reduction for small signals

will need electronic calibration to correct for linearity

10.5x103

10.0

9.5

9.0

8.5

AD

C u

nits

543210

Qin [pC]

12

11

10

9

x103

version 1 version 2

Trip-t V1/V2 linearity comparison


Tript V2 linearity(1)

4000

3000

2000

1000

0

AD

C u

nits

403020100

total external charge injected [pC]

all 16 channels, hi and lo gains

component values chosen forSiPM gain ~ 5x105 (Chi = 100pFClo=10pF, Cadd=330pF)

lo gain saturates at ~ 40 pC (500 p.e.)

hi gain saturates at ~ 4 pC (50 p.e.)

higaincahnnels

logainchannels


Tript V2 linearity(2)

10

2

3

4

5

678

100

2

3

4

5

678

1000

2

3

4

AD

C u

nits

5 6 7 80.1

2 3 4 5 6 7 81

2 3 4 5 6 7 810

2 3 4


log-log plot of same data

10:1 gain ratio means gain rangechange occurs where logain signalsize already large so no S/N problems

higainchannels

logainchannels


Tript V2 discriminator measurement

1000

800

600

400

200

0

# of

tim

es

disc

. fir

es

0.400.350.300.250.200.150.100.050.00


count the no. of times the discriminator firesfor 1000 preamp integration periodssweep the injected signal size

for 5x105 1p.e. -> 0.08 pC

pk-pk width ~ 1 p.e. also for this measurment

so +/- 0.5 p.e. precision

can improve precision but remember trade-offwith adjustment range

1 p.e.

discriminator curves for all 16 higain channels

2 p.e.


Tript V2 discriminator timewalk

355

350

345

340

335

330

325

aver

age

disc

rimin

ator

firi

ng t

ime

[nse

c]

2.01.51.00.50.0

overall injected charge [pC]

ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 ch8 ch9 ch10 ch11 ch12 ch13 ch14 ch15

1 2 3 p.e. (1 p.e. = 80 fC (5x105)

significant timewalk and chan-to-chan spread for small signals

can set threshold at 1.5 p.e. and discriminator will fire, but timestamp for low amplitude signals will not be reliable

OK for signals > ~ 3 p.e.

can correct for timewalk off-line


TFB (Tript Front-end Board) prototype status

main functionality:

4 Tript’s/TFB => 64 SiPM channels (for ECAL) individual programmable HVtrim (5 V range) for each SiPM channel tript O/P signal digitisation front end electronic calibration FPGA to program tript, sequence operation, timestamp hits, control digitisation, format and transmit data, … local LV power regulation

prefer to prototype designs for individual functions as much as poss. before committing to final TFB prototype

results here for on-board ADC, HVtrim and electronic calibration circuits


cal cct

HVtrimDACAD9201

SiPM

Tript

miniature coax and connectors

prototyping elements of TFB

necessary to proove as much of TFB circuitry as possible before committing to layouthelps to identify where extra layout care is neededimproves chances of TFB prototype working successfully


47k50V, 0402

220pF50V0402

330pF100V0603

10pF100V0603

100pF100V0603

51RLV

0603

100nFLV

0402

1kLV, 0402

trip-t

10pF100V, 0603

HVglobal

HVtrim(0-5V)

cal testpulse

coax sheath not DCcoupled to GND

SiPM

SiPM -> TFB connection - details

47k50V, 0402

HVglobal: common to all SiPM channels on TFBHVtrim: individual for each SiPM channel, 5V adjustment range (choice of 8/10/12 bit DAC precision)HVtrim applied to coax sheath – AC but not DC coupled to GND

significant no. of passives/channel – need careful, high

density layout


ADC for the TFB

AD9201 – used by D-zero

dual-channel => 2 tript’s/ADC

28 pin SSOP package

separate analog and digital supplies

5V analogue – needed to accommodate tript O/P range

3.3 V digital


analog supply and ADC reference voltage configuration optimised so that tript output signals well matchedto 10 bit ADC range

1000

900

800

700

600

500

400

300

200

100

0

AD

C u

nits

4035302520151050

Qin [pC]

high gain channel low gain channel

tript linearity measured with AD9201


SiPM signals measured with tript/AD9201

3000

2500

2000

1500

1000

500

0

coun

ts (

with

LE

D)

260240220200180160140

ADC units

14x103

12

10

8

6

4

2

0

counts (no LED

)

with LED pulse no LED pulse

Russian SiPM: gain 5.6x105

275 ns preamp integration period

100,000 events in each spectrum

~ 10 ADC units / p.e.=> 0.1 p.e. ADC resolution


HV trim circuit for TFB

51RLV

0603

100nFLV

0402

1kLV, 0402

HVtrim(0-5V)

coax sheath carriesHVtrim voltage

SiPM

HVglobal

8 channel DAC chip => 2 / tript, 8 / TFB

8/10/12 bit versions availableidentical chips, just different resolution(price difference but negligible to us)

TSSOP 16 pin SM package

serial interface to program (from FE FPGA)

output voltage variable 0 -> 5 V20 mV resolution for 8 bit version


TFB HV trim circuit linearity

5

4

3

2

1

0

Out

put

volta

ge

250200150100500

DAC value

-4

-2

0

2

4

residuals [mV

]

8 bit DAC version used here

gives 20 mV precision for 5 V range should be enough?

single DAC channel measurement


TFB HV trim circuit with SiPM

800

600

400

200

0

500400300200100

DAC value = 0HVtrim = 0HV eff. = 50 Volts

1600

1200

800

400

0

500400300200100

DAC value = 50HVtrim = 1.0 VoltsHV eff. = 49 Volts

3000

2000

1000

0

500400300200100

DAC value = 100HVtrim = 2.0 VoltsHV effective = 48 Volts

25

20

15

10

5

0

x103

500400300200100


3025

20

15

10

5

0

x103

500400300200100


8000

6000

4000

2000

0

500400300200100


SiPM LED spectra for device withnominal 47.5 V operating voltageshowing effect of HVtrim circuit

5 Volt range for HVtrim givesoverall range 45 – 50 Volts (when combined with HVglobal)


CAL circuit for TFB

Vcal (0 – 5 V)(use another

AD5308 DAC here)

to 16 trip-t SiPM channelsbefore gain splitting capacitors

4 CAL lines feedingevery 4th channel

from FE-FPGAdiscrete

MOSFETs

10 pF


CAL circuit test results with tript/AD9201

16 low gain chans

16 high gain chans

2.2

2.0

1.8

1.6

1.4

1.2

1.0

Vol

ts

time [500 ns / division]

pedestal DAC=50 DAC=100 DAC=150 DAC=200 DAC=250

2.2

2.0

1.8

1.6

1.4

1.2

1.0

Vol

ts

time [500 ns /division]

pedestal DAC val. = 0 DAC val. = 5 DAC val. = 10 DAC val. = 15 DAC val. = 20 DAC val. = 25

tript multiplexed analog output streamfor different DAC values for one CALtest input – sampled with scope

tript MUX (and ADC) running at 5 MHz

substantial crosstalk – but only afterhigh gain channels beyond saturation


CAL circuit test results with tript/AD9201

1000

800

600

400

200

0

AD

C u

nits

403020100

Qin [pC]

high gain / external test pulse low gain / external test pulse high gain / CAL cct low gain / CAL cct

linearity measured for one SiPM channelusing external test pulse and CAL circuit

-> close correspondence

(also using AD9201)


TFB elements prototyping summary

tript output ADC, SiPM HVtrim DAC circuit and electronic chain calibration circuit all prototypedand tested

no major problems encountered

can now proceed to lay out the TFB prototype with confidence that at least these elements should function OK.


Tript FPGA footprint

HVtrimHVtrim 16 SiPM I/Ps and passives

CAL cct

AD9201footprint

TFB layout status – 10 cm x 16 cm

high density SiPM I/P layout complete – gives confidence that size target ~ achievable

still much left to do (e.g. FPGAdig. signals routing, power regs.,connectors (power and control),slow control interface, …..


cooled Al mounting plate

thermal gap filler

TFB

TFB mounting ideas (ECAL)

TFB mounted on cooled Al plate with cutouts through which SiPM cables are fed

min. coax connectors (and other connectors) on top surface

chips to be cooled on bottom surface, in thermal contact with platethermal gap filler allows for differences in chip thicknesses

power regs. on top side – dissipating heat to board – so will need to provide good thermal pathwayto mounting plate in this area of TFB

to SiPM

coax socket~2 mm dia.

terminated coax cable (1.3 mm dia.)


TFB interfaces

4 LVDS pairs (RJ45 type connector and cable – should be screened)

Clocks input: 100 MHz, 1Hz, Spill/Cosmic triggerData inputData outputRF clock ? (maybe not needed)

slow control

TBD (maybe just a connector to plug-on micro-controller based circuit?)

Power< ~100V small SiPM HV+2.5 ~ 0.5A tript and FPGA I/O+ 5 ~ 0.2A ADC analogue and HVtrim DAC+3.3 TBD ADC digital and FPGA I/O+1.2 TBD FPGA core


for programmingtript: ~ 900 kbits for 50k channels HVtrim DACs: 8 bits res’n x 50k chans = 400 kbits

for raw spill data readout (data only)assume 23 integration periods

4 tript’s / TFB32 channels/tript (hi and logain)10 bit ADC

=> ~30k bits /TFB /spill

+ hit timestamp data and associated hit channel addresses

some data volume numbers


planning

Plans for this year (2006)

1st TFB prototype to be produced by end October

in parallel produce sufficient firmware for characterization

detailed electrical characterization by beginning 2007

Plans for next year (2007)

vertical slice test (1st quarter) TFB prototype with photosensors, RMM and MCM prototypes

review requirements and design 2nd (final) TFB prototype for ECAL

produced and tested by end of year

Mark Raymond - 5/10/061 TFB hardware status – 5/10/06 update including mods discussed at previous...

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Transcript of Mark Raymond - 5/10/061 TFB hardware status – 5/10/06 update including mods discussed at previous...