M75 MLB 051-7225.bak

ANGLES

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

DATE

APPDENG

DATE

APPDCK

ECNZONEREV

DO NOT SCALE DRAWING

X.XXX

X.XX

XX

DIMENSIONS ARE IN MILLIMETERS

THIRD ANGLE PROJECTIOND

SIZE

APPLICABLENOTED AS

MATERIAL/FINISH

NONE

SCALE

DESIGNER

MFG APPD

DESIGN CK

RELEASE

QA APPD

ENG APPD

DRAFTER

METRIC

OFSHT

DRAWING NUMBER

TITLE

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PARTII NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

Apple Computer Inc.

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DESCRIPTION OF CHANGE

TABLE_TABLEOFCONTENTS_ITEM






















































































DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL

TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_HEAD

DRAWING

SCHEM,MLB,MBP15

Schematic / PCB #s

04/24/2007

051-72251

? ?? ??

88A.0.0TITLE=MLBABBREV=DRAWING

Page Date(.csa) Contents Sync

820-2101 1 PCB CRITICAL

Page Contents DateSync(.csa)45 SMC49 01/17/2007T9_NOME1 N/A1 N/ATable of Contents

1051-7225 CRITICALSCH

46 SMC Support50 (MASTER)(MASTER)47 LPC+ Debug Connector51 03/19/2007M76_MLB48 SMBus Connections52 (MASTER)(MASTER)49 Current & Voltage Sensing53 (MASTER)(MASTER)50 Current Sensing54 (MASTER)(MASTER)51 Thermal Sensors55 (MASTER)(MASTER)52 Fan Connectors56 03/19/2007M76_MLB53 ALS Support58 03/19/2007M76_MLB54 Sudden Motion Sensor (SMS)59 03/19/2007M76_MLB55 SPI BootROM61 03/16/2007T9_NOME56 PBus-In & Battery Connectors69 09/09/2006(M59_SYNC)57 Power FETs70 03/19/2007M76_MLB58 IMVP6 CPU VCore Regulator71 01/23/2007M76_MLB59 IMVP6 NB Gfx Core Regulator72 03/19/2007M76_MLB60 5V / 3.3V Power Supply73 03/19/2007M76_MLB61 1.25V / 1.05V Power Supply74 03/12/2007M76_MLB62 1.8V DDR2 Supply75 03/19/2007M76_MLB63 1.5V Power Supply76 03/12/2007M76_MLB64 FW PHY Power Supplies77 03/19/2007M76_MLB65 3.425V G3Hot Supply & Power Control78 (MASTER)(MASTER)66 NV G84M PCI-E80 (MASTER)(MASTER)67 NV G84M Core/FB Power81 (MASTER)(MASTER)68 NV G84M Frame Buffer I/F82 (MASTER)(MASTER)69 GDDR3 Frame Buffer A84 (MASTER)(MASTER)70 GDDR3 Frame Buffer B85 (MASTER)(MASTER)71 NV G84M GPIO/MIO/Misc86 (MASTER)(MASTER)72 GPU Straps87 (MASTER)(MASTER)73 NV G84M Video Interfaces88 (MASTER)(MASTER)74 GPU (G84M) Core Supply89 (MASTER)(MASTER)75 LVDS Display Connector90 (MASTER)(MASTER)76 DVI Display Connector94 (MASTER)(MASTER)77 LVDS Interface Mux95 (MASTER)(MASTER)78 Project Specific Connectors96 08/24/2006(M59_SYNC)79 CPU/FSB Constraints100 01/17/2007T9_NOME80 NB Constraints101 01/17/2007T9_NOME81 Memory Constraints102 01/17/2007T9_NOME82 SB Constraints (1 of 2)103 01/17/2007T9_NOME83 SB Constraints (2 of 2)104 01/17/2007T9_NOME84 Clock & SMC Constraints105 01/17/2007T9_NOME85 FireWire Constraints106 01/17/2007T9_NOME86 GPU (G84M) Constraints107 (MASTER)(MASTER)87 Project Specific Constraints108 (MASTER)(MASTER)88 PCB Rule Definitions109 (MASTER)(MASTER)

2 (T9_MLB)2 08/23/2006System Block Diagram3 (T9_MLB)3 08/23/2006Power Block Diagram4 N/A4 N/APower Block Diagram5 N/A5 N/ABOM Configuration6 N/A6 N/ARevision History7 (MASTER)7 (MASTER)Functional / ICT Test8 (MASTER)8 (MASTER)Power Aliases9 (T9_MLB)9 08/23/2006Signal Aliases10 T9_NOME10 03/16/2007CPU FSB11 T9_NOME11 03/16/2007CPU Power & Ground12 M76_MLB12 03/19/2007CPU Decoupling & VID13 T9_NOME13 12/12/2006eXtended Debug Port (XDP)14 T9_NOME14 03/16/2007NB CPU Interface15 T9_NOME15 03/16/2007NB PEG / Video Interfaces16 T9_NOME16 03/16/2007NB Misc Interfaces17 T9_NOME17 03/16/200718 T9_NOME18 03/16/2007NB Power 119 T9_NOME19 03/16/200720 T9_NOME20 03/16/200721 T9_NOME21 01/17/2007

M76_MLB22 03/12/2007

23 T9_NOME23 03/16/2007SB Enet, Disk, FSB, LPC24 T9_NOME24 03/16/2007SB PCI, PCIe, DMI, USB25 T9_NOME25 03/16/2007SB Pwr Mgt, GPIO, Clink26 T9_NOME26 03/16/2007SB Power & Ground27 T9_NOME27 01/17/2007SB Decoupling28 (T9_MLB)28 08/24/2006SB Misc29 T9_NOME29 03/16/2007Clock (CK505)30 (MASTER)30 08/23/2006Clock Termination31 (M59_SYNC)31 08/24/2006DDR2 SO-DIMM Connector A32 (M59_SYNC)32 08/24/2006DDR2 SO-DIMM Connector B33 (T9_NOME)33 11/14/2006Memory Active Termination34 (M59_SYNC)34 08/24/2006Left I/O Board Connector35 T9_NOME37 03/16/2007Ethernet (Yukon)36 T9_NOME38 03/16/2007Yukon Power Control37 M76_MLB39 03/19/2007Ethernet Connector38 M76_MLB40 03/19/2007FireWire Link (TSB83AA22)39 M76_MLB41 03/19/2007FireWire PHY (TSB83AA22)40 M76_MLB42 03/19/2007FireWire Port Power41 M76_MLB43 03/19/2007FireWire Ports42 (MASTER)44 (MASTER)PATA Connector43 M76_MLB46 03/19/2007External USB Connector44 M76_MLB47 03/19/2007Left Clutch Barrel Interconnect

NB DDR2 Interfaces

NB Power 2NB GroundsNB Standard DecouplingNB Graphics Decoupling22

SCHEM,MLB,MBP15PCBF,MLB,MBP15

SCHEM,MLB,MBP15

LAST_MODIFIED=Tue Apr 24 17:23:54 2007

DSIZE

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DRAWING NUMBER



III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT


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REV.

APPLE COMPUTER INC.SCALE

NONE

Pg 15Pg 17,18,19

Pg 77

Pg 79,81

3.3 V100 MHz

J4400

Pg 35

DVI-I MUX

GPIO

ConnInt Disp

Pg 78

U1000

Pg 10

2.? GHzCPU

Pg 9

Core ~1.2V

ITP/XDP CONNJ1300/JD000 Pg 28

TERMSPg 29

UC500

ClocksPg 98

CK 505U2900

Pg 98

Clocks

Pg 13U1400P

CI-E

Pg 14

J8000

FSB64-Bit

800/1066? MHz

SDVOx16 PCI-E

Main Memory

Misc

ParallelTermPg 32

NB-GMCHCore

DMIPg 15

CLnk 0Pg 15

DDR2 - Dual Channel1.8V - 64 Bits

J3100J3200

DIMM

Pg 15/1

6

TV

Out

RGB

LVDS

Pg 14

x4 DMI2.5 GHzJ9200

J9200 Source is the LVDSfrom the PEG based GPU.

MUX

Pg 80GPIO

J4510/20/30 1.2 V / 1.5 GHz

SATAConnPg 43

UATA

ConnPg 42

JB200 JB300 JB400

PCI-E

Conns

Pg 93/4/5

UB100

6 - x12.5 GHz

PCI-E

Pg 92

MUX

DMIPg 23

CLnk 0Pg 24

SPIPg 23

67

89

51

23

4

CorePg 25

E-NETPg 22

CLnk 1Pg 24

PCIPg 23

AZALIA

USB

Pg 23

Pg 22DIMMs Clk GenJ3100J3200

U2900UC500

U6100/50

SPIBoot ROM

Pg 58 A B,0 BSA BSB ADC Fan Ser

PrtSMC

U4900 Pg 46

U6000

TPMPg 57

J5100

LPC ConnPg 48

Fan Conn Pg 53, 54

J6900/50

Pg 66

Power

Temp Sense

ChargerRight SideGPUCPU

Linda FncPrt 80, Comm 1, SMC, FWH

J4630

USB Connectors

Pg 44

J4710

Camera/IRPg 45

J4720

Bluetooth

Pg 45

J4700

Trackpad/KeyboardGeyser

Pg 45

MDC

Pg ??

U????U6200

AudioCodecPg 59

U6300/1 U6400 U6500 U6600/10/20

Line InAmpPg 60

Line Out

Pg 61

Amp 1Line OutAmp 2Pg 62

SpeakerAmpsPg 63

ConnsAudio

Pg 65

J3400

Pg 33

Mini PCI-EAirPort

JB500

PCI-EConn

U3700

NINEVEHE-NET

Pg 37

ConnE-NET

J4630

33 MHz32-Bit

U4000

TSB82AA2

Pg 38

FW-Link

U4100

TSB81BA3

Pg 39

FW-PHY

J4320 J4330

FireWireConnPg 41

JB000

PCIConnPg 91

100 MHz8-Bit

Ln1

Ln2

Ln3

Ln4

Ln5

Ln6

Pg 22

UATA

PCI-E

Pg 23

SATA-0

SATA-1

SATA-2

SATA

Pg 22

U2300

SB-ICH8Core 1.05V

Pg 22

Pg 24

GPIOs

SMB

LPC

Pg 24

Pg 51Pg 52Pg 52Pg ??

ReGenTERMS

J5810/20/90 ALS SENS Pg 55

U5920 Sudden Motion Detect Pg 56

Pg30,31533/667/800? MHz

1.05 - 1.25V

PEG Connector

ConnPg 68-76Supply

DC/Batt

U5500U5550U???

U5572

Power Sense Pg 51, 115-120

J5600/10/50/60, J5720/30/50

Pg 124-130

Pg 12/103

Pg 96

J4600

J6800/1/2/3

J9400

U9120

J9000/10 U9250/60

Approximate System Block Diagram

SYNC_DATE=08/23/2006System Block Diagram

051-7225

2 88

A.0.0

SYNC_MASTER=(T9_MLB)

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Power Block Diagram

051-7225 A.0.0

883

SYNC_MASTER=(T9_MLB) SYNC_DATE=08/23/2006

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NONE

SYNC_DATE=N/ASYNC_MASTER=N/A

4 88

A.0.0051-7225

Power Block Diagram

DSIZE

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NONE

TABLE_BOMGROUP_ITEM

BOM OPTIONSBOM GROUPTABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM



BOM OPTIONSBOM NAMEBOM NUMBERTABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

BOM OPTIONSBOM GROUPTABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

Bar Code Labels / EEE #s

Module Parts

IS

M75 BOM Groups

BOM Variants

337S3464 IC,MDC,SR,E1,PRQ,2.2G,35W,800FSB,4M,BGA1 U1000 CPU_2_2GHZCRITICAL

337S3465 IC,MDC,SR,E1,PRQ,2.4G,35W,800FSB,4M,BGA CPU_2_4GHZU10001 CRITICAL

1 IC,GPU,NV G84M,BGA338S0388 U8000 CRITICAL

IC,NB,CRESTLINE,GM,C0,PRQ,965PM338S0432 1 CRITICALU1400

IC,ISL9504,SYNC REG CTRL,2PHAS,QFN48,LF353S1461 ISL9504A1 U7100 CRITICAL

IC,ISL9504B,2PH IMVP6 REG,PMON,QFN48 ISL9504B353S1651 1 CRITICAL

IC,68 PIN,CK505,LOW POWER CLOCK GENER SLG8LP537CRITICAL359S0127 1

IC,SLG2AP101,LW PWR CLCK GEN,CK505,QFN68 SLG2AP1011 CRITICALU2900359S0130

IC,88E8058,GIGABIT ENET XCVR,64P QFN CRITICAL1 U3700338S0386

IC,SMC,HS8/2116338S0274 CRITICAL SMC_BLANK1

IC,16MBIT 8-PIN SPI SERIAL FLASH,SOIC81335S0384 U6100 BOOTROM_BLANKCRITICAL

341S2002 CRITICAL1 BOOTROM_PROGU6100IC,EFI ROM,DEVELOPMENT,M75

VRAM_128_SAMSUNGIC,SGRAM,GDDR3,8Mx32,700MHZ,136 FBGA4 U8400,U8450,U8500,U8550333S0404

IC,SGRAM,GDDR3,8Mx32,700MHZ,136 FBGA VRAM_128_HYNIXCRITICAL4 U8400,U8450,U8500,U8550333S0409

IC,SGRAM,GDDR3,16Mx32,700MHZ,136 FBGA VRAM_256_HYNIXU8400,U8450,U8500,U85504 CRITICAL333S0401

M75_COMMON1

BOOTROM_PROG,SMC_PROGM75_PROGPARTS

630-7931 M75_COMMON,EEE_X5D,CPU_2_2GHZ,FB_128_SAMSUNG

152S0276 ALL152S0476 Inductor alternate

IC,SGRAM,GDDR3,16Mx32,700MHZ,136 FBGA VRAM_256_SAMSUNGU8400,U8450,U8500,U85504 CRITICAL333S0382

IC,SMC,DEVELOPMENT,M75 U49001 SMC_PROGCRITICAL341S2004

338S0434 IC,SB,ICH8M,B1,PRQ,BGA CRITICAL1 U2300

630-7932 M75_COMMON,EEE_X5E,CPU_2_4GHZ,FB_256_SAMSUNG

630-8662 M75_COMMON,EEE_XXT,CPU_2_4GHZ,FB_256_HYNIX

[EEE:X5D] CRITICAL EEE_X5D826-4393 1

ALL138S0602 Murata alt to Samsung138S0603

ALL TI alt to National353S1681 353S1294

ALL157S0011 E&E alt to TDK/BI-Tech magnetics157S0030

630-8659 M75_COMMON,EEE_XXS,CPU_2_2GHZ,FB_128_HYNIX

VRAM_256,VRAM_SAMSUNG,VRAM_256_SAMSUNG

VRAM_256,VRAM_HYNIX,VRAM_256_HYNIX

[EEE:X5E]826-4393 EEE_X5ECRITICAL1

1826-4393 CRITICAL[EEE:XXT] EEE_XXTCRITICAL826-4393 1 [EEE:XXS] EEE_XXS

VRAM_128,VRAM_HYNIX,VRAM_128_HYNIX

VRAM_128,VRAM_SAMSUNG,VRAM_128_SAMSUNG

M75_COMMON

M75_DEBUG SMC_DEBUG_NO,XDP,LPCPLUS

SYNC_DATE=N/A

051-7225 A.0.0

885

SYNC_MASTER=N/ABOM Configuration

ALTERNATE,COMMON,M75_COMMON1,M75_COMMON2,M75_DEBUG,M75_PROGPARTS

M75_COMMON2 P1V8S3_1V825,SLG2AP101,SMS_MOT_DIS,YUKON_ULTRA,VGA_TERM_CONN

EXTGPU_RST_HW,ISL9504B,LVDS_SEL_RESUME,ONEWIRE_PU

PCBA,2.4GHZ,256SAM_VRAM,M75,MBP15

PCBA,2.2GHZ,128SAM_VRAM,M75,MBP15

PCBA,2.2GHZ,128HY_VRAM,M75,MBP15

PCBA,2.4GHZ,256HY_VRAM,M75,MBP15

CRITICAL

U4900

U2900

U7100

LBL,P/N LABEL,PCB,28MM X 6 MM




FB_256_HYNIX

FB_256_SAMSUNG

FB_128_HYNIX

FB_128_SAMSUNG

DSIZE

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REV.


NONE

04/24/07 -- SMC Support: Changed R5031 to 2.37K, R5032 to 9.09K to meet SIL brightness targets

04/18/07 -- Modules: Updated Intel chipset to PRQ parts16.3.0:04/20/07 -- Power FETs: Changed R7097 to 220K to maintain EnergyStar compliance with FET gate pulled to PBUS 04/20/07 -- Power FETs: Changed C7095/C7083 to 16V for proper rating of parts tied to PBUS 04/20/07 -- CPU VCore: Changed C7196 to 16V to eliminate a BOM item

See Perforce change notes for updates before Proto Release12/22/06 -- Released for Proto (Schem Rev 08, PCB Rev 01)

01/05/07 -- Clock Termination: Removed NO STUFF property from R3067

04/24/07 -- SB Decoupling: Changed L2700 from 155S0152 to 155S0333 for AVL updates

01/19/07 -- Power Sequencing: Changed power rail for U7850 to PP3V3_S5 to eliminate a leakage path

01/23/07 -- BOM: Changed C3860/61 to 22pF from 27 pF based on -R characterization (T9_noME change 41248)

01/24/07 -- Power Aliases: Updated PP3V3_S0 aliases to support above changes

01/25/07 -- Released for EVT (Schem Rev 11, PCB Rev 03)

02/19/07 -- Power Sequencing: NO STUFFed U7885 to remove GPU PGOOD from PWROK chain

02/20/07 -- GPU FB: Changed cal resistors per Nvidia PUN (R8290 to 45.3 ohm and R8291 to 24.9 ohm)

02/19/07 -- Released post-EVT to document what was built (Schem Rev 12)

02/19/07 -- GPU PGOOD: Changed C9595 to 330pF to reduce PGOOD delay on powerup02/19/07 -- GPU Reset: Changed C2885 to 0.047uF to reduce reset delay on powerup

02/19/07 -- Power Sequencing Rework: Short pins 2 and 4 of U7885 to complete PWROK chain

02/20/07 -- GPU FB: Changed unterminated-mode reference voltage to 40% (R8297 -> 1.02K, R8432/82, R8532/82 -> 2.21K)

02/26/07 -- GPU Vcore: NO STUFFed all PWRCTL related components (feature not to be supported)

02/26/07 -- SB GPIOs: Syncd page25.csa to T9_MLB to get pullup updates

02/28/07 -- Power Aliases: Moving PP1V8_GPU FET source to PP1V8_S3 rather than PP1V8_S3_ISNS to improve power delivery to GPU (rdar://5021462)

02/28/07 -- NB GFX Core: Changed Vcore controller to ISL6263B (part consolidation effort between Apple/Intersil - rdar://5009109)

03/01/07 -- Thermal Sensors: Updated topology of EMC1033 sensors (removed shorts, changed connector caps to 18pF)

03/01/07 -- LVDS Connector: Changed pin 5 of connector from NC to PP3V3_SW_LCD (in case we add extra cable for power - rdar://5024882)

03/02/07 -- Power/Signal Aliases: Added XW0900 to PP5V_S5 to enable layout improvements

03/06/07 -- FireWire Ports: Changed D4260 to PDS340 for lower height

03/06/07 -- Ethernet Connector: Removed RX shorts on Ethernet MDI lines per EMC request

17.0.0:

01/22/07 -- BOM: Selected P1V8S3_1V825 BOMOPTION to lift voltage at FB memories

01/23/07 -- BOM: Changed FB memories to new Samsung and Hynix APNs (also added new BOMOPTIONs to GPU straps)

01/24/07 -- PATA Conn: Added pass FET Q4430 to allow PCIREQ3 (ODD reset GPIO) to pullup to S0

01/25/07 -- PATA Conn: Replaced PCIREQ pass FET with OD buffer to correct a corner case during PLTRST

01/25/07 -- BOM: Updated gain of PP1V25_ENET current sense amplifier to 165 (R5432 to 165K)

01/25/07 -- Power Aliases: Updated PP5V_S0 aliases to support above changes

01/23/07 -- Released for EVT (Schem Rev 10, PCB Rev 02)

01/22/07 -- BOM: Added BOMOPTIONs for SLG2AP101 (primary) and SLG8LP537 (backup)01/22/07 -- Clock Termination: Added R3051 for Silego 537/101 compatibility

01/24/07 -- PATA Conn: Changed =PP5V_S0_ODDPWREN to =PP3V3_S0_ODDPWREN for minor power savings

02/26/07 -- Thermal Sensors: Updated topology of EMC1033 filter caps (added C5515 next to IC, moved other caps to connectors - rdar://5025773)

02/28/07 -- Left Clutch IC: Updated both I-PEX connectors to new APN (part update for shell plating)

03/01/07 -- NB GFX Decoupling/Power Aliases: Connected VCCD_CRT of NB to GND per CRT disable guidelines

03/06/07 -- SB GPIOs: Changed R2514 from pulldown to pullup to correct auto power-on issue (Linda card detect GPIO)

01/17/07 -- BOM: Consolidated 3 caps on page 59 from 132S0120 to 132S013101/17/07 -- Testpoints: Removed FUNC_TEST from NB_RESET_L and FSB_DPWR_L per PCB request

01/17/07 -- Power FETs: Corrected BOM values for 5V/3.3V S3/S0 FETs

04/03/07 -- GPU FB: Changed FB clock termination to 242 ohms (2x121) per Nvidia PUN

03/30/07 -- SIL: Changed R5031 to 2.21K and R5032 to 9.53K to raise SIL current approx 15% (lightpipe dimmed by 20%)

03/19/07 -- Power Supplies: For 1.8, 3.3 and 5V, increased cap size to 0603/0805 on VBST caps (rdar://5070179)

03/19/07 -- Power Control: Tied all 4 5V/3.3V enables (EN1, EN2, EN3, EN5) together as part of PM_G2_EN

03/20/07 -- GPU Vcore: Updated setpoints for GPU Vcore based upon Nvidia Vmin (i.e. 1.05V,1.05V,1.05V,1.125V)03/20/07 -- FB: Changed FB VREF caps to 2x0.0047uF as required in Nvidia PUN 02736-001-v07 (which requests 1x0.01uF)15.0.0:

03/30/07 -- Power Supply: Changed 1.05V power supply current limit to 10A from 8A (R7455 to 5.62k -- rdar://5095642)04/03/07 -- Power Supply: Changed numerous 10K Rs to 100K for Energy Star compliance (rdar://5102118)

04/03/07 -- Released for DVT (BOM update)

04/17/07 -- Power Sequencing: NO STUFFED U7858 and stuffed R7860 to allow SMC to drive S5 enable pins directly04/17/07 -- Released for DVT (As-Built)

04/18/07 -- GPU Misc: Added R8735-37 to implement PCI DEVID 0x407 in hardware16.1.0:

PVT

14.0.0:

01/09/07 -- Temp Sensors: NO STUFFed C5520 (circuit should have only 1 cap)

01/12/07 -- Power Supplies: Minor power supply feedback connection changes from M76

PROTO

DVT

01/19/07 -- Power Sequencing: Added C7859 to create RC delay for 1.5 and 1.05V S0 rails

01/19/07 -- GPU GPIOs: Added 2 TPs on GPIOs to make G-state externally visible

01/22/07 -- LIO Conn: Removed unnecessary aliases as T9 reference design now matches M75 (T9_noME change 40998)

03/01/07 -- NB GFX Decoupling: Added R2260 (0.3 ohm, 0603) to bring ESR of regulator output cap in spec (rdar://5000272)

03/12/07 -- Power Control: Corrected alias connections for 5V/3V3 S5 enable signals13.1.0:03/13/07 -- BOM Options: Removed HDCP BOM option from stuffing list (feature removed)

03/06/07 -- FireWire Ports: Changed D4260 to PDS540 for higher current capacity

01/25/07 -- BOM: Updated all Intel APNs to use QS parts

12.1.0:

12.0.0:

12.6.0:03/06/07 -- Power FETs: Changed Q7080 to RJK0301 which provides much lower Rds(on)

12.4.0:

12.3.0:

01/17/07 -- SMBus: Changed R5260 & R5261 from 4.7K to 3.3K

EVT_SE

11.0.0:

10.2.0:

EVT

9.5.0:

9.2.0:

9.4.0:

9.3.0:

8.1.0:

10.1.0:

9.1.0:

12.2.0:

12.5.0:

9.0.0:

8.2.0:

12.7.0:

02/28/07 -- Power Supplies: Replaced APN 152S0511 with 152S0368 (duplicate APNs for same part - rdar://5009109)

02/21/07 -- Power Sequencing: Removed U7885/C7885 to take GFX_PGOOD out of PWR_OK chain (rdar://4974927)

03/06/07 -- DDR2 Regulator: Changed FB resistors to 0.1% to raise guaranteed lowest output voltage

13.0.0:

10.0.0:

13.3.0:

02/27/07 -- ODD Conn: Changed ODD power FET to FDC606P (from FDC638P) for reduced Rds(on) (rdar://4993378)

02/26/07 -- GPU Vcore: Updated voltage setpoints to 1.000/1.070/1.125V (rdar://5021453)

02/21/07 -- FireWire: Changed to Rev C of TI FireWire MCM (APN: 338S0435)

01/22/07 -- Clocks: Changed U2900 to SLG2AP101 as primary clock chip (T9_noME change 40975)

01/19/07 -- SB GPIOs: Changed SB_GPIO42 to WOW_EN and changed pullup to pulldown (T9_noME change 40787)

01/19/07 -- Clock Termination: Changed R3050 and R3055 to bypass discrete muxes for pending change to SLG2AP10101/19/07 -- Ethernet Conn: Changed resistor short reference designators from R392x to RX392x01/19/07 -- SB Decoupling: Removed filtering for PP1V5_S0_SB_VCCGLANPLL to enable PP1V5_S0 corrections at SB

01/18/07 -- ODD Conn: Reconnected ODD power FET gate control circuitry to properly implement soft start (added one cap)

01/18/07 -- IMVP: Updated BOMOPTIONs and values for ISL9504B01/18/07 -- Clock Termination: Changed series termination on all single ended clocks to 33 ohms

13.4.0:

13.5.0:

03/19/07 -- Power Supplies: For 1.8, 3.3 and 5V, removed VBST 0-ohm series R (rdar://5070179)03/19/07 -- Power Control: Added U7858 to level shift PM_G2_EN from 3.42V to 5V03/19/07 -- Thermal Sensors: Updated U5500 power alias to indicate device should be on S3 rail

03/16/07 -- Thermal Sensors: Moved remote sensor U5500 to SMC SMBus "A" and S3 power rail to clear I2C addr clash

03/16/07 -- Yukon Power Control: Crystal caps changed to 18pF (rdar://4946795 and rdar://4945362) 03/16/07 -- NB GFX: LVDS_VREFL/VREFH changed to single pin nets to prevent LVDS glitches per Intel 03/16/07 -- Thermal Sensors: Replaced EMC1033 with second EMC1043 for improved noise filtering

03/14/07 -- Constraints: Constrained WWAN_SIM signals to 50 ohms03/14/07 -- Thermal Sensors/Aliases: Changed mounting pads of Th2H sensor connector to left clutch chassis gnd13.2.0:

01/08/07 -- GPU FB: Added VREF support for unterminated memory mode (added FETs and pulldown Rs)

12.8.0:

DVT (contd)03/08/07 -- Thermal Sensors: Added R5515/R5516 in case low pass filter is needed for EMC1033

16.0.0:

04/03/07 -- CPU Vcore: Changed R7117,C7134 and R7115,R7130 for calibration improvements (rdar://5085959)01/18/07 -- Testpoints: Added NO_TEST property to LVDS_L_DATA_N, _N, _P due to lack of layout space for TP

01/17/07 -- Power Aliases: Deleted alias that accidentally eliminated filtering on PP1V5_S0_SB_VCC1_5_B

01/17/07 -- BOM: Added Hynix BOM configurations

01/17/07 -- Power Sequencing: Added RC delay on PP1V8_S3 switcher enable

01/17/07 -- Sync with T9 noME (6.1.4) to pull in WOL_EN and Wake-on-Wireless support

01/17/07 -- Power Aliases: Moved LCD panel FET to PP3V3_S5 from S0

01/12/07 -- Power Aliases: Moved Ethernet to PP3V3_S3 from S5 (layout improvements)

01/05/07 -- GPU FB: Corrected FB CLK termination (added cap and removed connection to VDDQ)

16.2.0:04/18/07 -- Power FETs: Changed Q7095 to FDM6296 and pulled up to PBUS for better PP1V25_S0 FET Rds(on)

A.0.0:04/20/07 -- No changes. Weekly BOM release.

04/24/07 -- Released for PVT

6 88

051-7225

Revision HistorySYNC_MASTER=N/A SYNC_DATE=N/A

A.0.0

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

CPUTHMSNS can not be supported due to layout constraints

Fan Connectors

FUNC_TEST

Thermal Diode Connectors

FUNC_TEST

FUNC_TEST

LPC+ Debug Connector

FUNC_TESTFUNC_TEST

FUNC_TEST FUNC_TEST

FUNC_TEST

FUNC_TEST

FUNC_TEST

FUNC_TEST

FUNC_TEST

NO_TEST

System Validation TPs

NB NO_TESTs

6 TPs, 2 with each of above TP pairs

ICT Test PointsFunctional Test Points

Left I/O Power Connector

Battery Digital Connector

Left Clutch Barrel Connector

2 TPsper

Other Func Test Points

Current Sense Calibration

RTC Battery Connectorcalled out separately in these notes.NOTE: 10 additional GND test points are

Request for at least 10 GND test points

Left ALS Connector

NO_TEST

CPU FSB NO_TESTs

NO_TEST

GPU NO_TESTs

I550

I551

I552

I553

I554

7 88

A.0.0051-7225

Functional / ICT TestSYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)

TRUE HSTHMSNS_D_NTRUE HSTHMSNS_D_P

TRUE RSFSTHMSNS_D_PTRUE RSFSTHMSNS_D_N

CPUTHMSNS_D2_NCPUTHMSNS_D2_P

FAN_LT_PWMTRUEFAN_LT_TACHTRUE

TRUE FAN_RT_PWM

CPU_DPSLP_LTRUECPU_PWRGDTRUE

=PP3V3_S3_LTALSTRUEALS_GAINTRUELTALS_OUTTRUE

DEBUG_RESET_LTRUESMC_TRST_LTRUESMC_TDOTRUESMC_MD1TRUE

LPC_ADTRUEINT_SERIRQTRUEPM_SUS_STAT_LTRUE

SMC_RESET_LTRUESMC_TCKTRUESMC_TDITRUE

PM_SB_PWROKTRUESB_RTC_RST_LTRUEPM_STPCPU_LTRUEPM_STPPCI_LTRUEVR_PWRGD_CLKENTRUEVR_PWRGOOD_DELAYTRUE

NB_CLK100M_PCIE_NTRUE

NB_CLK100M_DPLLSS_NTRUE

NC_NB_NCTRUE TP_NB_NCSMC_BS_ALRT_LTRUE=SMBUS_BATT_SCLTRUE

PM_CLKRUN_LTRUE

PM_ENET_ENTRUE

PM_S4_STATE_LTRUE

P1V5P1V05S0_PGOODTRUECPU_DPRSTP_LTRUEIMVP6_VIDTRUE

NB_CLK96M_DOT_PTRUE

NB_CLKREQ_LTRUENB_CLK100M_PCIE_PTRUE

CPU_STPCLK_LTRUE

SMC_LRESET_LTRUEGPU_RESET_LTRUE

PLT_RST_LTRUE

=SMBUS_BATT_SDATRUEGND_BATTTRUE

LPC_ADTRUE

FWH_INIT_LTRUE

=PP5V_S0_FAN_LTTRUE

ISENSE_CAL_ENTRUE

=PPVCORE_S0_NBGFX_REGTRUE=PP5V_S0_ISENSECALTRUE

=PPVCORE_GPU_REGTRUE

USB_CAMERA_NTRUE=PP5V_S3_CAMERATRUE

USB_CAMERA_PTRUE

USB_WWAN_NTRUE=PP5V_S3_WWANTRUE

USB_WWAN_PTRUE

SMC_ONOFF_LTRUEPM_SYSRST_LTRUE

PM_DPRSLPVRTRUE

PM_RSMRST_LTRUE

FSB_CPURST_LTRUE

IMVP_VR_ONTRUE

PM_SLP_S3_LTRUEIMVP_DPRSLPVRTRUE

PM_SLP_S5_LTRUE

=PPBUS_G3H_LIO_CONNTRUE

PPVBATT_G3_RTCTRUE

NB_SB_SYNC_LTRUEFSB_DPWR_LFSB_CPUSLP_LTRUE

PCI_RST_LTRUEPM_LAN_ENABLETRUECPU_DPSLP_LTRUE

=PP3V3_S5_LPCPLUSTRUE

=PPVCORE_S0_CPU_REGTRUE

BOOT_LPC_SPI_LTRUE

LPC_ADTRUE

LPC_ADTRUEPCI_CLK33M_LPCPLUSTRUE

SMC_TX_LTRUE

LPC_FRAME_LTRUE

LINDACARD_GPIOTRUE

SMC_NMITRUE

TRUE FAN_RT_TACH

=PP5V_S0_LPCPLUSTRUE

SMC_TMSTRUE

SMC_RX_LTRUE

NB_CLK96M_DOT_NTRUE

CPU_THERMTRIP_RTRUE

NB_RESET_L

FSB_CLK_NB_PTRUEFSB_CLK_NB_NTRUE

NB_CLK100M_DPLLSS_PTRUE

TRUE FSB_LOCK_LTRUE FSB_REQ_L

TRUE FSB_HITM_LTRUE FSB_HIT_LTRUE FSB_DSTB_L_PTRUE FSB_DSTB_L_NTRUE FSB_DRDY_LTRUE FSB_DINV_LTRUE FSB_DBSY_LTRUE FSB_D_L

TRUE FSB_BNR_LTRUE FSB_BREQ0_L

TRUE FSB_ADSTB_LTRUE FSB_ADS_LTRUE FSB_A_L

TRUE LVDS_L_DATA_NTRUE LVDS_L_DATA_N

TRUE LVDS_L_DATA_P

GNDTRUE

GNDTRUE

GNDTRUE

GNDTRUE

79

65

79

79

47

58

58

79

79

45

79

47

47

23

23

78

47

47

47

46

47

47

47

28

30

30

28

84

84

56

47

65

23

79

84

79

77

47

74

82

82

78

45

58

14

40

46

79

79

23

58

47

47

84

46

47

47

46

84

84

84

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

86

86

86

87

87

87

10

13

78

53

78

47

47

46

47

45

45

45

46

46

46

25

28

29

29

28

16

30

30

46

56

45

65

45

16

58

29

30

23

45

66

28

56

45

52

49

59

49

49

44

44

44

44

46

28

25

45

13

58

36

79

45

56

25

14

14

28

45

10

47

49

47

45

45

47

45

45

47

47

47

46

45

28

30

30

30

14

14

14

14

14

14

14

14

14

14

14

14

14

14

14

77

77

77

51

51

51

51

51

51

52

52

52

7

10

8

45

53

28

45

45

45

23

25

25

45

45

45

9

23

25

25

25

9

16

22

16 45

48

25

36

25

65

10

12

84

16

16

10

28

28

24

48

56

23

47

8

45

8

8

8

24

8

24

44

8

44

45

25

16

25

10

45

25

58

25

8

28

16

10

10

24

25

7

8

8

24

23

23

30

43

23

25

45

52

8

45

43

84

23

16

14

14

22

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

73

73

73

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

Chipset "VCore" Rails

"FW" (FireWire) Rails

"GPU" Rails

3.3V-2.5V Rails 1.8V-0.9V Rails

MAX I = 0.36A

MAX I = ?.??A

"ENET" Rails

Yukon EC will not be supported

5V Rails

"G3Hot" (Always-Present) Rails

SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)

8 88

A.0.0051-7225

Power Aliases

=PP3V3_S3_TOPCASE=PP3V3_S3_LTALS

=PP3V3_S0_NB_VCCHV

=PPVCORE_GPU_REGMIN_NECK_WIDTH=0.2 mm

PPVCORE_GPU

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mmVOLTAGE=1.2V

=PPVCORE_GPU

=PPBUS_G3H_LIO_CONN

=PP5V_S0_ODD

MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUEVOLTAGE=5V

PP5V_S3

=PP5V_S0_ISENSECAL

=PPVCORE_S0_NBGFX_VSEN

PPVCORE_S0_CPUMIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUEVOLTAGE=1.25VMIN_NECK_WIDTH=0.3 mm

=PP3V3_S5_SMC

=PP5V_S5_P1V05S0

=PP5V_S0_P5VS0FET

=PP5V_S0_KBDLED

=PP3V42_G3H_LIDSWITCH

=PPVIN_G3H_P3V42G3H

=PP1V25_S0M_NB_PLL

MIN_LINE_WIDTH=0.4 mmPP3V3_GPU


=PP3V3_GPU_HDCP=PP3V3_GPU_VCORELOGIC

MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mmMAKE_BASE=TRUEVOLTAGE=1.8V

PP1V8_GPU

=PP1V8_GPU_FBVDDQ

=PP1V8_GPU_FB_VDD

=PP5V_S5_P1V5S0

MIN_LINE_WIDTH=0.4 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=3.3VMAKE_BASE=TRUE

PP3V3_GPU_TMDS

=PPVCORE_S0_NB_FOLLOW=PPVCORE_S0_SB

=PPVCORE_S0_NBCOREISNS

=PP1V25R1V05_S0_FSB_NB=PP1V25R1V05_S0_NB_VTT

=PP1V05_S0_SB_CPU_IO=PP1V05_S0_SMC_LS

=PP1V05_S0_NB_FOLLOW=PP1V05_S0_NB_PCIE

PP1V05_S0

VOLTAGE=1.05VMAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mm

=PP3V42_G3H_SMCUSBMUX=PP3V42_G3H_LIO

=PP3V3_GPU_PWRCTL=PP3V3_GPU_SMBUS_SMC_0_S0=PP2V5_GPU_LTC2900=PP3V3_GPU_VIDEOMUX=PP3V3_GPU_TMDS=PP3V3_GPU_VGASYNC

=PP3V3_GPU_DVI=PP3V3_GPU_LVDS_DDC

=PP1V25_S0_NB_VCCDMI

=PP1V25_S0_SB_DMI

=PP3V3_GPU_IFPCD_IOVDD

=PP1V25_GPU_FET

=PP3V3_GPU_TMDSBIAS

=PP1V25_ENET_ISNS

PP1V25_S0MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=1.25VMAKE_BASE=TRUE

=PP1V2_GPU_PLLVDD

=PP1V8_GPU_IFPX=PP1V8_GPU_FBIO

=PP1V8_GPU_FB_VDDQ

=PP1V8_GPU_FET

=PP1V2_GPU_PEX_IOVDD=PP1V2_GPU_PEX_PLLXVDD

=PP3V3_S5_SB_VCCSUS3_3

=PP3V3_S5_SB_CLINK1

=PP3V3_GPU_TMDS_FET

=PP1V2_GPU_H_PLLVDD=PP1V2_GPU_VID_PLLVDD

=PP3V3_S5_REG

=PP5V_S3_FET

=PP5V_S3_WWAN

=PP3V3_S5_SB_3V3_VCCSUSHDA

=PP3V3_GPU_VDD33

=PP3V3_GPU_FET

=PPDCIN_G3H_LIO_CONN

=PP3V3_S5_SB_PM=PP3V3_S5_SB_USB=PP3V3_S5_SB

=PP3V3_S5_SB_VCCSUS3_3_USB

=PP3V3_S5_SMBUS_SB_ME

PPVP_FW

VOLTAGE=33VMIN_NECK_WIDTH=0.3 mmMIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

VOLTAGE=1.95VMAKE_BASE=TRUEMIN_NECK_WIDTH=0.2 mmPP1V95_FWMIN_LINE_WIDTH=0.4 mm

PP3V3_FW

MAKE_BASE=TRUEVOLTAGE=3.3VMIN_LINE_WIDTH=0.4 mmMIN_NECK_WIDTH=0.2 mm

=PPBUS_S5_FW_FET

=PPVP_FW_SUMNODE=PPVP_FW_CPS=PPVP_FW_P3V3FW

=PPVP_FW_PORT0PPVP_FW_PORTA_UFMAKE_BASE=TRUE

=PPVP_FW_PORT1PPVP_FW_PORTB_UFMAKE_BASE=TRUE

=PP3V3_FW_REG

=PP3V3_FW_PHY=PP3V3_FW_LATEVG_ACTIVE

=PPVIN_FW_P1V95FW=PP3V3_FW_LATEVG

=PP1V95_FW_PHY

=PP1V95_FW_LDO

=PP1V8_FW_PHYOSC

=PP3V3_GPU_MIO=PP3V3_GPU_DAC

=PPBU_S0_P3V3FWPPBUS_FW_FWPWRSW_FMAKE_BASE=TRUE

=PP5V_S5_P1V25ENET

=PP5V_S3_RTUSB

=PP5V_S5_P1V25GPUFET

=PP5V_S5_REG

=PP5V_S3_SYSLED=PP5V_S3_CAMERA

=PP5V_S5_P1V8DDRREG

=PP5V_S3_IR

=PP3V3_S5_S5PWRGD

=PP3V3_S5_SB_GPIO

=PP1V2_GPU_PEX_IOVDDQ

=PP1V8_S3_REG

=PP1V8_S3M_MEM_A=PP1V8_S3_FW

=PP1V8_S3M_MEM_B=PP1V8_S3_ISNS_R

=PP5V_S5_PWRCTL

PP0V9_S3_MEM_VREFMIN_LINE_WIDTH=0.4 mmVOLTAGE=0.9VMAKE_BASE=TRUEMIN_NECK_WIDTH=0.2 mm

VOLTAGE=0.9VMAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4 mmMIN_NECK_WIDTH=0.2 mmPP0V9_S0

=PP1V5_S0_CPU

=PP1V5_S0_REG

=PP1V25_S0_FET

=PP1V25_S0M_NB_VCCA=PP1V25_S0M_NB_VCC

=PP1V25_S0_NB_PLL=PP1V25_S0_NB_VCC

=PP1V05_S0_REG

=PP1V05_S0M_NB_VCCAXM

=PPVCORE_S0_NB_R

=PP0V9_S3M_MEM_NBVREFA

=PP0V9_S3_VTTR_BUF

=PP0V9_S3M_MEM_NBVREFB=PP0V9_S3M_MEM_DIMMVREFA=PP0V9_S3M_MEM_DIMMVREFB

=PP0V9_S0_VTT_LDO

=PP1V8_S0_FET

=PP1V8_S0_NB_LVDS

PP3V3_ENET

VOLTAGE=3.3VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.4 mm

MAKE_BASE=TRUE=PP3V3_ENET_PHY

=PP3V3_ENET_FET

=PP3V3_ENET_AVDDLDO

VOLTAGE=1.9V

PP1V9_ENETMIN_LINE_WIDTH=0.4 mmMIN_NECK_WIDTH=0.2 mmMAKE_BASE=TRUE=PP1V8R2V5_ENET_PHY

VOLTAGE=1.25VMIN_LINE_WIDTH=0.6 mmPP1V25_ENET_ISNS

MAKE_BASE=TRUEMIN_NECK_WIDTH=0.2 mm

=PP1V25_S0_P1V25S0FET=PP1V25_GPU_P1V25GPUFET

PPVCORE_S0_NB_GFXMIN_LINE_WIDTH=0.5 mm


=PPVCORE_S0_CPU

=PPVCORE_S0_CPU_REG

=PPVCORE_S0_NBGFX_REG

=PP1V2_GPU_FBPLLAVDD=PP1V2_GPU_VCOREPWRCTL

MIN_LINE_WIDTH=0.6 mmVOLTAGE=1.25VMAKE_BASE=TRUE

PP1V25_GPUMIN_NECK_WIDTH=0.2 mm

=PP5V_S5_P1V8S0FET

=PP5V_S5_P1V25S0FETXW

=PP5V_S5_GPUVCORE

=PP5V_S5_P1V8GPUFET

MIN_LINE_WIDTH=0.4 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=0.9VMAKE_BASE=TRUE

PPVCORE_S0_NB_R

=PPVCORE_S0_NB

=PP1V05_S0_CPU

=PP0V9_S0M_MEM_TERM

=PP1V25_ENET_ISNS_R=PP1V2_ENET_PHY

MIN_LINE_WIDTH=0.6 mmVOLTAGE=1.25VMAKE_BASE=TRUEMIN_NECK_WIDTH=0.2 mmPP1V25_ENET

=PPVOUT_ENET_AVDDLDO

=YUKON_EC_PP2V5_ENET

=PP3V3_S5_LPCPLUS

=PP5V_S5_SB

=PP1V25_ENET_REG

=PP5V_S3_TOPCASE

=PP5V_S3_P5VS3FET

=PP1V5_S0_SB_VCC1_5_A_ATX

=PP1V5_S0_SB_VCCUSBPLL

=PP1V5_S0_LIO=PP1V5_S0_SB_VCC1_5_A_USB_CORE

=PP3V42_G3H_SB_RTC

=PP3V42_G3H_SMBUS_SMC_BSA

=PP3V3_S3_FW=PP3V3_S3_PCI=PP3V3_S3_SMBUS_SMC_A_S3=PP3V3_S3_RTALS=PP3V3_S3_SMS

=PP3V3_S3_P1V25ISNS=PP3V3_S3_SMBUS_SMC_MGMT

=PP3V3_S3_P1V8ISNS

=PP3V3_S0_NB_FOLLOW

=PP3V3_S0_FET

=PP3V3_S0_SB_GPIO=PP3V3_S0_SB_PCI=PP3V3_S0_SB_VCC3_3_IDE=PP3V3_S0_SB_VCC3_3_PCI=PP3V3R1V5_S0_SB_VCCHDA=PP3V3_S0_SB_VCC3_3_DMI=PP3V3_S0_SB_VCC3_3_VCCPCORE=PP3V3_S0_SB_VCCGLAN3_3=PP3V3_S0_SB_VCC3_3_SATA=PP3V3_S0_SB=PP3V3_S0_SB_PM=PP3V3_S0_RSTBUF=PP3V3_S0_CK505

=PP3V3_S0_SMC=PP3V3_S0_IDE

=PP3V3_S0_LPCPLUS=PP3V3_S0_SMBUS_SB=PP3V3_S0_SMBUS_SMC_B_S0=PP3V3_S0_CPUCOREISNS=PP3V3_S0_NBGFXCOREISNS=PP3V3_S0_CPUTHMSNS

=PP3V3_GPU_P3V3GPUFET=PP3V3_S5_PWRCTL

VOLTAGE=3.3V

PP3V3_S5MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

=PPVCORE_S0_NB_GFX

=PP5V_S0_SB

=PP5V_S0_LPCPLUS=PP5V_S0_FAN_LT=PP5V_S0_FAN_RT=PP5V_S0_CPU_IMVP

=PP5V_S0_SB_HPD=PP5V_S0_HDD

=PPBUS_S5_FWPWRSW

=PP5V_S0_DVI_DDC=PP5V_S0_GFXIMVP6

VOLTAGE=5V

PP5V_S0MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

=PP5V_S0_FET

=PP5V_S0_ODDPWREN=PP5V_S0_PCIREQFIX

=PP3V42_G3H_REG

MAKE_BASE=TRUEVOLTAGE=1.8VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.4 mmPP1V8_S0

=PPVIN_S0_NB_DPLL

=PP1V8_GPU_P1V8GPUFET

VOLTAGE=1.8VMIN_NECK_WIDTH=0.2 mmMAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mmPP1V8_S3

=PP3V3_S0_P3V3S0FET=PP3V3_S0_LCD=PP3V3_S3_P3V3S3FET=PP3V3_S5_P1V5P1V05PG=PP3V3_S5_ROM

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUEMIN_NECK_WIDTH=0.2 mmVOLTAGE=1.8V

PP1V8_S3_ISNS

=PP1V8_S3M_NB_VCC

=PP1V8_S3_ISNS

=PP1V8_S3M_MEM_NB=PP1V8_S0_P1V8S0FET

=PP1V5_S0_NB_TVDAC=PP1V5_S0_SB=PP1V5_S0_SB_VCC1_5_A_ARX

=PP1V5_S0_SB_VCC1_5_A

MAKE_BASE=TRUEMIN_NECK_WIDTH=0.2 mm

PP1V5_S0MIN_LINE_WIDTH=0.5 mmVOLTAGE=1.5V

=PP3V3_S3_FET

=PP3V3_S3_P3V3ENETFET

=PP3V3_S3_REMTHMSNS

=PP3V3_S0_NB_VCCA_PEG_BG

MIN_NECK_WIDTH=0.2 mmVOLTAGE=3.3V

PP3V3_S3MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

=PP3V3_S0_GPUTHMSNS=PP3V3_S0_FAN_LT=PP3V3_S0_FAN_RT=PP3V3_S0_IMVP=PP3V3_S0_GFXIMVP6=PP3V3_S0_NBCOREISNS=PP3V3_S0_ALLSYSPG=PP3V3_S0_DDC_LCD=PP3V3_S0_LVDS_MUX=PP3V3R5V_GPU_GPUISENS=PP3V3_S0_XDP=PP3V3_S0M_CK505=PP3V3_S0_GPUCLKGATE=PPSPD_S0M_MEM_A=PPSPD_S0M_MEM_B=PP3V3_S0MWOL_SB_CLINK0=PP3V3_S0MWOL_SB_VCCCL3_3=PP3V3_S0MWOL_SB_VCCLAN3_3=PP3V3_S0_PWRCTL

PP3V3_S0MIN_LINE_WIDTH=0.6 mmVOLTAGE=3.3VMAKE_BASE=TRUEMIN_NECK_WIDTH=0.2 mm

PP5V_S5

VOLTAGE=5VMAKE_BASE=TRUEMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mm

=PPVIN_S5_SMCVREF=PP3V42_G3H_PWRCTL

MIN_NECK_WIDTH=0.2 mmMAKE_BASE=TRUEVOLTAGE=3.42V

PP3V42_G3HMIN_LINE_WIDTH=0.3 mm

MIN_LINE_WIDTH=0.4 mm

MAKE_BASE=TRUEMIN_NECK_WIDTH=0.2 mmVOLTAGE=18.5V

PPDCIN_G3H

=PPBUS_S5_P1V8GPUFET=PPBUS_S5_P1V25S0FET

MIN_NECK_WIDTH=0.2 mm

PPBUS_G3H

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mmVOLTAGE=12.6V

=PPVIN_S5_CPU_IMVP_VIN

=PPVIN_S5_P5VS5

=PPVIN_S5_CPU_IMVP=PPVIN_S5_P5VP3V3

=PPVIN_S5_P3V3S5=PPVIN_ENET_P1V25ENET

=PPVIN_S0_GFXIMVP6

=PPVIN_S3_P1V8S3=PPVIN_S0_P1V5S0

=PPVIN_S0_P1V05S0=PPVIN_GPU_GPUVCORE

13

21

74

27

49

58

22

12

21

78

19

49

56

49

46

70

27

30

21

26

21

27

70

27

44

27

27

27

41

72

44

87

87

12

21

12

49

59

21

11

47

27

27

27

25

27

27

27

27

27

30

22

47

52

18

27

21

30

27

27

87

78

7

16

7

67

7

42

7

59

45

61

57

53

78

65

21

77

72

74

77

67

69

63

21

26

50

14

19

23

46

21

21

43

34

65

48

77

72

72

76

76

77

19

26

73

57

76

50

65

71

73

68

69

57

66

66

26

25

72

71

71

60

57

7

26

71

57

34

28

24

25

26

48

40

40

39

64

41 40

41 40

64

39

40

64

41

39

64

39

71

73

64 40

61

43

57

60

46

7

62

78

46

25

66

62

31

38

32

50

65

11

63

57

21

21

21

21

61

18

50

16

62

16

31

32

62

57

22

35

36

36

35

57

57

11

7

7

68

74

77

57

9

74

57

18

10

33

50

35

36

35

7

27

61

78

57

26

26

34

26

28

48

38

38

48

53

54

50

48

50

21

57

23

24

26

26

26

26

26

26

26

27

28

28

29

46

42

47

48

48

50

50

51

57

65

87

18

27

7

7

52

58

76

78

40

76

59

65 57

42

42

65

65

22

57

57

75

57

65

55 21

50

16

57

22

27

26

26

87

57

36

51

19

51

52

52

58

59

50

65

75

77

74

13

29

30

31

32

25

26

26

65

65

46

65

57

57

49

58

60

58

60

60

61

59

62

63

61

74

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

TM Hole

(Cant be PTH)

ToolingHoles

(Cant be PTH)

NotchesEdge

Chassis GNDs

Frame Holes

Top CPU TM Notch

Left CPU

Add 2 buried vias to GND

RAM Door (Torx) Holes

TM Hole

Top GPU Right

Bottom Left GPU

TM Hole

Digital Ground

TM HoleRight CPU

Thermal Module Holes

Board HOLE-VIA-P5RP25

HOLE-VIA-P5RP25

402NONE

NONESHORT

NONE

OMIT

SHLD-SM-LFOG-503040

5P75R2P7 5P75R2P7 5P75R2P7

5P75R2P7

3P7R3P2

3P7R3P2

3P7R3P2

3P2R2P7

3P2R2P7

3P2R2P7

HOLE-VIA-P5RP25

HOLE-VIA-P5RP25

SM

Signal AliasesSYNC_MASTER=(T9_MLB)

9 88

A.0.0051-7225

SYNC_DATE=08/23/2006

GND_CHASSIS_DVI_BOT

MAKE_BASE=TRUEVOLTAGE=0VMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mm

TP_USB_EXTCNMAKE_BASE=TRUE

PEG_CLK100M_N

PEG_CLK100M_P

MAKE_BASE=TRUEPEG_CLK100M_GPU_N

PEG_CLK100M_GPU_PMAKE_BASE=TRUE

USB_EXTC_P

SMC_SMS_INTMAKE_BASE=TRUE

=SMC_SMS_INT

MAKE_BASE=TRUEPM_ALL_NBGFX_PGOOD GFXIMVP6_PGOOD

VR_PWRGOOD_DELAYMAKE_BASE=TRUE

=NB_CLINK_MPWROK

=GFX_VR_EN

GFX_VIDMAKE_BASE=TRUEGFX_VR_EN

MAKE_BASE=TRUEGFXIMVP6_VID

MEM_A_AMAKE_BASE=TRUETP_MEM_A_A

MEM_B_AMAKE_BASE=TRUETP_MEM_B_A

TP_USB_EXTCPMAKE_BASE=TRUE

GND_CHASSIS_DVI_TOPMIN_LINE_WIDTH=0.5 mm

MAKE_BASE=TRUEMIN_NECK_WIDTH=0.25 mmVOLTAGE=0V

GND_CHASSIS_ENETMIN_NECK_WIDTH=0.25 mmVOLTAGE=0VMIN_LINE_WIDTH=0.5 mm

MAKE_BASE=TRUE

MAKE_BASE=TRUEVOLTAGE=0VMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mmGND_CHASSIS_RTUSB

=GND_CHASSIS_DVI_TOP

=GND_CHASSIS_DVI_BOT

=GND_CHASSIS_FW_PORT1=GND_CHASSIS_FW_PORT0U

=GND_CHASSIS_ENET

=GND_CHASSIS_FW_PORT0L=GND_CHASSIS_RTUSB

GND_CHASSIS_RAMDOOR_HOLE_1

GND_CHASSIS_LVDS_HOLE

GND_CHASSIS_RIGHT_FAN_HOLE

GND_CHASSIS_RIGHT_FAN_NOTCH

GND_CHASSIS_DIMM_NOTCH

GND_CHASSIS_LIOFLEX_HOLE

GND_CHASSIS_LINDACARD_HOLE

GND_CHASSIS_BATTCONN_HOLE

GND_CHASSIS_DVI_HOLE

GND_CHASSIS_RAMDOOR_HOLE_0

PM_SB_PWROKMAKE_BASE=TRUE

=SB_CLINK_MPWROK

=PP5V_S5_P1V25S0FETMIN_LINE_WIDTH=0.1 mm

MAKE_BASE=TRUE

PP5V_S5_P1V25S0FETMIN_NECK_WIDTH=0.1 mmVOLTAGE=5VNO_TEST=TRUE

USB_EXTC_N

=PP5V_S5_P1V25S0FETXW

GND_CHASSIS_LEFTCLUTCHMIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=0VMAKE_BASE=TRUE

=GND_CHASSIS_LEFTCLUTCH

=GND_CHASSIS_J5590

GND

VOLTAGE=0VMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.6MM

ZT09451

ZT09501

R09101

2

SH09251

2

3

ZT09701

ZT09751

ZT09801

ZT09851

ZT09301

ZT09351

ZT09401

ZT09201

ZT09651

ZT09551

ZT09901

ZT09601

XW09001 2

58 28

28

66

66

82

16

25

82

84

84

30

30

24

54 45

77 59

7 16

16

16

59

59

31

32

76

76

41

41

37

41

43

7 25

57

24

8

44

51

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

IN

IN

IN

OUT

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

IN

IN

IN

IN

IN

IN

IN

IN

OUT

BI

BI

BI

BI

LOCK*

INIT*

A20M*

A6*

A3*A4*

A14*

A16*

REQ0*REQ1*REQ2*REQ3*REQ4*

BCLK1BCLK0

THERMTRIP*

THERMDAPROCHOT*

DBR*

TRST*TMSTDOTDI

TCKPREQ*PRDY*

BPM3*BPM2*BPM1*BPM0*

HITM*HIT*

TRDY*

RS2*RS1*RS0*

RESET*

IERR*

BR0*

DBSY*DRDY*

DEFER*

BNR*

RSVD9RSVD8RSVD7RSVD6RSVD5RSVD4RSVD3RSVD2RSVD1RSVD0

SMI*LINT1LINT0STPCLK*

FERR*

ADSTB1*A35*A34*A33*A32*A31*A30*A29*A28*

A19*A18*A17*

ADSTB0*

A13*A12*

BPRI*

A20*A21*A22*A23*A24*

A26*A27*

A9*A8*A7*

A11*

A25*

THERMDC

IGNNE*

ADS*

A10*

A15*

A5*

NC

1 OF 4

CONTROL

THERMAL

XDP/I

TP S

IGNA

LS

H CLK

RESERVED

ADDR GROUP0

ADDR GROUP1

ICH

DINV1*

D31*D30*

D25*

D11*D12*D13*D14*

DSTBP0*DINV0*

D9*D8*D7*D6*

D19*D18*

DATBP1*

D0* D32*D1*D2*

D5*

D16*

D20*D21*D22*D23*D24*

D26*D27*D28*D29*

DSTBN1*

GTLREFTEST1TEST2TEST3TEST4TEST5TEST6

BSEL0BSEL1BSEL2

D33*D34*D35*D36*D37*D38*D39*D40*D41*D42*D43*D44*D45*D46*D47*

DSTBN2*DSTBP2*DINV2*

D48*D49*D50*D51*D52*D53*D54*D55*D56*D57*D58*D59*D60*D61*D62*D63*

DSTBN3*DSTBP3*DINV3*

COMP0COMP1COMP2COMP3

DPRSTP*DPSLP*DPWR*

PWRGOODSLP*PSI*

D17*

D4*D3*

DSTBN0*D15*

D10*

2 OF 4

DATA GRP 3

DATA GRP 2

MISC

DATA GRP 0

DATA GRP 1

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

NC

LAYOUT NOTE:

MAKE TRACE LENGTH SHORTER THAN 0.5".COMP0,2 CONNECT WITH ZO=27.4OHM,

MAKE TRACE LENGTH SHORTER THAN 0.5".COMP1,3 CONNECT WITH ZO=55OHM,

PM_THRMTRIP#SHOULD CONNECT TO ICH ANDGMCH WITHOUT T (NO STUB)

0.1" AWAY

PLACE TESTPOINT ONFSB_IERR_L WITH A GND

0.5" MAX LENGTH FOR CPU_GTLREF

REFERENCED TO GND

PLACE C1000 CLOSE TO CPU_TEST4PIN. MAKE SURE CPU_TEST4 IS

1%1/16W54.9

MF-LF402

685%1/16W402MF-LF

1/16W1%

MF-LF

1K

402

1%MF-LF

2.0K1/16W

402

1%

MF-LF1/16W

54.9

402

27.4

1/16WMF-LF

1%

402

1%

MF-LF1/16W

54.9

402

1%

MF-LF1/16W

27.4

402

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 16 23 58 79

7 23 79

7 14 79

7 14 79

28

7 13 23 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

30 79

30 79

30 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

14 79

14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

7 14 79

13 79

13 79

13 79

13 79

13 79

13 79

10 13 79

13 28

46 58 79

51

16 23 46 79

23 47 79

7 13 14 79

14 79

14 79

14 79

14 79

10 13 79

10 13 79

10 13 79

10 13 79

51 87

30 84

30 84

23 79

23 79

23 79

23 79

7 23 79

23 79

23 79

0

1/16WMF-LF

5%

NOSTUFF

402

1/16W5%MF-LF

1K

NOSTUFF

402

1/16W1%MF-LF

54.9

402

1%

MF-LF1/16W

54.9

40254.9

1/16WMF-LF

1%

402

54.9

1/16WMF-LF

1%

402

14 79

14 79

14 79

14 79

649

1/16WMF-LF

1%

402

1/16W5%1K

NOSTUFF

MF-LF402

X5R

NOSTUFF

0.1uF10%16V

402

OMIT

MEROMFCBGA

OMIT

MEROMFCBGA

1%

MF-LF1/16W

54.9

PLACEMENT_NOTE=Place R1024 near ITP connector (if present)402

SYNC_DATE=03/16/2007SYNC_MASTER=T9_NOME

88

051-7225 A.0.0

10

CPU FSB

XDP_BPM_L

XDP_BPM_LXDP_TCK

CPU_THERMD_N

=PP1V05_S0_CPU

=PP1V05_S0_CPU

=PP1V05_S0_CPU

=PP1V05_S0_CPU

XDP_TRST_L

XDP_TDI

XDP_TMS

XDP_TDO

XDP_TCK

FSB_A_L

FSB_A_L

FSB_A_L

FSB_ADS_L

CPU_IGNNE_L

FSB_A_L

FSB_A_L

FSB_A_LFSB_A_LFSB_A_L

FSB_A_LFSB_A_L

FSB_A_LFSB_A_LFSB_A_LFSB_A_LFSB_A_L

FSB_BPRI_L

FSB_A_LFSB_A_L

FSB_ADSTB_L


FSB_A_LFSB_A_LFSB_A_LFSB_A_LFSB_A_LFSB_A_LFSB_A_LFSB_A_LFSB_ADSTB_L

CPU_FERR_L

CPU_STPCLK_LCPU_INTRCPU_NMICPU_SMI_L

TP_CPU_RSVD0TP_CPU_RSVD1TP_CPU_RSVD2TP_CPU_RSVD3TP_CPU_RSVD4TP_CPU_RSVD5TP_CPU_RSVD6TP_CPU_RSVD7TP_CPU_RSVD8TP_CPU_RSVD9

FSB_BNR_L

FSB_DEFER_LFSB_DRDY_LFSB_DBSY_L

FSB_BREQ0_L

CPU_IERR_L

FSB_CPURST_LFSB_RS_LFSB_RS_LFSB_RS_LFSB_TRDY_L

FSB_HIT_LFSB_HITM_L

XDP_BPM_LXDP_BPM_L

XDP_BPM_LXDP_BPM_L

XDP_TDIXDP_TDOXDP_TMSXDP_TRST_LXDP_DBRESET_L

CPU_PROCHOT_LCPU_THERMD_P

PM_THRMTRIP_L

FSB_CLK_CPU_PFSB_CLK_CPU_N

FSB_REQ_LFSB_REQ_LFSB_REQ_LFSB_REQ_LFSB_REQ_L

FSB_A_L

FSB_A_L

FSB_A_LFSB_A_L

FSB_A_L

CPU_A20M_L

CPU_INIT_L

FSB_LOCK_L

FSB_D_L

FSB_D_LFSB_DSTB_L_N

FSB_D_LFSB_D_L

FSB_D_L

CPU_PSI_LFSB_CPUSLP_LCPU_PWRGDFSB_DPWR_LCPU_DPSLP_LCPU_DPRSTP_L

CPU_COMPCPU_COMPCPU_COMPCPU_COMP

FSB_DINV_LFSB_DSTB_L_PFSB_DSTB_L_NFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_L

FSB_DINV_LFSB_DSTB_L_PFSB_DSTB_L_NFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_L

CPU_BSELCPU_BSELCPU_BSEL

TP_CPU_TEST6

CPU_TEST4TP_CPU_TEST3CPU_TEST2CPU_TEST1CPU_GTLREF

FSB_DSTB_L_N

FSB_D_LFSB_D_LFSB_D_LFSB_D_L

FSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_L

FSB_D_L

FSB_D_L

FSB_D_LFSB_D_L

FSB_D_LFSB_D_L

FSB_DSTB_L_P

FSB_D_LFSB_D_L


FSB_DINV_LFSB_DSTB_L_P


FSB_D_L

FSB_D_LFSB_D_L

FSB_DINV_L

TP_CPU_TEST5

R10021

2

R10041

2

R10051

2

R10061

2

R1019

R1018

R1017

R1016

R1030

R10071

2

R10031

2

R1020

R1021

R1022

R1023R10121

2

C10001

2

U1000

N3P5P2L2P4P1R1

Y2U5R3W6

A6

U4Y5U1R4T5T3W2W5Y4

J4

U2V4W3AA4AB2AA3

L5L4K5M3N2J1

H1

M1

V1

A22A21

E2

AD4AD3AD1AC4

G5

F1

C20

E1

H5F21

A5

G6E4

D20

C4

B3

C6B4

H4

B1

AC2AC1

D21

K3H2K2J3L1

C1F3F4G3

M4N5T2V3B2C3D2D22D3F6

A3

D5

AC5AA6AB3

A24B25

C7

AB5

G2

AB6

U1000

B22B23C21

R26U26AA1Y1

E22F24

J24J23H22F26K22H23

N22K25P26R23

E26

L23M24L22M23P25P23P22T24R24L25

G22

T25N25

Y22AB24V24V26V23T22U25U23

F23

Y25W22Y23W24W25AA23AA24AB25

AE24AD24

G25

AA21AB22AB21AC26AD20AE22AF23AC25AE21AD21

E25

AC22AD23AF22AC23

E23K24G24

M26

H25

N24

U22

AC20

E5B5D24

J26

L26

Y26

AE25

H26 AA26

AF24

AD26

AE6

D6D7

C23D25C24

AF26AF1A26

R1024

13

13

13

13

12

12

12

12

11

11

11

11

79

79

79

79

79

10

10

10

10

13

13

13

13

13

8

8

8

8

10

10

10

10

10

79

79

79

79

79 79

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

VCC

VSSSENSE

VCCSENSE

VID6VID5VID4VID3VID2VID1VID0

VCCA

VCCP

VCC

3 OF 4

VSS VSS

4 OF 4

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

TBD A (Deep Sleep LFM)

TBD A (Sleep LFM)

TBD A (Auto-Halt/Stop-Grant LFM)

Current numbers from Merom for Santa Rosa EMTS, doc #22221.

TBD A (LFM)TBD A (HFM)

TBD A (Auto-Halt/Stop-Grant HFM)

TBD A (Sleep HFM)

TBD A (Deep Sleep HFM)

TBD A (Deeper Sleep)TBD A (Enhanced Deeper Sleep)TBD A (Enhanced Deeper Sleep)

TBD A (Deeper Sleep)TBD A (Deep Sleep SuperLFM)TBD A (Deep Sleep HFM)TBD A (Sleep SuperLFM)TBD A (Sleep HFM)TBD A (Auto-Halt/Stop-Grant SuperLFM)TBD A (Auto-Halt/Stop-Grant HFM)TBD A (SuperLFM)18.7 A (LFM)21.0 A (HFM)23.0 A (Design Target) 17.0 A (Design Target)

Ultra Low Voltage:Low Voltage:

(CPU INTERNAL PLL POWER 1.5V)

(CPU IO POWER 1.05V)

130 mA

(CPU CORE POWER)

Standard Voltage:44.0 A (Design Target)41.0 A (HFM)

16.8 A (Sleep SuperLFM)

16.0 A (Deep Sleep SuperLFM)

4500 mA (before VCC stable)2500 mA (after VCC stable)

9.4 A (Enhanced Deeper Sleep)

25.5 A (SuperLFM)30.4 A (LFM)

27.4 A (Auto-Halt/Stop-Grant HFM)17.0 A (Auto-Halt/Stop-Grant SuperLFM)27.4 A (Sleep HFM)

25.0 A (Deep Sleep HFM)

11.5 A (Deeper Sleep)

12 79

12 79

12 79

12 79

12 79

12 79

1/16W1%100

402MF-LF

PLACEMENT_NOTE=Place within 1 inch of CPU, no stub.

12 79

58 79

58 79

OMIT

MEROMFCBGA

OMIT

MEROMFCBGA

1001%1/16W

PLACEMENT_NOTE=Place within 1 inch of CPU, no stub.402MF-LF

8811

A.0.0051-7225

CPU Power & GroundSYNC_MASTER=T9_NOME SYNC_DATE=03/16/2007

CPU_VIDCPU_VID

CPU_VID

=PPVCORE_S0_CPU

CPU_VCCSENSE_N

CPU_VCCSENSE_P

CPU_VIDCPU_VID

=PPVCORE_S0_CPU

CPU_VID

CPU_VID

=PP1V5_S0_CPU

=PP1V05_S0_CPU

R11011

2

U1000

A7A9

B9B10B12B14B15B17B18B20C9C10

A10

C12C13C15C17C18D9D10D12D14D15

A12

D17D18E7E9E10E12E13E15E17E18

A13

E20F7F9F10F12F14F15F17F18F20

A15

AA7AA9

AA10AA12AA13AA15AA17AA18AA20AB9

A17

AC10AB10AB12AB14AB15AB17AB18

AB20AB7AC7

A18

AC9AC12AC13AC15AC17AC18AD7AD9AD10AD12

A20

AD14AD15AD17AD18AE9AE10AE12AE13AE15AE17

B7

AE18AE20AF9AF10AF12AF14AF15AF17AF18AF20

B26C26

G21V6

R21R6T21T6V21W21

J6K6M6J21K21M21N21N6

AF7

AD6AF5AE5AF4AE3AF3AE2

AE7

U1000

A4A8

B11

W1W4W23W26Y3Y6Y21Y24AA2AA5

B13

AA8AA11AA14AA16AA19AA22AA25AB1AB4AB8

B16

AB11AB13AB16AB19AB23AB26AC3AC6AC8AC11

B19

AC14AC16AC19AC21AC24AD2AD5AD8AD11AD13

B21

AD16AD19AD22AD25AE1AE4AE8AE11AE14AE16

B24

AE19AE23AE26A2AF6AF8AF11AF13AF16AF19

C5

AF21A25AF25

C8C11C14

A11

C16C19C2C22C25D1D4D8D11D13

A14

D16D19D23D26E3E6E8E11E14E16

A16

E19E21E24F5F8F11F13F16F19F2

A19

F22F25G4G1G23G26H3H6H21H24

A23

J2J5J22J25K1K4K23K26L3L6

AF2

L21L24M2M5M22M25N1N4N23N26

B6

P3

P6P21P24R2R5R22R25T1T4

B8 T23T26U3U6U21U24V2V5V22V25

R11001

2

49

49

13

12

12

12

11

11

12

10

8

8

8

8

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

WF: Consider sharing bulk cap with NB Vtt?

VCCA (CPU AVdd) DECOUPLING1x 10uF, 1x 0.01uF

VCCP (CPU I/O) DECOUPLING1x 470uF, 6x 0.1uF 0402

CPU VCORE HF AND BULK DECOUPLINGCPU VCORE VID CONNECTIONS4x 330uF, 20x 22uF 0805

22UF20%6.3V805CERM-X5R

470UF20%

D2TTANT2.5V

CRITICAL


22UF

CERM-X5R8056.3V20%

22UF

CERM-X5R8056.3V20%




6.3V22UF20%

805CERM-X5R


22UF

CERM-X5R8056.3V20%

22UF

CERM-X5R20%

8056.3V

22UF

CERM-X5R8056.3V20%

22UF

CERM-X5R20%6.3V805

20%

8056.3V22UF

CERM-X5R

22UF

CERM-X5R20%6.3V805

10V402CERM20%0.1UF



22UF

CERM-X5R8056.3V20%

22UF

CERM-X5R8056.3V20%

10V0.1UF

402CERM20%

10V0.1UF

402CERM20%

10V0.1UF

402CERM20%

10V0.1UF

402CERM20%

10V0.1UF

402CERM20%

22UF

CERM-X5R20%

8056.3V

0.01UF10%16V402CERM

PLACEMENT_NOTE=Place near CPU pin B26.603

10uF20%

6.3VX5R

CRITICAL

PLACEMENT_NOTE=Place in CPU center cavity.D2T

TANT

330UF2.0V10%

PLACEMENT_NOTE=Place in CPU center cavity.

D2TTANT

CRITICAL

330UF2.0V10%


10%

D2TTANT

CRITICAL

330UF2.0V


CRITICAL

D2TTANT

10%330UF

2.0V

051-7225


A.0.0

12 88

SYNC_MASTER=M76_MLB

CPU Decoupling & VID

=PPVCORE_S0_CPU

CPU_VIDMAKE_BASE=TRUE

IMVP6_VID

=PP1V5_S0_CPU

=PP1V05_S0_CPU

C12081

2

C12071

2

C12191

2

C12181

2

C12061

2

C12041

2

C12161

2

C12141

2

C12031

2

C12021

2

C12011

2

C12131

2

C12121

2

C12111

2

C12001

2

C12101

2

C12361

2

C12051

2

C12091

2

C12151

2

C12171

2

C12371

2

C12381

2

C12391

2

C12401

2

C12411

2

C12811

2

C1280 1

2

C1250 1

2 3

C1251 1

2 3

C1252 1

2 3

C1253 1

2 3

C1235 1

2 3

13

49

79

11

11

79 58

11

10

8

11 7

8

8

IN

BI

BI

OUT

OUT

IN

BI

IN

IN

IN

OUT

IN

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI

IN

BI

IN

IN

IN

IN

IN

IN

IN

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

NB CFG[0]NB CFG[1]

Use with 920-0451 adapter board to support CPU, NB & SB debugging.

Mini-XDP ConnectorNOTE: This is not the standard XDP pinout.

(VCC_OBS_CD)

OBSFN_C0

OBSDATA_D3

SB GPIO[8]NB CFG[8]

NB CFG[3]

NB CFG[7]NB CFG[6]

NB CFG[5]NB CFG[4]

NB CFG[2]

SB OC[4]#

(OBSDATA_A2)

SB OC[3]#

PWRGD/HOOK0

TCK0

(OBSDATA_A3)

NC

OBSFN_C1

OBSDATA_C0

OBSDATA_C2

TDO

ITPCLK#/HOOK5

RESET#/HOOK6DBR#/HOOK7

SB OC[0]#

OBSDATA_C3

SB OC[1]#

SB OC[2]#

SB OC[5]#

SB OC[6]#SB OC[7]#

TCK1SCLSDA

OBSDATA_B1

OBSDATA_A1

OBSFN_A1

TRSTn

HOOK3HOOK2

VCC_OBS_ABHOOK1

OBSDATA_D1OBSDATA_D0

OBSDATA_A3OBSDATA_A2

OBSDATA_B3OBSDATA_B2

OBSFN_A0

OBSDATA_A0

ITPCLK/HOOK4

Direction of XDP moduleon even-numbered side of J1300Please avoid any obstructions

OBSDATA_C1

XDP_PRESENT#TMSTDI

OBSDATA_B0

998-1571

OBSDATA_D2

(OBSDATA_A1)(OBSDATA_A0)

7 10 23 79

402MF-LF1/16W5%

1K

XDP

15

15

1/16W

XDP

402MF-LF

1%54.9

402

16V10%

0.1uFX5R

XDP

MF-LF

10K5%

XDP

1/16W402

MF-LF

10K5%

1/16W

XDP

402

402

16V10%0.1uFX5R

XDP

10 28

10 79

10 79

10 79

10 79

10 79

10 79

10 79

7 10 14 79

10 79

10 79

10 79

10 79

30 79 84

30 79 84

24 34

24

24 77

24

24 36

24

24

24 43

1/16W402

MF-LF

5%

1K

XDP

XDP_CONNCRITICAL

F-ST-SMLTH-030-01-G-D-NOPEGS

16 30 79

16 30 79

16

16

16

16

25 45

16

16 30 79

16

eXtended Debug Port (XDP)SYNC_DATE=12/12/2006SYNC_MASTER=T9_NOME

13

A.0.0

88

051-7225

=PP1V05_S0_CPU

NB_BSEL

PM_LATRIGGER_LEXTGPU_LVDS_EN

=PP3V3_S0_XDP

XDP_CLK_PXDP_OBS20

LVDS_CTRL_CLKLVDS_CTRL_DATA

XDP_TRST_L

XDP_DBRESET_L

USB_EXTA_OC_LSB_GPIO40

XDP_TMSXDP_TDI

XDP_CPURST_L FSB_CPURST_L

XDP_TDO

XDP_TCK

XDP_BPM_L

TP_XDP_HOOK3

SB_GPIO30USB_EXTB_OC_L

TP_XDP_HOOK2

WOW_EN

XDP_BPM_L

XDP_BPM_L

XDP_BPM_L

NB_BSEL

NB_CFGNB_CFG

NB_CFGNB_CFG

XDP_PWRGDCPU_PWRGD

SMC_WAKE_SCI_L

NB_BSELNB_CFG

USB_EXTD_OC_L

NB_CFG

XDP_CLK_N

XDP_BPM_L

XDP_BPM_L

R13991 2

R13151

2

C1300 1

2

R13311

2

R13301

2

C13011

2

R13031 2

J1300

1

10

1112

1314

1516

1718

19

2

20

2122

2324

2526

2728

29

3

30

3132

3334

3536

3738

39

4

40

4142

4344

4546

4748

49

5

50

5152

5354

5556

5758

59

6

60

78

9

12 11 10 8

8

79

BI

BI

BI

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

BI

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

H_D0*

H_D3*H_D2*

H_D33*H_D34*H_D35*

H_D1*

H_D4*

H_D10*

H_A4*H_A5*H_A6*H_A7*H_A8*H_A9*H_A10*H_A11*H_A12*H_A13*H_A14*H_A15*H_A16*H_A17*H_A18*H_A19*H_A20*H_A21*H_A22*H_A23*H_A24*H_A25*H_A26*H_A27*H_A28*H_A29*H_A30*H_A31*H_A32*H_A33*H_A34*H_A35*

H_ADS*H_ADSTB0*H_ADSTB1*

H_A3*

H_D7*H_D8*H_D9*

H_D11*H_D12*H_D13*H_D14*H_D15*H_D16*H_D17*H_D18*H_D19*H_D20*H_D21*H_D22*H_D23*

H_D25*H_D26*H_D27*H_D28*H_D29*H_D30*

H_D32*

H_D36*H_D37* H_BNR*H_D38* H_BPRI*H_D39*H_D40* H_DEFER*H_D41* H_DBSY*H_D42*H_D43*H_D44* H_DPWR*H_D45* H_DRDY*H_D46* H_HIT*H_D47* H_HITM*H_D48* H_LOCK*

H_TRDY*

H_D51*H_D52*H_D53*

H_DINV0*H_D54*

H_DINV1*H_D55*

H_DINV2*H_D56*

H_DINV3*H_D57*H_D58*

H_DSTBN0*H_D59*

H_DSTBN1*H_D60*

H_DSTBN2*H_D61*

H_DSTBN3*H_D62*H_D63* H_DSTBP0*

H_DSTBP1*H_DSTBP2*

H_SWINGH_RCOMP

H_REQ0*H_SCOMP H_REQ1*H_SCOMP* H_REQ2*

H_REQ3*H_CPURST* H_REQ4*H_CPUSLP*

H_RS0*H_RS1*

H_AVREF H_RS2*H_DVREF

H_D5*H_D6*

H_D31*

H_BREQ*

H_D24*

H_D49*H_D50*

H_DSTBP3*

HPLL_CLKHPLL_CLK*

HOST

(1 OF 10)

BI

BI

BI

BI

BI

IN

IN

IN

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

7 10 79

7 10 79

7 10 79

10 79

10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

X5R

0.1uF10%16V402

2.0K

MF-LF

1%1/16W

402

1K

MF-LF1%

1/16W402

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

10 79

7 10 79

10 79

10 79

10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

54.9

MF-LF

1%1/16W402

24.9

MF-LF

1%1/16W

402

221

MF-LF

1%1/16W

402

100

MF-LF

1%1/16W

402 X5R

0.1uF10%16V402

7 10 79

OMIT

CRESTLINEFCBGA

10 79

10 79

10 79

10 79

7 10 79

54.9

MF-LF

1%1/16W

402

7 10 79

7 30 84

7 30 84

7 10 13 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

7 10 79

SYNC_DATE=03/16/2007NB CPU Interface

051-7225 A.0.0

8814

SYNC_MASTER=T9_NOME

FSB_RS_L

FSB_RS_LFSB_RS_L

FSB_REQ_LFSB_REQ_LFSB_REQ_LFSB_REQ_LFSB_REQ_L

FSB_DSTB_L_PFSB_DSTB_L_PFSB_DSTB_L_PFSB_DSTB_L_P

FSB_DSTB_L_NFSB_DSTB_L_NFSB_DSTB_L_NFSB_DSTB_L_N

FSB_DINV_LFSB_DINV_LFSB_DINV_LFSB_DINV_L

FSB_LOCK_LFSB_TRDY_L

FSB_HITM_LFSB_HIT_LFSB_DRDY_L

FSB_CLK_NB_NFSB_CLK_NB_P

FSB_DPWR_L

FSB_DBSY_LFSB_DEFER_LFSB_BREQ0_L

FSB_BNR_LFSB_BPRI_L

FSB_ADSTB_LFSB_ADSTB_LFSB_ADS_L


FSB_A_LFSB_A_L

FSB_A_L

FSB_A_LFSB_A_LFSB_A_LFSB_A_LFSB_A_LFSB_A_LFSB_A_LFSB_A_LFSB_A_LFSB_A_LFSB_A_LFSB_A_LFSB_A_LFSB_A_LFSB_A_LFSB_A_LFSB_A_LFSB_A_L

FSB_A_LFSB_A_L


FSB_A_LFSB_A_L

FSB_A_L

FSB_A_L

NB_FSB_VREF

NB_FSB_RCOMPNB_FSB_SWING

FSB_D_L

FSB_D_L

FSB_D_L

FSB_D_L

FSB_D_LFSB_D_L

FSB_D_L

FSB_D_L

FSB_D_LFSB_D_L

FSB_D_L

FSB_D_L

FSB_D_L

FSB_CPUSLP_LFSB_CPURST_L

NB_FSB_SCOMP_LNB_FSB_SCOMP


FSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_L

FSB_D_L

FSB_D_LFSB_D_LFSB_D_L

FSB_D_L

FSB_D_LFSB_D_L

FSB_D_LFSB_D_L

FSB_D_L

FSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_L

FSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_LFSB_D_L

FSB_D_L


FSB_D_L

FSB_D_L


FSB_D_LFSB_D_L

FSB_D_L

=PP1V25R1V05_S0_FSB_NB

C14251

2

R14261

2

R14251

2

R14201

2

R14151

2

R14101

2

R14111

2

C14101

2

U1400

G17C14K16B13L16J17B14K19P15R17B16H20L19D17M17N16J19B18E19B17

J13

B15E17C18A19B19N19

B11C11M11C15F16L13

G12H17G20

B9

C8E8F12

B6E5

E2G2

M10N12N9H5P13K9M2W10Y8V4

G7

M3J1N5N3W6W9N2Y7Y9P4

M6

W3N1

AD12AE3AD9AC9AC7

AC14AD11AC11

H7

AB2AD7AB1Y3AC6AE2AC5AG3AJ9AH8

H3

AJ14AE9

AE11AH12AJ5AH5AJ6AE7AJ7AJ2

G4

AE5AJ3AH2

AH13

F3N8H2

C10D6

K5L2AD13AE13

H8K7

M7K3AD2AH11

L7K2AC2AJ10

A9

E4C6G10

C2M14E13A11H13B12

E12D7D8

W1W2

B3

B7

AM5AM7

R14211

2

30 8

IN

IN

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

BI

L_BKLT_CTRL

L_VDD_EN

PEG_TX15*PEG_TX14*PEG_TX13*PEG_TX12*PEG_TX11*PEG_TX10*PEG_TX9*PEG_TX8*PEG_TX7*

PEG_TX6*PEG_TX5*PEG_TX4*PEG_TX3*PEG_TX2*PEG_TX1*PEG_TX0*

PEG_TX15PEG_TX14PEG_TX13PEG_TX12PEG_TX11PEG_TX10PEG_TX9PEG_TX8PEG_TX7

PEG_TX6PEG_TX5PEG_TX4PEG_TX3PEG_TX2PEG_TX1PEG_TX0

PEG_RX14

PEG_RX15*PEG_RX14*PEG_RX13*PEG_RX12*PEG_RX11*

PEG_RX15

PEG_RX13PEG_RX12PEG_RX11PEG_RX10PEG_RX9PEG_RX8PEG_RX7

PEG_RX6PEG_RX5PEG_RX4PEG_RX3PEG_RX2PEG_RX1PEG_RX0

PEG_RX10*PEG_RX9*PEG_RX8*PEG_RX7*

PEG_RX6*PEG_RX5*PEG_RX4*PEG_RX3*PEG_RX2*PEG_RX1*PEG_RX0*

PEG_COMPI

PEG_COMPO

CRT_DDC_DATA

L_CTRL_DATA

LVDSB_DATA1LVDSB_DATA2

LVDSB_DATA0

LVDSB_DATA2*LVDSB_DATA1*LVDSB_DATA0*

LVDSA_DATA2

LVDSA_DATA0LVDSA_DATA1

LVDSB_CLK*

LVDS_VREFL

LVDS_IBG

TVC_RTN

TVA_RTN

TVB_RTN

TVC_DAC

TVB_DACTVA_DAC

CRT_RED*

CRT_REDCRT_GREEN*

CRT_GREEN

CRT_BLUE*CRT_BLUE

CRT_VSYNCCRT_TVO_IREF

CRT_HSYNC

CRT_DDC_CLK

L_BKLT_EN

L_DDC_CLK

TV_DCONSEL0TV_DCONSEL1

LVDSA_DATA2*

L_DDC_DATA

LVDSA_DATA1*LVDSA_DATA0*

LVDSB_CLK

LVDSA_CLKLVDSA_CLK*

LVDS_VREFH

L_CTRL_CLK

LVDS_VBG

VGA

TV

LVDS

(3 OF 10)

PCI-EXPRESS GRAPHICS

BI

BI

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

recommendation is to float both signals, see Radar #5067636.a glitch during wake-up on LVDS DATA/CLK pairs. NewNote: SR DG says to tie LVDS_VREFH/L to GND. This causes

If SDVO is used, VCCD_LVDS must remain powered with proper

should connect to GND through 75-ohm resistors.omit filtering components. Unused DAC outputsUnused DAC outputs must remain powered, but can

Can leave all signals NC if LVDS is not implemented.

decoupling. Otherwise, tie VCCD_LVDS to GND also.

Tie VCC_TX_LVDS and VCCA_LVDS to GND.

SDVO_FLDSTALL#

SDVO Alternate Function

SDVO_TVCLKIN#SDVO_INT#

SDVO_TVCLKINSDVO_INTSDVO_FLDSTALL

SDVOB_GREENSDVOB_RED

SDVOC_CLKNSDVOC_BLUE#SDVOC_GREEN#SDVOC_RED#SDVOB_CLKNSDVOB_BLUE#SDVOB_GREEN#SDVOB_RED#

SDVOB_CLKPSDVOB_BLUE

SDVOC_CLKPSDVOC_BLUESDVOC_GREENSDVOC_RED

LVDS Disable

TVDAC rails. VCCA_TVx_DAC and VCCA_DAC_BG can

Component: DACA, DACB & DACC

Composite: DACA only

TV-Out Signal Usage:

Can tie the following rails to GND:VSYNC and CRT_TVO_IREF to GND.

CRT Disable / TV-Out Enable

TV-Out Disable / CRT EnableTie TVx_DAC and TVx_RTN to GND. Must power all

Leave GFX_VID and GFX_VR_EN as NC.Tie VCC_AXG and VCC_AXG_NCTF to GND.Tie VCCA_DPLLA and VCCA_DPLLB to VCC (VCore).

Tie DPLL_REF_CLK and DPLL_REF_SSCLK to GND.

Can also tie CRT_DDC_*, L_CTRL_*, L_DDC_*, SDVO_CTRL_* andTV_DCONSELx to GND.

Follow instructions for LVDS and CRT & TV-Out Disable above.

Internal Graphics Disable

and filtered at all times!NOTE: Must keep VDDC_TVDAC powered

VCCD_CRT, VCCD_QDAC and VCC_SYNC.VCCA_CRT_DAC, VCCA_DAC_BG, VCCA_TVx_DAC,

All CRT/TVDAC rails must be powered. All

CRT & TV-Out Disable

Tie TVx_DAC, TVx_RTN, R/R#/G/G#/B/B#, HSYNC,

Tie R/R#/G/G#/B/B#, HSYNC and VSYNC to GND.

share filtering with VCCA_CRT_DAC.

S-Video: DACB & DACC only

Tie DPLL_REF_CLK* and DPLL_REF_SSCLK* to VCC (VCore).

rails must be filtered except for VCCA_CRT.

66 80

66 80

402MF-LF1/16W1%24.9

77

66 80

22

22

22

22

22

22

22

66 80

22

22

22 80

OMIT

CRESTLINEFCBGA

13

13

22

22

66 80

66 80

66 80

66 80

66 80

66 80

66 80

66 80

66 80

66 80

66 80

66 80

66 80

66 80

66 80

66 80

66 80

66 80

66 80

66 80

66 80

66 80

66 80

66 80

66 80

66 80

66 80

66 80

66 80

66 80

66 80

66 80

66 80

66 80

66 80

66 80

66 80

66 80

66 80

66 80

66 80

66 80

66 80

66 80

66 80

66 80

66 80

66 80

66 80

66 80

66 80

66 80

66 80

66 80

66 80

66 80

66 80

77

77

66 80

77

77

77 80

77 80

77 80

77 80

77 80

77 80

66 80

77 80

77 80

77 80

77 80

77 80

77 80

77 80

77 80

77 80

77 80

66 80

22

22

22

22

22

22

22

22


15 88

A.0.0051-7225

NB PEG / Video InterfacesSYNC_MASTER=T9_NOME

=TV_B_RTN

=TV_B_DAC

LVDS_B_DATA_NLVDS_B_DATA_N

LVDS_CTRL_DATALVDS_CTRL_CLK

TP_LVDS_VBG

PEG_D2R_P

PEG_D2R_PPEG_D2R_P

PP1V05_S0_NB_VCCPEG

PEG_D2R_N

PEG_D2R_N

TP_LVDS_VREFH

LVDS_A_CLK_NLVDS_A_CLK_P

LVDS_B_CLK_P

LVDS_A_DATA_NLVDS_A_DATA_N

LVDS_DDC_DATA

LVDS_A_DATA_N

TV_DCONSELTV_DCONSEL

LVDS_DDC_CLK

LVDS_BKLT_EN

CRT_DDC_CLK

=CRT_HSYNC_R=CRT_TVO_IREF=CRT_VSYNC_R

=CRT_BLUE=CRT_BLUE_L=CRT_GREEN=CRT_GREEN_L=CRT_RED=CRT_RED_L

=

M75 MLB 051-7225.bak

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