[M2] Traffic Control

Group 2Chun Han ChenTimothy Kwan

Tom BoldsShang Yi Lin

ManagerRandal HongWed. Sep 29

Overall Project Objective :

Dynamic Control The Traffic Lights

Status

Design Proposal Chip Architecture Behavioral Verilog Implementation Size estimates (Refined) Floorplanning (Refined) Behavioral Verilog simulated Gate Level Design Component Layout/Simulation Chip Layout Complete Simulation

Traffic Flows

Sensors (Blue)To detect the car entered

Sensors (Red)To detect the car leaved

ARM 1

ARM 2

Traffic Light Flow

Whenever pedestrian push the button, then this light will insert in the end of this cycle.

ARM 1

ARM 2

Red

Green Y

Green (Straight + Right) Y Red+Green(Left)

Red

Y Red

Green (Straight + Right) Y Red+Green(Left) Y

Phase A

Phase C

Phase B Phase A Phase BARM1 ARM1 ARM2 ARM2

PED

We define three phases (A,B,C) for different operations.

SW – Switch light

G – Green

R – Red

Y – Yellow

T – Time for Yellow

PED – Pedestrian

SW (1bit)

ARM (1bit)

PED(1bit)

CLK

ARM1 [1:0]FSM

Initial

G.R

Y.R

R+Left.R

Y.R

R.G

R.Y

R.Y

R.R+Left

PED

SW = 0 SW =0

SW = 1 SW = 1

T < 2 T < 2

T = 2 T = 2

SW = 1 SW = 1

SW =0

T<10

PED = 1

T = 2

PED = 1

T = 2

T<= 2 T<= 2

SW = 0

T=15

T = 2

PED = 0

T = 2

PED = 0

ARM = 0 ARM = 1

FSM For Lights

Clear (1bit)

ARM2 [1:0]PED(1bits)

Blink

T=10T < 5

Complete(1bits)

Hold until n1 or n2 changes

Light favorsn1 or n2 ?

n1 n2

T<r1? T<r2?

T>= R1?

T>= R2?

n1=0?

n2=0?

f1<=0?

f2<=0?

Switch Light

ResetT = 0

No

Yes

Yes Yes

YesYes

Yes YesNoNo

No

No No

No

Yes

No

Light favorsarm1 or arm2 ?

n1 n2

T<rleft? T<rleft?

T>= Rleft? T>= Rleft?

No

Yes

Yes Yes

YesYesNo

No

Yes

Non1 not change in T = 5?

No

No

Control

reset Pedestrian For Green light

For Red + Left

T>= Rp ?

Yes

No

For Pedestrian

n2 not change in T = 5?

n1, n2 :# of carsT :Time spent in this phaseRi , ri : Max. and Min. time for each phasefi : the control functionf1 = α1*n1+ β1 – n2 f2 = α2*n2+ β2 – n1

FPU Multiplier

FPU Mult

AdderAdd exps

MultMultiply significants

Mtmp + LeadshiftDetermine possible ovf and normalize

SigshiftY, SigY, SignYRounding more or lessDetermines sign

Special Cases – NaN/inf

FPU Multiplier Hardware

4-bit adder(RCA) – 112 Sequential Multiplier(8-bit)

8-bit RCA – 2248 2-input AND gates – 483x8bit Registers – 3364-bit decrementer – 14217 Bit Barrel Shifter -5780!!!(Programmable)

12 bit comparator – 408Other Logic gates – 14

FPU Mult. Hardware cont.

Special Case Logic(NaN/Inf) 3x4-bit comparators – 0* (use prev 12 bit comp) 2x7-bit comparator – 0* 12-bit comparator – 0* 2x12-bit MUX – 96 Other logic gates – 56

Overflow Mult Logic 3x4 bit comparator – 0* 12 bit comparator – 0* 2x 2-bit MUX – 16 Other Logic – 60 1x 8-bit MUX – 32 1x12-bit MUX – 48

FPU Mult Hardware cont. sigY

8-bit incrementer – 112 4-bit incrementer - 56 2x12-bit MUX – 96 8-bit comparator - 0* 12-bit Shifter – 0* 1-bit MUX – 4 4-bit mux - 16 Other Logic – 12

SignY 12-bit comparator – 0* 4-bit comparator – 0*

Leading Zeroes 12-bit – 340

FPU Mult. Hardware cont. Mtmp

16-bit MUX – 64 4-bit MUX – 16 1-bit MUX - 4 4 bit adder(RCA) – 112 16 Bit shifter – 0* Other logic -86

Leadshift 2x4-bit Comparator – 0* 2x16-bit shifter – 0* 2x16-bit MUX – 128 2x4-bit MUX – 32 Other logic -34

Total 8484(2704 excluding barrel shifter) Transistors with some

reuse(Reg/Mux not added for reuse operations)

Addition/Subtraction•Shifting

•Shift significants and alter exp

•Inv Signal if necessary(Add/Sub)

•Does Add/Sub in Add/Sub

•Does sign Recognition

•Make_pos

•Possibly a negative significant, thus make it a positive significant if necessary otherwise filter threw

•Overflow

•Rounding

•Special Cases

FPU Add/Sub hardware

Special Cases-0*Other Logic – 40Shifting

- 17-bit barrel shifter – 0*- 5x 5-bit comparators – 0*- Other logic – 600 (lot of gate logic to

choose shifting and get diff of exp(with adders))

- LeadingZeros12 – 0*- 3x8-bit adder

FPU Add/Sub hardware

Add/Sub12-bit RCA –336Logic Gates/Arrays – 3002:1 12-bit MUX – 48

MakePos12-bit RCA – 336Logic Gates – 426

Zero Res12-bit comparator – 0*Logic Gates – 208

FPU Add/Sub Hardware Overflow Manipulation

2x17 bit barrel-shifter – 0* 4-bit RCA Adder -112 4-bit Comparator – 0* 2:1 12 bit MUX – 48 Other logic to determine ovf – 300

Rounding 2x17 bit barrel-shifter -0* Other logic - 576 2x12-bit adder – 672 4-bit adder -112 4-bit comparator – 0*s

Total -3474

FPU Total Transistor Count

Addition/Sub – 3474Multiplier – 8484Extra Muxing + Registers for

Reuse – 1000?Total- 12958

Save more adders?

Block Diagram

Accum Reg Conv.F

8

8

12ENTER

128

Accum Reg Conv.F

8

8

12OUT or LEFT

128

s0,s1: X2

q0,q1: X2

Reg X 10

1212

Reg X 10

2:1 MUX

120

120

12 X 10

12 X 9

12 X 1

q0q1

1212

12β

n1n0

12

1212

Q_len1212

16:1 MUX

4Sel

12

s0s112

12

1212

12

12

1212

1212

Sel4

N_avgαn0-n1

αn0

q0-s0

q1-s1

α0

α1

Q(αn0-n1)

FPU

2Sel_FPU

1:16 De-MUX

4

Sel

12 192Reg.

12bit

n0n1

ROM

12

1212

β

2:1 MUX

temp

12

n_avg

Q(αn0-n1)q1-s1

q0-s0

αn0

αn0-n1

12

F

ROM

12

12

User Input

2:1 MUX

Reg12

α0,α1:X2

ROM

User Input 1/Q

Reg

Reg

User Input R,r

64

64 64

12

12 12

8 X 8 : to comparator

R,r, RL,rl for arm1&2

12

½

2:1 MUX

RegPED

PED Input11

RegPEDCLK 11

to comparator

β

8 X 8

8 X 8

8:1 MUX

8

8

INT.

Compar

8 X 2

8 X 2

8

8

FP.

Compar

2:1 MUX

1

1

FSM

SWARM

PEDCLK

Clear

FSM

11

1

11

Complete

1

ARM 1

ARM 2

PED.1

2

2

½

Accum Reg Conv.F

8

8

12ENTER

128

Accum Reg Conv.F

8

8

12OUT or LEFT

128

s0,s1: X2

q0,q1: X2

Reg X 10

1212

Reg X 10

2:1 MUX

120

120

12 X 10

12 X 9

12 X 1

q0q1

1212

12β

n1n0

12

1212

Q_len1212

16:1 MUX

4Sel

12

s0s112

12

1212

12

12

1212

1212

Sel4

N_avgαn0-n1

αn0

q0-s0

q1-s1

α0

α1

Q(αn0-n1)

FPU

2Sel_FPU

1:16 De-MUX

4

Sel

12 192Reg.

12bit

n0n1

ROM

12

1212

β

2:1 MUX

temp

12

n_avg

Q(αn0-n1)q1-s1

q0-s0

αn0

αn0-n1

12

F

ROM

12

12

User Input

2:1 MUX

Reg12

α0,α1:X2

ROM

User Input 1/Q

Reg

Reg

User Input R,r

64

64 64

12

12 12

8 X 8 : to comparator

R,r, RL,rl for arm1&2

12

½

2:1 MUX

RegPED

PED Input11

RegPEDCLK 11

to comparator

β

8 X 8

8 X 8

8:1 MUX

8

8

INT.

Compar

8 X 2

8 X 2

8

8

FP.

Compar

2:1 MUX

1

1

FSM

SWARM

PEDCLK

Clear

FSM

11

1

11

Complete

1

ARM 1

ARM 2

PED.1

2

2

½

T : 3336 X 2

T : 3336 X 2

T : 334

T : 2072

T : 14

T : 14

T : 1680 X 2

T : 96

T : 1440X2

T : 1440T : 12k T : 1680

T : 166

T : 64 X 2T : 448 X 2

T : 5000

T : 460

T : 344T : 344

Transistor Count EstimatesDevices Number of

Transistors

FPU 12,000

Registers 5,824

MUX 6240

Flow Control FSM 5,000

Light Control FSM 460

Convert to FP 6000

ROM ~1000 (?)

Comparator 688

Total 37212

InputGet q0 q1 s0 s1

Avg. q

½ , Q_L

FPU Output

Reuse

F , Ni

Give R,r Input PED, CLK

Compare T

Control Light