Low Voltage Sequential Circuit With a Ring Oscillator Clock

ELEC 6270 Low power design of Electronic Circuits Spring, 2009

Presented by Mridula AllaniUnder the guidance of Dr. Vishwani Agrawal

Dynamic Voltage and Frequency Scaling

• Power Dissipation in electronic circuits.

• The total power dissipation varies linearly with clock frequency and quadratically with supply voltage.• In idle periods a microprocessor is optimized to run at a low-voltage and less than maximum speed to save power.• Generally, a power management unit controls this operation and reduces the Vdd and fclk after detecting an idle state.• Having an internally generated clock for such designs will decrease the burden on the power-management unit and save clock power . dleakddSC

2 VIVI +)( CLKddLttotal fVCpP

2

Globally Asynchronous and Locally Synchronous Architecture

Sequential Sequential

Clock Generator

Clock Generator

• Power dissipation due to clock (appx. 40% of total) can be reduced using such architecture by designing clocks suitable for the local logic blocks.

Asynchronous Protocol Driven Communication

3

Project Overview

Ring Oscillator

Input Registers Combinational

Logic (Ripple Adder)

Output Registers

ENTITY local_synch IS PORT (set, clear, count_enable: IN STD_LOGIC; cry_out : OUT STD_LOGIC; sum_out: OUT STD_LOGIC_VECTOR( 3 DOWNTO 0 ));END local_synch;

In_reg2

cry_in

cry_out

In_reg1

sum_out

setring_clock

Sequence Generator (Binary Counter)

Clock Distribution Network

count_enable

clear

4

Design Considerations• Ripple adder critical path delay = clock period of the ring oscillator.

Td = n*(tpHL + tpLH) = 1/fclk

tpHL, tpLH respectively are the fall and rise times of a single inverter Td critical delay of the ripple adder n = number of inverters in a ring oscillator and is odd fclk frequency of the ring oscillator• Assume the propagation delay for the high-to-low or low-to-high

transitions of an inverter to be equal.tpHL + tpLH = 2*Tinv

Td = n* 2*Tinv = 1/fclk

Tinv is the inverter delay• Delays are calculated as the time between the 50% point of the input

waveform and the 50% point of the output waveform.

5

Objectives• Design a ring oscillator clock to meet the critical path delay

of the ripple adder.• Observe the variation in clock frequency of the ring

oscillator with supply voltage and compare with the theoretical values.

• Design a clock distribution network to distribute the clock generated by ring oscillator.

• Design a binary counter to supply input vectors to the ripple adder.

• Observe the variation of the average and peak powers and the delay of the complete system with supply voltage.

• Find the optimum operation condition for the system from the power delay product.

6

Tools Used

• ModelSim SE for behavioral modeling of the blocks.

• Leonardo Spectrum for gate-level synthesis.• Design Architect for transistor-level synthesis.• Eldo Spice for voltage, delay, power and

critical path delay.• ADK tsmc018 technology file for 0.18 um

models.

7

Experimental Results• Schematic Diagram of the Whole System

8

• Ring Oscillator

Voltage (V)

Clock Frequency

(GHz)

Average Power (uW)

Maximum Power (uW)

Delay(ns)

Energy = Power /

Clock frequenc

y(fJ)

Energy*Delay(E-

24Js)

1.8 0.5588 321.4063 413.1771 1.78947 575.172 1029.21

1.6 0.5071 216.509 287.3531 1.97193 426.955 841.913

1.4 0.4107 134.5032 182.2995 2.435 327.497797.456

3

1.2 0.33023 73.6066 109.5668 3.02817 222.895 674.948

1.0 0.2212 33.5073 63.5944 4.5211151.479

7 684.855

0.8 0.1055 9.9393 20.1049 9.4782 94.211892.950

7

0.6 0.0168 0.9035546 7.8281 59.5348 53.7833201.91

78

0.4 4.842E-04 0.0119375 0.117383 2065.22 24.65450916.0

75

0.2 5.61E-064.54174E-

05 0.000355178260.

87 8.09581443163

.144

Voltage (V)

Average Power (uW) Maximum

Power (uW) Delay(ps)

1.8 36.2283 134.6928 10.66338

1.6 25.3686 95.0667 12.91967

1.4 17.1228 54.9572 17.03383

1.2 11.5631 37.004 23.38268

1.0 7.9412 23.5385 31.57895

0.8 7.9287 23.8102 55.85586

0.6 6.211 8.1721 128.6984

0.4 3.0039 0.194451 400.7

0.2 0.274565 0.000531 395541.6

• Inverter

Experimental Results

9

10

Experimental Results

• From the graph, the optimum operation point is at VDD = 1V.

Theoretical Verification of Dependence of Voltage Scaling on the Frequency of Ring Oscillator

11

• Variation of frequency with the supply voltage is given by the α-power law, given by

•VDD is the supply voltage, Vth is the zero-bias threshold voltage, f is the clock frequency, k and α are constants.• Typical Vth for 0.18 um technology is 0.3932V.• ‘k’ and ‘α’ are calculated from the VDD and f values obtained for 1.8V and 1.6V supply voltage experimentally.• k = 1.097 G and α = 2.74

(VDD – Vth)α

f = k × ───────

VDDα

•The experimental results obtained for the remaining voltage 1.4V to 0.2 V in steps of 0.2V are compared to the theoretical results and are tabulated as follows..

12

Voltage (V)Observed Clock Frequency

(GHz)Theoretical Clock Frequency

(GHz)

1.4 0.4107 0.4445

1.2 0.33023 0.3697

1.0 0.2212 0.2791

0.8 0.1055 0.1720

0.6 0.0168 0.0593

0.4 4.842E-04 0.1555E-04

0.2 5.61E-06 undefined

•We observe that the calculated frequencies are found to be close to the theoretical results in almost all cases, but do not match the observed frequencies near and below threshold voltages.

Comparison of Observed and Calculated Frequencies of Ring Oscillator

Voltage (V)

Average Power (uW)

Maximum Power

(uW)Critical

Delay(ns)Average

Power*Delay

1.8 6.284 928.2791 1.0781 6.775

1.6 4.8427 636.8054 1.24825 6.045

1.4 3.5987 413.6859 1.51913 5.467

1.2 2.5949 272.8673 2.00965 5.2148

1.0 1.7407 179.5037 3.02571 5.2668

0.8 1.0849 56.7458 6.19 6.7155

0.6 0.562447 16.7108 35.187 19.79

0.4 0.031435 0.431696 1456.19 45.775

0.2 0.000582 0.001475 105682.1 61.506

Voltage (V)Clock

Frequency (GHz)

Average Power (uW)

Maximum Power (uW)

Critical Delay(ns)

Critical Delay of Ripple

Adder(ns)

1.8 0.5588

1.6 0.5071

1.4 0.4107

1.2 0.33023

1.0 0.2212

0.8 0.1055

0.6 0.0168

0.4 4.842E-04

0.2 5.61E-06

• Complete System• Ripple Adder

Experimental Results

13

14

Experimental Results

• From the graph, the optimum operation point is at VDD = 1V.

• The power-delay product of the ring oscillator was monotonically decreasing, but its energy-delay product had a minimum at 1V supply voltage.

• The power-delay product of ripple carry adder is minimum at 1V supply voltage.

• Thus, VDD = 1V is the optimum supply voltage.• The whole system could not be simulated due

to convergence errors in ELDO.

15

Conclusions

16

• The convergence errors need to be resolved.• This experiment has to be repeated for high

leakage technologies and similar trends need to be compared.

16

Future Work

17

• Dr Agrawal’s class slides for ELEC6270, Spring 2009.

• Power Management and Dynamic Voltage Scaling: Myths and Facts, David Snowdon, Sergio Ruocco and Gernot Heiser

• A Deterministic Globally Asynchronous Locally Synchronous Microprocessor Architecture, Matthew Heath and Ian Harris

• http://www.wikipedia.org/

17

References