Low Power viaSub-Threshold Circuits

Mike Pridgen

• “Logic Circuits Operating in Subthreshold Voltages”– Jabulani Nyathi and Brent Bero

• “Sub-Threshold Design: The Challenges of Minimizing Circuit Energy”– B.H. Calhoun, A. Wang, N. Verma, and A.

Chandrakasan

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Goal of Sub-Threshold Circuits

• Minimize energy– Utilize leakage currents– Sacrifice speed

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Uses of Sub-Threshold Circuits

• Standalone, low power devices– Wireless sensor nodes– RFID tags

• Burst-mode applications– Short, intensive bursts– Long, near-idle periods

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Sub-Threshold FFT

• 16 bit FFT• FFT lengths of 128 to 1024• 350mV VDD

• 10kHz• 155nJ / FFT– 350x better than microprocessor– 8x better than ASIC

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Improving Performance by Changing VBULK

• nMos– VBULK = 600mV

• pMos– VBULK = 0V

• 0 – 380mV • ID increases by 10x• Never “OFF”– ID > 0.1nA

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Body Biasing Types

• Traditional• Three main variations– SBB– DTMOS– ABB

• Plus many others

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Traditional Biasing

• nMos VBULK = GND

• pMOS VBULK = VDD

Traditional CMOS Inverter

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Switched Body Biasing

• nMos VBULK = VDD

• pMos VBULK = GND

• VDD < VTH

SBB CMOS Inverter

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Dynamic Threshold

• VBULK = VG

• Off if VDD > VTH

DTMOS Inverter

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Adjustable Bulk Bias

• VDD < VTH

• VDD > VTH • Tunable– Low Power– High Speed– TBB TBB Inverter

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Shorter Delays

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• 6 – 10x speedup

Improving Performance

• Increased VDD = Increased Speed

• VDD = .75VTH versus VDD = .5VTH – 8x faster• Bias scheme irrelevant

– More power

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Noise Effects

• TBB versus Traditional• VDD = 376.2mV• Logic 0– 0 to 200mV

• Logic 1– 225 to 376.2mV

• SBB noise margins worse

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Standard (6T) SRAM

• Adjacent cells leakage current• Fails Static Noise Margins

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Conclusions

• Bias schemes increase performance• Speed versus Power• Slight increase in noise• 6T SRAMS unusable

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Questions