Low power design of digital systems: presentation

Transcript of Low power design of digital systems: presentation

Energy-EfficientCache

AlejandroBaranda

Introduction

Variable-strengthECC

Results

Energy-Efficient CacheUsing Error-Correcting Codes

Alejandro Baranda

October 21th 2014

Alejandro Baranda Energy-Efficient Cache 1/17

AlejandroBaranda

Introduction


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Outline

1 Introduction

2 Variable-strength ECC

3 Results


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Source


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Energy efficiency

Voltage scaling

Most effective mechanism

Processors not reliable below Vccmin

Memory failures Vccmin processorDifferent line failures


AlejandroBaranda

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Energy efficiency

Voltage scaling





AlejandroBaranda

Introduction


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Energy efficiency

Voltage scaling





AlejandroBaranda

Introduction


Results

Energy efficiency

Voltage scaling





AlejandroBaranda

Introduction


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Energy efficiency

Voltage scaling

Figure: Different line failures


AlejandroBaranda

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Energy efficiency

Possible solutions

Reduce cache capacity

Error correcting codes

Increase latency and bandwidthUp to 50% of cache areaHigh cost


AlejandroBaranda

Introduction


Results

Energy efficiency

Possible solutions

Reduce cache capacity

Error correcting codes

Increase latency and bandwidthUp to 50% of cache areaHigh cost


AlejandroBaranda

Introduction


Results

Outline

1 Introduction


3 Results


AlejandroBaranda

Introduction


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Energy efficiency

Solution (I)

Variable-strength ECC

Determine multi-bit failure lines0/1 failure fast ECCMore failures more complex ECCCache protection in low voltage mode


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Energy efficiency

Solution (II)

High performance solution

Power EnergyAvoid reductions in cache capacityLittle area overheadAvoids Latency Bandwidth


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Background

Related Work: dealing with bit errors

Row/column level redundancy

Manufacturing-time testing

Upsizing transistors (100% area overhead)

Variable-strength protection in CommunicationTheory


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Background







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AlejandroBaranda

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Background

Built upon an observation

96% of lines none or one failure Vcc = 500mVSECDED ECC to all lines

Strong protection VS-ECC


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Background


Figure: Probability of e failures in a 64B cache line


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Background





AlejandroBaranda

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Background





AlejandroBaranda

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Background


Figure: Probability of e failures in a 64B cache line


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Variable Strength ECC

Cache organization

3 possible designs presented


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Cache organization

Figure: Cache organization


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Cache characterization (I)

Low voltage mode characterization phaseBefore: reset E-bits, reduce processor voltage

Associate eECC fields with first 4 ways

Deactivate remaining ways


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Figure: Active and inactive areas


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Cache characterization (II)

Traditional memory test on inactive portion

Lines written and read known patternMulti-bit failure set E-bitSingle-bit write location

Continue testing

5 errors in a line Higher voltage RestartTest correct move live data test of previouslyactive region


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Continue testing



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Continue testing



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Continue testing



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Continue testing



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Continue testing



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Continue testing



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Figure: More complex design


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Cache operation

Figure: Regular cache operation


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Outline

1 Introduction


3 Results


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Results

Reliability: 0.999

Performance loss: less than 0.1%

Energy efficiency


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Reliability: 0.999


Energy efficiency


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Reliability: 0.999


Energy efficiency


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Figure: Comparison


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Energy-Efficient CacheUsing Error-Correcting Codes

Alejandro Baranda

October 21th 2014


IntroductionVariable-strength ECCResults

Low power design of digital systems: presentation

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Transcript of Low power design of digital systems: presentation