Logic Circuits II ECE 2411

Thursday 4:45pm-7:20pm

Nathan Pihlstrom

B.S.E.E. from Colorado State University M.S.E.E. from Colorado State University M.B.A. from UCCS Ford Microelectronics, Inc./Visteon 1985 - 2000 Intel Corp. 2000-2006 Marvell 2006-2009 Hittite Microwave 2009-2011 Covidien 2011 - 2013 LSI/Avago 2013 - present UCCS Fall Semester 2013 – ECE4280/5280 UCCS Spring Semester 2014 – ECE4211/5211

My Background

Chapter 1

Binary Numbers

• Floating Point Representation:

– 11010.112 = 26.7510

– 1x24 + 1x23 + 0x22 + 1x21 + 0x20 + 1x2-1 + 1x2-2 = 26.75

2-1 = 0.5

2-2 = 0.25

2-3 = 0.125

2-4 = 0.0625

2-5 = 0.03125

One’s Complement

• Obtained by subtracting each digit from 1 1 – 0 = 1

1 – 1 = 0

• Examples 1011000 -> 0100111

0101101 -> 1010010

Two’s Complement

• Formed by:

– Leaving all least significant 0s and the first 1 unchanged

– Replacing 1s with 0s and 0s with 1s in all other higher significant digits.

• Examples: 1101100 ->

0101101 ->

1000 0010

1 100100

Subtraction with 2’s Complements

• Given X = 1010100 and Y = 1000011

• X – Y: X = 1010100

Y’= 0111101 (2’s Complement)

Sum = 1 0010001

• Y – X: Y = 1000011

X’= 0101100 (2’s Complement)

Sum = 1101111

Subtraction with 1’s Complement • Given X = 1010100 and Y = 1000011

• X – Y: X = 1010100

Y’= 0111100 (1’s Complement)

Sum = 10010000

Carry 1

Sum = 0010001

• Y – X: Y = 1000011

X’ = 0101011 (1’s Complement)

Sum = 1101110

Signed Binary Numbers

• Signed Magnitude Representation: – Left most bit indicates sign: 0 for +, 1 for –

• Signed 1’s Complement Representation: – 1’s Complement (invert) all bits including the sign bit

• Signed 2’s Complement Representation: – 2’s Complement all bits including the sign bit

• Book example of -9 using eight bits: – Signed Magnitude: 00001001 -> 10001001 – Signed 1’s Complement: 00001001 -> 11110110 – Signed 2’s Complement: 00001001 -> 11110111

Signed Binary Numbers

• Signed 2’s Complement has only one positive representation for zero.

– See table 1.3

• 1’s Complement is seldom used for arithmetic operations though easily generated.

Arithmetic Subtraction

• Generate the 2’s complement of the subtrahend and add to minuend. Discard sign bit carry out

(+A) – (+B) = (+A) + (-B)

(+A) – (-B) = (+A) + (+B)

Book Example: -6 – (-13) = -6 + 13 = +7

-6 1111_1010 -> 1111_1010

-13 1111_0011 -> 0000_1101

+7 1_0000_0111

Arithmetic Addition

• Represent positive numbers using binary

• Represent negative numbers using 2’s complement

• Discard carry out of sign bit. +6 0000_0110 -6 1111_1010

-13 1111_0011 -13 1111_0011

-7 1111_1001 (000_0111) -19 1_1110_1101

Real Numbers in Binary • Defined by IEEE754 specification

• Format

Single Precision Example: 1234.5678 is normalized to 1.2345678 x 103

with Exponent = 3, Mantissa = 12345678 Signed Exponents are biased by adding 127 (ranges from -127 to 128)

S 1 bit

Exponent 8/11 bits

Mantissa 23/52 bits

Level Bits Range Precision

Single precision 32 +1.18x10-38 to +3.4x1038 ~ 7 digits

Double precision 64 +2.23x10-308 to +1.80x10308 ~ 15 digits

Offset Binary • Value stored is offset from the actual value by the

offset value.

• Coding technique where all zeros corresponds to the minimal negative value and all ones to the maximal positive value.

• Converted to 2’s complement by inverting MSB.

• Allows high speed comparison.

Offset Binary Decimal 2’s Complement Offset Binary

7 0111 1111

6 0110 1110

5 0101 1101

4 0100 1100

3 0011 1011

2 0010 1010

1 0001 1001

0 0000 1000

-1 1111 0111

-2 1110 0101

-3 1101 0101

-4 1100 0100

-5 1011 0011

-6 1010 0010

-7 1001 0001

-8 1000 0000

Real Numbers in Binary • Example:

– Convert -14.09375 to IEEE754 single precision format: • First bit is 1 as value is negative • Convert 0.09375 to binary:

0.09375 x 2 = 0.1875 0 0.1875 x 2 = 0.375 0 0.375 x 2 = 0.75 0 0.75 x 2 = 1.5 1 0.50 x 2 = 1.00 1 So 14.0937510 = 1110.000112

• Next rewrite binary number in scientific form by moving binary point to right three places:

1.11000011 x 23

All binary number in scientific form will have a 1 on left side of binary point, so ignore (don’t store).

• Next convert Exponent to excess 127 form: 127 + 3 = 13010 = 100000102

• Thus -14.09375:

S Exponent Mantissa

1 1 0 0 0 0 0 1 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Gray Code

• Only one bit changes when going from one number to the next

• Useful for optical rotary encoders:

Error Detecting Code

• Additional bit added to bus, RAM, etc. to indicate parity. – Even parity:

• Set to one if number of ones in value is odd • Set to zero if number of ones in value is even

– Odd parity: • Set to one if number of ones in value is even • Set to zero if number of ones in value is odd

• Note: detects errors only. Error Correcting Code invented by Hamming in 1950s which can detect up to two errors and correct one.

Chapter 2

• “+” = OR Function

• “.” = AND Function

• Theorems important to remember for post place and route edits as only have defined gates to work with.

• DeMorgan’s Theorem (bubble pushing):

Bubble Pushing • Bubble Pushing Rules

– Begin at the output and work back to inputs

– Working backwards, draw each gate in a form so that bubbles cancel.

Source: Digital Logic Design Slides, James E. Stine, Jr.

Minterms and Maxterms

• Canonical Form: Simplest or Standard form of an expression

• Minterm or Standard Product – 2n Minterms for n variables – A product term in which each of the variables appears

once (complemented or uncomplemented) – AND operation

• Maxterm or Standard Sums – 2n Maxterms for n variables – A sum term in which each of the variables appears once

(complemented or uncomplemented) – OR operation

Sum of Minterms and Product of Maxterms

• Sum of Minterms

– Recall that for n variable, there are 2n Miterms and any Boolean function can be expressed as a sum of minterms or sum or product (SoP)

– The minterms whose sum results in 1’s of the 22n functions in the Truth table

• Product of Maxterms

– Each of the 22n functions of n binary variable can also be expressed as a product of maxterms

Standard Forms

Sum of Products F1 = y’ + xy + x’yz’

Product of Sums F2 = x(y’ + z)(x’ + y + z’)

Non-Standard Form F3 = AB + C(D + E)

Sum of Products F3 = AB + CD + CE

Chapter 3

• Karnaugh Maps (K-maps) used for manual gate level minimization

• Recall that any Boolean function can be expressed as a sum of minterms

• The resulting expression is always on of the two standard forms

Two Variable K-map

F = xy = (x+y)(x+y’)(y’+x)

Minterm Maxterms

F = x + y = x’y + xy’ + xy

Maxterm Minterms

Four Variable K-map

F = BD + B’D’ + CD +AD

F = BD + B’D’ + CD +AB’

F = BD + B’D’ + B’C + AD

F = BD + B’D’ + B’C AB’

Four Variable K-Map

Don’t Care Conditions

NAND and NOR

NAND Circuits

• Must be Sum of Products form

F = AB + CD = ((AB)’((CD)’)’

NOR Circuits

• Must be in Product of Sums form

Exclusive OR

• Useful for Parity Generation

P = x + y + z

Hardware Description Language (HDL)

`timescale 1ns/1ps // Verilog Model of Fig. 3.35 circuit module Simple_Circuit1(A, B, C, D, E) input A, B, C; output D, E; wire w1; and G1(w1, A, B); not G2(E, C); or G3(D, w1, E); endmodule

`timescale 1ns/1ps // Verilog Model of Fig. 3.35 circuit module Simple_Circuit2(A, B, C, D, E) input A, B, C; output D, E; wire w1; assign w1 = A && B; assign D = w1 && E; assign E = !D; endmodule

`timescale 1ns/1ps // Verilog Model of Fig. 3.35 circuit primative Simple_Cir_UDP (A, B, C, D) input A, B, C; output D ; table A B C : D 0 0 0 : 1 0 0 1 : 1 0 1 0 : 1 0 1 1 : 1 1 0 0 : 0 1 0 1 : 0 1 1 0 : 1 1 1 1 : 1 endtable endprimative