PMOSFET AND NMOSFET BROADBAND MIXER DESIGN

A THESIS SUBMITTED TO THE GRADUATE DIVISION OF

THE UNIVERSITY OF HAWAI' I IN PARTIAL FULFILLMENT

OF THE REQUIREMENTS FOR THE DEGREE OF

MASTER OF SCIENCE

IN

ELECTRICAL ENGINEERING

MAY 2008

By

Yun-Pyo Hong

Thesis Committee:

Olga Boric-Lubecke, Chairperson Victor M. Lubecke

Eric Miller

LIZ? 7

Acknowledgements

First, I would like to thank my research advisor Professor Olga Boric-Lubecke for

her guidance and help during this project. Her insight and suggestions were invaluable for

the completion of my research.

I would like to thank Professor Victor M. Lubecke, and professor Eric Miller for

very useful advices and discussions. Also, I would like to thank Ivy Lo and Byung-Kwon

Park for their help on chip testing, Alex Vergara, Wansuree Massagram, Xiaoyue Wang,

Mingqi Chen, Noah Hafner,Dung Phuong Nguyen, Issar Mostafanezhad, John E

Kiriazi,Chenyan Song, Xi Zhao, Renbin Dai, Qin Zhou, and Nicolas Petrochilos for their

great help and warm encouragements during thesis writing.

Finally, I would also like to thank my parents for their great supports

II

We certify that we have read this thesis and that, in our opinion,

it is satisfactory in scope and quality as a thesis for the degree of

master of science in Electrical Engineering.

THESIS COMMITTE

ii

•

Abstract

In this thesis work, three double balanced resistive mixers realized in a 0.25 Ii m

CMOS TSMC process were designed and fabricated in order to obtain low conversion

loss and high input third order intercept point(IIP3), and in order to compare the flicker

noise ofNMOSFET to PMOSFET. These mixers were designed for wireless applications

with RF and IF frequency ranges of I to 3 GHz, and DC to 50 MHz, respectively. The

mixer design process as well as simulated and measured results are given and discussed.

A measured conversion loss of 10.1 dB, 21.8 dB and 14.8 dB of NMOSFET and

PMOSFET mixers has been achieved respectively. Measured linearity values are 7 dBm,

17 dBm and 14 dBm for IdB compression point and 12 dBm, 7 dBm and 19.25 dBm for

third order intercept point. All measured isolation values are higher than 45 dB between

all ports. The circuit was simulated using Agilent ADS software with BSIM3v3 transistor

models and the layout has been carried out in Cadence. These mixers achieve a

broadband performance, at moderate conversion loss.

III

Table of Contents

Acknowledgement ................................................................................... 2

Abstract ......................................................................................................... 3

List of Figures .................................................................................................. 7

List of Tables ........................................................................................ 12

Chapter I: Introduction ........................................................................... 14

1.1 Motivation .......................................................................... 14

1.2 CMOS technology .................................................................. 15

1.3 PMOSFET and NMOSFET .................................................... .16

1.4 Objective and outline of thesis ................................................... 17

Chapter 2: Theoretical Description ............................................................... 19

2.1 General Description ............................................................... 19

2.2 Active Mixer ........................................................................ 21

2.3 Passive Mixer ....................................................................... 21

2.4 Unbalanced Mixer .................................................................. 22

2.5 Single Balanced Mixer ............................................................. 22

2.6 Double Balanced Mixer ........................................................... 24

2.7 Gilbert Mixer ....................................................................... 25

2.8 FET Resistive Mixer ............................................................. 25

2.9 Definition for RF Mixer Design .................................................. 27

2.9.1 Input and Output Impedance ........................................... 27

2.9.2 Harmonics ................................................................ 28

2.9.3 Third-order Inter-modulation Distortion .............................. 29

IV

2.9.4 Second-order Inter-modulation Distortion ........................... .31

2.9.5 I dB Compression Point ............................................. .3 I

2.9.6 Flicker(l/f) Noise ...................................................... 32

2.9.7 L0 Input Power ........................................................ .33

2.9.8 LO Feedthrough .......................................................... 33

2.10 CMOS Circuit Design .............................................. 34

2. I o. I MOS Transistor ........................................................ 34

2.10.2 PMOS and NMOS Design ............................................ 36

Chapter 3: CMOS Resistive Ring Mixer Design .............................................. 38

3.1 Schematic of the Mixer .......................................................... 38

3.2 Mixer Performance .............................................................. .43

3.2.1 Return Loss ............................................................. .43

3.2.2 Conversion Loss ........................................................ .49

3.2.3 Input PldB, IIP2 and IIP3 .............................................. 51

3.2.4 Flicker(l/f) Noise ........................................................ 57

3.2.5 Port-to-Port Isolation ..................................................... 58

3.3 Mixer Layout. ...................................................................... 59

Chapter 4: Chip Measurement.. ................................................................... 63

4.1 How to measure ..................................................................... 63

4.2 Summary of Measurement ........................................................ 64

4.2. I Return Loss ................................................................ 64

4.2.2 Conversion Loss .......................................................... 71

4.2.3 Input PldB, IIP2 and IIP3 .............................................. 74

4.2.4 Flicker (1/f) Noise ....................................................... 76

v

4.2.5 Port-to-Port Isolation ..................................................... 77

Chapter 5: Conclusions and Future Work ........................................................ 82

5.1 Conclusions ....................................................................... 82

5.2 Future Work ....................................................................... 82

References .......................................................................................... 84

VI

Figures

Fig. 1.I Typical heterodyne receiver (a) transceiver (b) architecture ..................... 15

Fig. 2.1 Up-conversion and Down-conversion .................................................. 19

Fig. 2.2 Multiplication of two signals in time-domain ....................................... 20

Fig. 2.3 Unbalanced mixer ...................................................................... 22

Fig. 2.4 Single balanced mixer .................................................................. 23

Fig. 2.5 Double balanced active mixer ......................................................... 24

Fig. 2.6 Double balanced resistive mixer ...................................................... 26

Fig. 2.7 Frequency spectrum of a mixer ........................................................ .30

Fig: 2.8 Graphical representation of the input and output third-order intercept point

(IIP3, OIP3) ........................................................................................ 30

Fig. 2.9 Second order distortion in a direct conversion mixer ............................... 32

Fig. 2.10 Graphical representation of the input PldB ......................................... 33

Fig. 2. I I Port-to-Port isolation of double balanced mixer .................................... .34

Fig. 2.12 Symbols for NMOS(a) and PMOS(b) transistor .................................... .34

Fig. 2.13 Cross section of NMOS transistor ................................................... 36

Fig. 3. I MOSFET schematic without matching network.. .................................. 38

VII

Fig. 3.2 Conversion loss of NMOSFET mixer as a function of device size without

matching network .................................................................................. 39

Fig. 3.3 Conversion loss of PMOSFET mixer as a function of device size without

matching network .................................................................................. 39

Fig. 3.4 NMOSFET 240 schematic with matching network ................................. .41

Fig. 3.5 PMOSFET 240 schematic with matching network .................................. 42

Fig. 3.6 PMOSFET 660 schematic with matching network .................................. 43

Fig. 3.7 The simulated return loss of NMOSFET 240 at RF, IF, and LO port, without

matching network, respectively .................................................................. 44

Fig. 3.8 The simulated return loss of PMOSFET 240 at RF, IF, and LO port, without

matching network, respectively .................................................................. .45

Fig. 3.9 The simulated return loss of PMOSFET 660 at RF, IF, and LO port, without

matching network, respectively .................................................................. 46

Fig. 3.1 0 The simulated return loss of NMOSFET 240 at RF, IF, and LO port, with

matching network, respectively ................................................................. .47

Fig. 3.11 The simulated return loss of PMOSFET 240 at RF, IF, and LO port, with

matching network, respectively ................................................................. .48

Fig. 3.12 The simulated return loss of PMOSFET 660 at RF. IF. and LO port. with

matching network, respectively .................................................................. 49

Fig. 3.13 The simulated conversion loss ofNMOSFET 240 as a function ofRF frequency

for LO power of 13 dBm .......................................................................... .49

Fig. 3.14 The simulated conversion loss of PMOSFET 240 as a function of RF frequency

for LO power of 13 dBm ........................................................................... 50

VIII

Fig. 3.15 The simulated conversion loss ofPMOSFET 660 as a function ofRF frequency

for LO power of 13 dBm ........................................................................... 51

Fig. 3.16 Input PldB ofNMOSFET 240, RF power: -40dBm, LO power: 13 dBm, RF

frequency: 2.4 GHz, IF frequency: 30 MHz .................................................... 52

Fig. 3.17 Input PldB ofPMOSFET 240, RF power: -40dBm, LO power: 13 dBm, RF

frequency: 2.4 GHz, IF frequency: 30 MHz .................................................... 53

Fig. 3.18 Input PldB of PMOSFET 660, RF power: -40dBm, LO power: 13 dBm, RF

frequency: 2.4 GHz, IF frequency: 30 MHz ..................................................... 54

Fig. 3.19 IIP2 and IIP3 of NMOSFET 240, RF power: -40dBm, LO power: 13 dBm,

Input frequency: 2.4 GHz ............................................................ 55

Fig. 3.20 IIP2 and IIP3 of PMOSFET 240, RF powe: -40dBm, LO power: 13 dBm,

Input frequency: 2.4 GHz ......................................................................... 56

Fig. 3.21 IIP2 and IIP3 of PMOSFET 660, RF power: -40dBm, LO power: 13 dBm,

Input frequency: 2.4 GHz ......................................................................... 56

Fig. 3.22 I1f noise of NMOSFET 240, RF power: -40dBm, LO power: 13 dBm, Input

frequency: 2.4 GHz ................................................................................. 57

Fig. 3.23 Iff noise of PMOSFET 240, RF power: -40 dBm, LO power: 13 dBm,

Input frequency: 2.4 GHz .......................................................................... 57

Fig. 3.24 Iff noise of PMOSFET 660, RF power: -40 dBm, LO power: 13 dBm,

Input frequency: 2.4 GHz ........................................................................... 58

Fig. 3 .. 25 Simulated LO - RF (a) and LO - IF (b) port isolation at RF frequency

2.4GHz .............................................................................................. 58

Fig. 3.26 Measured inductance and Q values for I nH , 3nH and 6 nH planar spiral

inductors ............................................................................................ 60

IX

Fig. 3.27 Layout ofNMOSFET 240 mixer, Chip size is 1.22 mm x 0.83mm ............ 61

Fig. 3.28 Layout ofPMOSFET 240 mixer, Chip size is 1.22 mm x 0.83mm ............. 61

Fig. 3.29 Layout ofPMOSFET 660 mixer, Chip size is 1.22 mm x 0.83mm ............. 62

Fig. 4.1 Mixer measurement system ........................................................... 64

Fig. 4.2 Measured return loss at RF and LO port of NMOSFET 240 as a function of RF

frequency ............................................................................................. 65

Fig. 4.3 Measured return loss at IF port ofNMOSFET 240 as a function ofRF frequency

........................................................................................................ 66

Fig. 4.4 Measured return loss at RF and LO port of PMOSFET 240 as a function of RF

frequency ............................................................................................. 67

Fig.4.5 Measured return loss at IF port of PMOSFET 240 as a function of RF

frequency... ... . . . . . . ... . . . . . . . . . ... .. . . .. . . . ... . . . ... . . . ... ... ... . .. . . . ... ... . . . ... . . . . . . ... ... ..... 68

Fig. 4.6 Measured return loss at RF and LO port of PMOSFET 660 as a function of RF

frequency ............................................................................................. 69

Fig. 4.7 Measured return loss at IF port of PMOSFET 660 as a function of RF

frequency ............................................................................................. 70

Fig. 4.8 Measured conversion loss versus available LO power of NMOSFET 240, RF

power -40 dBm, gate bias voltage = 0, 0.2, 0.45, 0.6 V, RF frequency = 2.4 GHz, LO

frequency = 2.37 GHz, IF frequency = 30 MHz ............................................... 71

Fig. 4.9 Measured conversion loss versus RF frequency ofNMOSFET 240, available LO

power \3 dBm, RF power -40 dBm, IF frequency = 30 MHz, gate bias voltage = 0, 0.2,

0.45, 0.6 V ........................................................................................... 72

x

Fig. 4.1 0 Simulated conversion loss versus RF frequency of NMOSFET 240, available

LO power 13 dBm, RF power -40 dBm, IF frequency = 30 MHz, gate bias voltage = 0,

0.2, 0.45, 0.6 V ..................................................................................... 72

Fig. 4.11 Conversion loss versus RF frequency of PMOSFET 240 and 660, available LO

power 13 dBm, RF power -40 dBm, gate bias voltage = 0 V, RF frequency = 2.4 GHz,

LO frequency = 2.37 GHz, IF frequency = 30 MHz ......................................... 73

Fig. 4.12 Conversion loss versus LO power of PMOSFET 660, available RF power -40

dBm, gate bias voltage = 0 V, RF frequency = 2.4 GHz, LO frequency = 2.37 GHz, IF

frequency = 30 MHz ............................................................................... 74

Fig. 4.13 The measurements results of each mixer on PldB .................................. 75

Fig. 4.14 The third order inter-modulation components ....................................... 75

Fig. 4.15 IIfnoise ofNMOSFET 240 ............................................................ 77

Fig. 4.16 IIf noise of PMOSFET 240 ............................................................ 78

Fig. 4.17 I/fnoise ofPMOSFET 660 ............................................................ 78

Fig. 4.18 Measurement system for LO to RF port isolation ................................... 79

Fig. 4.19 Measurement system for LO to IF port isolation ................................... 79

Fig. 4.20 Measured LO - RF (a) and LO - IF (b) port isolation at RF frequency

2.4GHz ................................................................................................ 80

XI

List of Tables

Table 4.1 The measurement results of PI dB, lIP2 and lIP3 .................................. 76

Table 4.2 Summary of each MOSFET simulated and measured results ................... 81

XII

Chapter 1

1. Introduction

1.1. Motivation

Recent growth of wireless communication systems has motivated the development of high

performance, low cost, radio transceivers. One of the key circuits in wireless transceiver modules is

the mixer used for up-conversion of modulated data stream on the transmitter side, and for

down-conversion to frequencies where analog signals can be readily digitized and further processed

on the receiver side. Mixers offering low conversion loss, low intermodulation distortion (IMD) and

requiring low LO power playa critical role in the performance of RF front-ends. A mixer produces

the intermediate frequency (IF) of sum and difference between radio frequency (RF) and local

oscillator (LO). In general, a balanced diode mixer and an active mixer provide the required

linearity for the transmission, but those mixers cannot achieve the linearity required for a

distortion-less transmission of nonlinear modulated signals. Only a double balanced resistive mixer

with high linearity, good port to port isolation due to differential LO signal and low power

consumption are superior to diode and active mixers in their intermodulation suppression

performance. Therefore, these mixers will play a more important role in future transmitter

architecture.

14

BPF LNA Mixer

PA BPF Mixer

LO

IF filter

(a)

IF filter

(b)

Demo-IF Amp dulator Data out

Mo­dulator Data in

Fig. 1.1 Typical heterodyne receiver (a) transceiver (b) architecture [14].

In this thesis work, we examine the double balanced resistive mixer design implemented in the

0.25 )j m CMOS process technology. The design steps are described, and a prototype was

fabricated as a "proof of concept" for resistive mixer.

1.2 CMOS Technology

Several technologies can be used for designing radio frequency (RF) circuits,

Bi-CMOS, GaAs, SiGe HBT, and Bipolar. But today, CMOS technology is the dominant

semiconductor technology for integration of both analog and digital circuits on a single chip.

CMOS circuits composed of NMOS and PMOS devices and provide the best speed per

15

power perfonnance. In the digital circuits, unlike NMOS or bipolar circuits, CMOS circuit has

the much smaller power dissipation and almost no static power dissipation. Power is only dissipated

in case the circuit actually switches. This allows to integrate many more CMOS gates on an IC than

in NMOS or bipolar technology, resulting in much better performance. Also it costs less than

other technologies because of their lower fabrication costs and wafer costs. Due to the

surge of faster digital processors, the gate length of a silicon device continues to decrease,

making it possible to make small and high-speed RF circuits with CMOS and Bi-CMOS

devices. Bi-CMOS devices on the same fabrication run, but it requires more mask and

more processing cycles, making it more expensive than CMOS process. On the other hand,

CMOS devices are cheaper, have a lower minimum noise figure, and beter linearity than

bipolar devices implemented in Bi-CMOS process. So CMOS technology is preferred for

implementation ofRF front-and circuitry [13].

In this thesis, design of a broadband mixer in the following CMOS process will be

explored: TSMC 0.25 Ii m.

1.3 PMOSFET and NMOSFET

The characteristic of NMOSFET and PMOSFET are of prime importance in the

perfonnance analysis of analog applications of transistors and circuits fabricated with

CMOS technology, because these transistors have different physical principles of operation.

Current through NMOSFET and PMOSFET transistors operated in linear region of

passive mixers are given by the following equations (1.1).

16

[ - JiNCm W [2(V V '] _ JipC~ W [ )V v '] d.N --2-L ",- IbN)V", -v", , [d.P --2-L 2(V",-V,bP '" - '" (1.1)

When V., )V'h and Vd , (V •.• - V,h , the transistor is turned on. and channel has

created which allows current to flow between source and the drain. The MOSFET operates

as a resistor, controlled by gate voltage. The length and width is decided by the process in

design. Electron mobility is dependent of doping concentration. Electron mobility is larger

than hole mobility. In pure silicon electron mobility is approximately 2.5 or 3.0 times larger

than hole mobility. PMOSFET with a P-doped channel between source and drain has

greater series resistance and channel length reduction than an NMOSFET. Therefore PMOS

transistors are often designed approximately 3 times wider width than a NMOS transistor,

designed for the same current and voltage. PMOS offers lower Flicker noise, however

NMOS offers a lower conversion loss.

Because of better performance ofNMOSFET in mobility, the mixer using NMOSFET

has more advantages in circuit size, the cost, high speed and linearity.

1.4 Objective and outline of thesis

The main objective of this thesis is to design a low cost. low conversion loss and

high performance linearity broadband mixer and to examine different topologies of mixer

17

and compare their performance on fabricated level.

Chapter) gives the motivation and outline to the thesis work.

Chapter2 gives theoretical background for mixer before entering the design section.

Chapter3 shows several different mixer topologies and compares them by

simulation results. Design and simulation of the chosen mixer are presented

in detail.

Chapter4 shows the summary of the mixer's chip measurement

Finally. In Chapter 5 gives the conclusions and future work.

18

Chapter 2

2. Theoretical Description

2.1 General Description

Mixer is a frequency converter which produces new frequencies different from those

present in the input signal. Because any linear time-invariant systems cannot generate

frequencies other than those present in the input signal. either time-varying or nonlinear

systems are used as mixers [I].

IfF ·0 • fRF = f/.{J ±hF ·0 ±hF

fRE = fw ±hF •

lfw lrw 2fw±hF

(a) (b)

Fig. 2.I.U p-conversion and Down-conversion

Fig. 2.1 shows the property of frequency translation using the multiplication of two

signals. In a transmitter application. the intermediate frequency I/F and a local oscillator

signal Iware mixed together to produce Iw ± IfF' and this is called up-conversion. In a

19

receiver application, an RF signal IRF and a local oscillator signal Iw are mixed

together to produce an intermediate frequency I"., and much higher frequencies

2/10 ± I". are filtered out. This is called down-conversion mixer.

The principle of a mixer is based on using a multiplication between the RF signal and

LO signal in the time domain to get the desired signal. This principle can be shown by the

following trigonometric identity:

(2.1)

From Fig. 2.1 we see that there is the product of difference frequency (001-00) at the

mixer output. The amplitude of the product is proportional to the amplitude of the RF and

the LO signals. The amplitude of the LO signal is constant so that the amplitude of IF is

transferred from the amplitude of RF signal [3].

V Baseband --+~ @ --~. V/F

t

(a) (b)

Fig.2.2 Multiplication of two signals in time-domain.

20

Mixer changes only the center frequency with the information unchanged. Passing

through the mixer. the baseband signal including the information is represented as the

envelope and the LO signal as the center frequency as shown in Fig. 2.2 (b).

2.2 Active Mixer

Active mixers achieve conversion gain and require lower LO power than passive counterparts.

Active mixers can be classified as unbalanced and balanced mixers. Balancing is a concept that

depends on how the output signal is taken from the mixer. For the active mixers. the conversion

gain is usually larger than I. while it is always less than I for the passive mixers. A mixer with high

conversion gain reduces the noise contribution from the subsequent stages. The distortion

performance of the active mixers is worse than of the passive mixers. So there is a trade-off at

distortion vs. gain. which exists between the passive and active mixers.

2.3 Passive Mixer

Passive mixers employ well known mixing techniques and excellent intermodulation

performance at the expense of higher LO power. Passive mixers not using dc power

supplies cannot amplifY the input signal and so exhibit conversion loss. Passive mixer can

be designed using diodes or MOSFETs. When used in passive mixers. MOSFETs operate

as voltage switches (linear region of operation).

21

2.4 Unbalanced Mixer

The so-called unbalanced mixer is shown in Figure 2.3 and is the simplest of the active

mixers. Port-to-Port isolation is a mixer concept that for example determines what fractions

of the IF signal appears at the RF output. Feedthrough between different ports are

undesirable in mixer design and can affect preceding or following circuits. It can be shown

that the resulting components from mixing in the unbalanced mixer is both (OJ"I + OJ,,,!)

and the unwanted (OJIft) frequency. This phenomenon is called IF-feedthrough and is

undesirable.

Fig. 2.3 Unbalanced mixer.

2.5 Single Balanced Mixer

The single balanced mixer is an improvement over the unbalanced mixer but it also

has its disadvantage. In this mixer structure the output is taken differential as shown in

Figure 2.4. The signal is taken from two branches. therefore IF feed through from each

branch cancels one another.

22

In this mixer the transistor of RF port always works in the saturation region. As shown,

the RF signal is applied at the gate of the device of RF port so that it is converted to a

current signal. The DC voltage of LO+ and LO- transistor are set around the threshold level.

As the LO signal is applied, LO+ and LO- transistor will switch on and off in tum. While

one of the LO transistor is on, the other is off. This requires the LO signal large enough to

drive the complementary switch. In this case, the RF signal is multiplied by the LO signal.

If we assume the LO signal is an ideal square wave, then the IF signal can be expressed as

following:

(2.3)

Fig. 2.4 Single balanced mixer.

23

The advantage of this structure is the rejection ofRF feedthrough. As the IF signal is

taken from both branches and follows the load resistors, the IF signal is derived from the

difference of the two branches. So the RF feedthrough from both branches can cancel

each other. On the other hand. the feedthrough of the LO signal will appear at the output

[2].

2.6 Double Balanced Mixer

By the combination of two single balanced mixers, we can get the double balanced

mixer, which is shown in Fig. 2.5

+ 1E"_

LO

<> RE'

Fig. 2.5 Double balanced active mixer.

The nonlinearity and noise performance of the double balanced mixer are better

compared to the single balanced mixer. But it consumes larger current than the single

balanced mixer.

Compared to the single balanced mixer, the double balanced mixer can cancel the

feedthrough of both the LO and the RF signal. But this only happens under ideal

conditions. Actually, the mismatches at the RF or the LO port will cause some

feedthrough.

2.7 Gilbert Mixer

The Gilbert mixer which is another type of the double balanced mixer has the

advantages that it rejects both IF- and LO frequency components at the output. The mixer

is shown in Figure 2.5. This kind of mixer is used in the design of the power mixer. The

rejection of IF- and LO frequency components is under ideal conditions. In practice, there

is always a little amount of feedthrough. The mixer contains a voltage to current

converter which is composed of transistors RF+ and RF-. A difference in voltage is

transformed to a difference in current through transistors RF+ and RF-. The currents !if +

and !if - generated from transistors RF+ and RF- are switched through the transistors

LO+ and LO-. The ideal LO is a square wave. This square wave should be large enough

to switch the transistors LO+ and LO- totally on when it is high and totally off when it is

low [3].

2.8 FET Resistive Mixer

The passive FET mixer, normally called the FET resistive mixer, operates in the

linear region, without any dc bias applied to the channel. The FET mixer uses the channel

resistance. When no dc drain-to-source voltage is applied, each MOS transistor of Fig.2.6

operates in its linear region, as a switch. Each switch is driven between its "on" and "oft"

25

states by applying the LO signal to its gate. The theoretical optimum conversion loss for

an ideal balance passive mixer is equal t02010g(~)=-3.9dB. The ~ term is the ratio 7r 7r

of the signal voltage to IF voltage. These assuming that LO signal at the gate is a square

waveform and the Ron resistance is zero, the RF and IF ports are conjugately matched, all

intermodulation (1M) products are resistively terminated, and no parasitic resistive or

reactive losses exist. The above analysis has been generalized to show that when matched

loads are presented to each 1M product, and the RF, IF, and image signals are conjugately

matched. Also, when all 1M products and the sum (fL + fR) product are reactively

terminated, the IF is conjugately matched, and the RF and image signals are identically

terminated, then the theoretical minimum conversion loss is 3 dB, with the lost energy

equally divided between conversion to the image, and reflection-loss at the signal

frequency [4],[12]. The advantages of such mixers are very low distortion, low IIfnoise,

no shot noise and good isolation; the conversion loss of such mixers is comparable to

diode mixers but the disadvantage is large LO power requirement.

j-LO

Fig. 2.6 Double balanced resistive mixer.

26

2.9 RF Mixer Design Parameters

2.9.1 Input and Output Impedance

In a super-heterodyne receiver, there is an off-chip image reject filter between the

LNA and the mixer. Since the mixer input is connected to an off-chip component with a

typical impedance of 50 n, it needs to be matched to avoid reflections connecting image

reject filter to the mixer. In a direct conversion receiver, there is no image reject filter

between the LNA and the mixer, so the mixer is directly connected to the LNA output

without going off-chip. However, since the mixer in this project is being designed

without an LNA preceding it, the inputs would have to come from off-chip and the input

needs to be matched to the source impedance that will drive it. The design assumes the

input impedance (Zo) is 50 n, since this is the source impedance of almost all input

sources. The input reflection coefficient (Sil ) is a good measure of the input match. Sil

is defined as the ratio of the reflected wave voltage to the incident wave voltage at the

input of the mixer and can be calculated using equation (2.3)

(2.3a)

(2.3b)

For a perfect input match Zin = Zo = 50 n. In most practical cases it is not

necessary to have a perfect match. An S II < -10 dB, which corresponds to a reflection of

less than 10%, is usually sufficient. The output of the mixer for a direct conversion

receiver is at baseband so there is no need to match the output of the mixer to the load

27

impedance. The load impedance of the mixer is the input impedance of the baseband

channel selection filter.

2.9.2 Harmonics

The nonlinear system can be modeled using the following function:

y(t)=a,s(t) + a,s' (I) + a,s' (t) (2.6)

Here y(t) is the output and s(t) is the input. The third-order polynomial specifies the

third-order nonlinearity. Because of this nonlinearity, distortion is generated. Although

there are many measures of nonlinearity, the most commonly used in RF design, are

third-order intercept (IP3) and I-dB compression point [2].

Using the function (2.6) with an input signals(t) = AcosoV. then the function of the

output can be derived as:

y(t) = a,A cos(av) +a,A' cos'(av) +a,A' cos'(av) (2.7a)

a A' a A' = A cos(aV) +_'_(1 +cos(2aV» + _'_(3 cos(aV) +cos(3Ii1ot))

2 4 (2.7b)

=-'-+ a,A+-'- COS(liIot)+-'-cos (21i101)+-'-cos(31i10t) (2.7c) a A' ( 3a A' ) a A' a A' 2 4 2 4

In the (2.7c) expression it can be seen that frequency components of liIol, 21i101 and

3 liIot are generated at the output. The liIo component is called the fundamental

frequency and the higher order terms are called "harmonics". Depending on how the

28

output is taken from the circuit different observations can be made. If the signal is taken

out as differential, the even-order harmonics will vanish.

2.9.3 Third-order Inter-modulation Distortion

If two tones are applied to a mixer they will produce distortion at many different

frequencies in the mixer's output. Many of these components lie outside the desired

signal band and are filtered out at some point in the receiver chain. However, some do

appear in the signal band and cannot be filtered. If two input tones, at f1 + fLO and f2 +

fLO, are close in frequency the intermodulation components at 2f2 - f1 and 2f1 - f2 will

be close to f1 and f2, making them difficult to filter without also removing the desired

signal. These products are called third-order intermodulation (1M3) products. Figure 2.3

shows the frequency spectrums at the input and output of a typical mixer including the

1M3 products.

The third-order intercept point is used to measure the intermodulation corruption.

Since the desired signal is proportional to A of 20 log alA in original tones and the

third-order product is proportional to A' of 20 log 3a,A' in third order products, this 4

point is defined as the cross point of these two curves [6]. This is shown in the following

Fig. 2.7 and Fig. 2.8.

29

Desired Output

7\ I I 1.

2'1-'2 " '2 2f2"" t .~ ---' ~/ third Order

Inermodulatlon Components

Fig. 2.7 Frequency spectrum ofa mixer.

2nd-Order PIO~!.

Slope c 2:1

Fig. 2.8 Graphical representation of the input and output third-order intercept point (IIP3, OIP3).

30

Output

P~rLimit

2.9.4 Second-order Inter-modulation Distortion

Second-order distortion perfonnance is not critical in a mixer that is downconverting

its input to an IF, since the second order products are out of the signal band. However, a

mixer that is converting directly down to baseband has very stringent IIP2 requirements.

To see why this is true, consider two interferers at f. + Iw and J; + 1 w shown in

Fig. 2.9. If f. and J; are approximately equal, their second order intennodulation

products at f. - J; and I, - f. lie near DC, which is in the signal band.

Interferers

/1 Desired signal

/

RF

Fig. 2.9 Second order distortion in a direct conversion mixer.

2.9.S PldB Compression Point

The P I dB is defined as the input or output signal level where the gain is decreased

by I dB from its ideal value. Like IIP3, P-ldB is used to estimate the largest input that a

mixer can handle. However, IIP3 is specified by extrapolating the first and third order

curves from their values with small inputs, while PldB is actually measured under large

signal input conditions. It is straightforward to show that if the compression is caused

exclusively by third-order nonlinearity the input PldB is

31

PldB = lIP' - 9.6dB (2.8)

However, it is often the case that nonlinearities higher than third-order contribute to

the gain compression or the supply headroom limits the output signal. Both of these cause

(2.8) to be inaccurate.

15

i 10

J I

5

o I i -5

I -10

/

-20

/ V

-15

(~ ,,~~

§.,.. 0

/' ~

.,.// /"

I

-10 -5 o Input Power (dBm)

Fig. 2.10 Graphical representation of the input PldB.

2.9.6 Flicker(l/t) Noise

-Gain

--- Pout Data - - Pout Unear

The Flicker noise is inversely proportional to the frequency. The flicker noise is also

called IIf noise. The flicker noise associated with MOS devices is much more severe than

that with bipolar devices, which has profound effect on analog intergrated circuits,

especially for narrow band direct conversion receivers. In a direct-conversion receiver,

Flicker noise degrades the signal-Io-noise ratio (SNR) and total noise figure (NF), which

32

results in the degradation of receiver sensitivity. The Flicker noise not only degrades the

noise performance of mixers and phase noise of oscillators, but also adds noise directly to

the base band [9]. PMOS has lower Flicker noise density than NMOS, possibly due to

the fact that channel in PMOS is a little bit further away from the surface. Flicker noise is

associated with the nature of MOS device and there is no effective solution today to

decrease it.

2.9.7 LO Input Power

The purpose of the LO signal is to switch the mixer on and off. In order to operate

properly, a mixer must be driven at the LO port by a sufficiently large LO signal. This

signal's size is limited by the power delivered by the oscillator generating the LO signal.

2.9.S LO Feedthrough

In a perfect mixer, the RF and LO signals would not be present at the IF port, and

the LO would not be present at the RF port. In most receive mixers, it is important to

have isolation between the LO and RF ports. Since the LO signal is usually a much

stronger signal that the other two ports, a significant amount of it may leak to the mixers

input and then leak back to the antenna through the reverse isolation of the LNA. This LO

signal at the antenna will radiate out and can interfere with other nearby receivers. Also,

LO (or RF) feed through signals at the IF port is that these signals may cause other

spurious products later in the chain and decrease the PldB of the mixer.

33

RF: II

~ RF ~ Q9 • II

RF:LO "-l.Jw .,

LO Fig. 2.11 Port-to-Port isolation.

2.10 CMOS Circuit Design

2.10.1 MOS Transistor

Most popular technology for realizing microelectronic circuits makes use of MOS

transistors. The MOS transistor is a device known as a FET, Field Effect Transistor. MOS

stands for Metal- Oxide- Semiconductor which describes the gate, insulator and the

channel region material. Today however, most MOS technologies utilize polysilicon

gates rather than metal gates structure. The semiconductor material, used as the transistor

starting material, is usually silicon and termed the substrate. There are two types of MOS

transistors- NMOS and PMOS. The most commonly used symbols that are used for MOS

transistors are shown in Fig. 2.12.

,

~~ .s MOSFET_NMOS MOSFET1

(a)

cmosn

•

•• is

MOSFET _PMOS MOSFET1

(b)

----,

~~ i L_~ _____ ----.J

8SIM3 M()\j,,1 cmosp

Fig. 2.12 Symbols for NMOS(a) and PMOS(b) transistor.

34

Most commonly used symbols for NMOS and PMOS transistors Fig. 2.1 3 shows a

cross sec tion of a sili con NMOS transistor. Source (S) and drai n (D) reg ions are heavi ly

doped n-type reg ions implan ted into lightl y doped p-type substrate. Between the drai n

and source reg ion si licon oxide is grown. A conducti ve material, most often

polycrystalline si licon (po ly si licon), covers the ox ide and fo rms the gate (G) of the

transistor. With no voltage applied to the ga te, n+ drain and source regions are separated

by the p- substrate. The sepa rat ion between those regions is ca lled the channel length L.

For an NMOS transisto r th e source term inal is defined as the terminal that has a lower

voltage, wh ile the de finition is oppos ite fo r PMOS transistors. Applying a small pos itive

voltage to the gate causes pos iti ve carr iers in the channel under the gate to repu lse and a

depletion area is formed. A larger positive gate vo ltage attracts negative mobi le carriers

from the source and drain reg ions and an n-cha nne l is formed under the gate .

The NMOS tra nsisto r is a so ca lled n-channel tra nsistor where electrons are used to

conduct current, while holes are used to conduct current in the PMOS transistor. With

that, current flows from dra in to source in a NMOS transistor and in the opposite

direct ion in a PMOS tra nsistor, when turned on.

Drain (D)

b======;Sili,:on di Oxid, msulation

p

,bonn,t

Source Substrate (S5)

+---+~ n-dcp<d "glon

substrate

L ____ ~ ~l,,~ cOII<,m

Sour" (S)

(a)

c;::====-:::,). Sit«oll di O",d, mS'Jla Ion

p

n·chanl1~l

Source Subsln.u (SS)

+---+~ n-dop<d ,,~on

L _ _ _ _ ~ ~i(u.l conucts

Sou", (5)

(b)

Fig_ 2. 13 Cross section ofNMOSFET with off (a) and on (b) state.

36

Chapter 3

In this chapter. the design of PMOS and NMOS resistive ring mixers is described.

including detailed simulation results. One NMOS and two PMOS mixers were designed

and their layouts were implemented in TSMC O.25~m process. The simulations were

performed using Agilent ADS with BSIM3v3 and for layout work the Virtuoso layout

tool from Cadence was used.

3. CMOS Ring Mixer Design

3.1 Schematic of Mixer

OCP'_

"-"" , ~"'"' "~""'-"~'I' ... ,," ~.-

"00" 'lc~06 , .. ..,,,,,,,, '._.'''1'''''' -"~

Fig.3.l MOSFETschematic without matching network.

This mixer design is based on the basic structure of a resistive FET mixer. The four FET

37

ring mixer presented in Fig.3.1 provides a double balanced solution with high linearity

and good port to port isolation.

NMOS and PMOSFET under analysis for these mixer designs have the following

technological parameters: gate oxide thickness of 57 angstrom, channel length of 0.24

pm, channel width of240 pm and 660pm, threshold voltage 0.48 of NMOS and 0.45

of PMOS. The mobility is 283.1 em'lV. for NMOSFET and 102.9 em'lV. for

PMOSFET.

B.5

5.0

4.5

-

-

-

10

rn~ep(';('?)=20.000 IDiot vs Con Loss Param)=4.60S m3 Indep (';?,3)=SS.OOO IDiot vs Con Loss, Param)=S.648

m3 --~ 'Y- .~-----

------./

... .----.

m2 .---

-"- -Y--I I

20 30

------'.

I 40

ParalTl

I 60

Fig. 3.2 Conversion loss ofNMOSFET mixer

I BO

as a function of device size without matching network.

38

70

7.0

l£I 6.6 3,

a 6.0

6.6

m2 Indep(m2)=20.000 plot vEi{Con Loss Param )=5. 795 m3 Indep(m3)=55.000 plot vs'{Con Loss Param )=6.195

~1\m2 m3 ,0' .----~ y.

,0' .--... ~

/

,,~ .

10

'. --- --I I

20 30

. " -. ---I

40

Param

I 60

Fig. 3.3 Conversion loss ofPMOSFET mixer

I 60

.~

as a function of device size without matching network.

/

70

In order to examine the conversion loss and Flicker noise differences between

NMOSFET and PMOSFET mixers, three double balanced FET ring mixer were designed

as following: each FET having a gate length and width of 0.24 and 240 Ii m for

NMOSFET mixer, a gate length of 0.24 Ii m and width of2401i m for PMOSFET mixer,

and a gate length of 0.24 Ii m and width of 660 Ii m for PMOSFET mixer. The gate

length was chosen equal to the minimum gate length of the TSMC 0.25 ).1m process, The

main differences between NMOSFET and PMOSFET devices lead to different matching

circuits and to a slightly different layout.

The first point during the optimization process of mixer design was the

determination of the FET size with respect to RF matching and conversion loss. It has

been found that both requirements can be fulfilled by a FET size whose impedance at the

RF port matches with the real part of the normalized impedance and was used for the

39

detennination of the matching elements. The MOS device size used for this circuit was

chosen to yield the lowest conversion loss.

Without matching network at RF, LO and IF pons, the RF and LO signal with power

of -40 and 13 dBm, respectively have been applied to the resistive FET mixer. Figo3.2

and Fig. 3.3 illustrate the conversion loss for NMOS and PMOS device size at mixer

design. In Figo3.2, the NMOS device size at the mixer without matching network

indicated the minimum value of conversion loss with device size of 240 Ji m whose value

is 4.6 dB and in Fig. 303, the PMOS device size pointed to the minimum conversion loss

with device size of 348 Ji m whose value is 5.65 dB. Even though the device size of

348 Ji m has minimum conversion loss at double balanced PMOSFET mixer, to compare

the magnitude of Flicker noise between NMOS and PMOS devices, we choose same

device size which is 240 Ji m and scaled for difference in mobility with NMOS resulting

in 660 Ji m. PMOSFET must be wider to provide similar drain current as compared to

NMOSFET. Typically the mobility of holes (Jip ) is 2 time or 3 times lower than the

mobility of electrons (Jin ). After the device size for minimum conversion loss has been

detennined, the matching networks have been added.

40

.,',... _. -,~-._-­'ooQorJ' qfo;ou;/l "I'l __ D'U'I

~~~PI'"

-'-' lolJ)e ... ...... 'l ....... ~ ."";(.,,,-~ ptJT'~-'II)'a:I

PIll~""1a:I

~. _. :.\1)0. ... .. _p'lltl '--

" ,­.­:,,"'0-~---+--I----+-----.~ L._--"'-liii;;::l,-b "[' .;,~

~~~~II''''''''~' T_'_ ,_: ,USBo'. r_IIIOII» ':1..&, ....

Fig. 3.4 NMOSFET 240 schematic with matching network.

The matching networks of the NMOSFET with width of 240 pm in Fig.3.2 have

been designed with input frequency bandwidth of I to 3 GHz with a few passive elements.

The RF and LO ports matching can be achieved using a single shunt inductance and a

shunt resistance. This shunt resistor value of RF and LO ports was chosen to minimize

RF power and LO power dissipation. RF and LO port impedances matched son and IF

port match to 50 n which match requirement removes the need to integrate large value

IF matching components on-chip [7]. Also, IF ports include 10 pF capacitor to achieve

better isolation between port and port. When joining the matching network for each port,

to maintain circuit symmetry is important. If an asymmetry is introduced, the 180 degree

out-off phase balance is destroyed, and the LO to RF leakage degrades.

41

In Fig. 3.3 and 3.4, the PMOSFET mixer design with width of240pm and 660pm

have been designed with RF bandwidth of I to 3 GHz, RF power of -40 dBm and LO

power of 13 dBm as NMOS mixer. IF frequency was fixed at 30 MHz.

-,,", _. -£>111"_ p......-.IlI'~(J

,-~

-, -, 1.~""" -jJtfto(!',~Q '--

-. ,-, .0'))00-~;~-~,q '--

__= _____ ..... 0"

Fig. 3.5 PMOSFET 240 schematic with matching network.

42

~ .. ~,' -, ,~~

~JIII"" ... -

_. -, l·Slo.o "~'.1.O1" --

-""'\ItI$3I$. _______ "" __

1..,'_

~..---..... . .4_--'" '-'---" '-~

~ .. • ""'I>i~~, ""'--------' '-'1"--""--> --- ,­-. -* -,

~ -'_<QoU'I,

'PI'""

Fig. 3.6 PMOSFET 660 schematic with matching network.

3.2 Mixer Performance

3.2.1 Return Loss

The figures 3.7 to 3.9 show the S-parameter and return loss simulation results ofRF,

LO and IF ports of three FET resistive mixers without matching network in bandwidth of

I to 3 GHz, RF power of -40 dBm and LO power of 13 dBm, respectively. Without

matching network, RF and LO ports of three FET resistive mixers do not have broadband

return loss in RF frequency range of I to 3 GHz. But the IF ports of these three mixer

show the excellent return loss below -15 dB with broad-bandwidth. IF port match to 50

Ohm which means that no matching network at IF port is needed on chip. The load

impedance of the RF port of three resistive mixers is located inside the conductance unity

43

(I + jb) circle and the load impedance ofLO port is located outside the resistance unity (I

+ jx) circle and conductance unity circle.

I f---------I'-' -". &

9,f-------,

ml

~~.~~~~ ~9.845 I dana. 34.341.38."

.~,

! ! ! i B i ! i ! ~ i I a ! ~ ! ! i ! i q",<,-: RFI'o~

m ~q-l.0nIlEIiI ::racJl=ez .:!B(RhO IF OctIneom 12.:U ml7 1~~3~~~508 1~.l.OIlIlE9

dB(Rho IF Co""con"I .. I2.'B

Figure 3.7 The simulated return loss ofNMOSFET 240 at RF, IF, and LO port, without matching network ,respectively.

44

•

" ffi ,. I;:: "J RFtreq-l.DOOIl9 Rho AF-04051.112,~~3

- .282&4 -J25.27

• • ~

! ! e ! ! ! ! i ! i

I, " ~

m" :O~2~~n'PtJ.oa4/.,.e13 1m 9lI0II- 58.848· .2111

m ,

~ i!!!ii~i!i~ R~f,*~

9, ~

.. , , • • •

Figure 3.8 The simulated return loss of PMOSFET 240 at RF, IF, and LO port, without matching network, respectively.

45

~

~

~

Ir" e>,. """.",, "''''''"I RFh 2.0otlE9 IRhoJ;aO.6741.131.9M 111!I1I8d:aru:oo.'1.S6&.21.283

mtO

i i & iii i ! iii

! ~

i

" , . .. 7

m18

j i i ; iii iii

9 a'

Fig. 3.9 The simulated return loss ofPMOSFET 660 at RF, IF, and LO port, without matching network, respectively.

Fig. 3.10 to 3.12 show the S-parameter and return loss simulation results ofRF, LO

and IF ports of three FET resistive mixers with matching network in bandwidth of 1.0 to

3.0 GHz, RF power of -40 dBm and LO power of 13 dBm, respectively. After adding the

optimized matching network into each port of three resistive mixers, the return loss ofRF

and LO ports was achieved lower than -10 dB in the frequency range of 1.0 to 3.0 GHz,

which demonstrates the broadband performance of the designed matching networks for

these three mixers.

46

~ f----~--~j

~ '1J;1X11;lr>31;tOO,

"" ~!~J~.'"1m !IP .3:8&19. 1m

. " "

.' ., /

---• • ------" a

i i I I I S i i i i

,~ :. ... , ....

! ~. i :t..-"-"""'-""'T"r"-""-',.-J iiiiil

Pf'"

.,.

'.

Fig. 3.10 The simulated return loss ofNMOSFET 240 at RF, IF, and LO port, with matching network, respectively

47

~' f-----'I''-----

m" =';~~~1~ ·12.1&8 1m edance It 51.588 . 8.592

ml7

9,f--_~-­I

\ / \ . ..1

.---m 3

iii iii iii i i i i ! iii iii ! !

Fig. 3.11 The simulated return loss of PMOSFET 240 at RF, IF, and LO port, with matching network, respectively

48

l' 1--~---;:iiiJ'--~~- t. f-----I>---"

if------IIIJ.--

m" RFfntq"1 .OOOSl dB 0 12.685 .n RFfntqa3.00BE9 dB ",

!

" ,0 ~

"

RFrr.cro2.000Ee I'!'" .J 1~_L()atl.nl3' 176.719 limpsdana" 38.0n. 06(1

Fig. 3.12 The simulated return loss of PMOSFET 660 at RF, IF, and La port, with matching network, respectively

3.2.2 Conversion Loss

~ > c 0

U , ~ 8

m 5 R F fr e q ::z 1 . a 0 D E 8 Down ConvGain=5.982 m 5 ORvers on , 0

, , , 6

• 4

, .2 6

, 0 ~ :: .. 0 0

~ ., ~ " io

0 0 0 0 0

" " 0 0 0 8 " " "

6 Ffreq=1.900E9 own ConvGaln==6.117

-!

N N

~ t: ~ " .. 0 0 !l 0 0 8 0

" " " " R F rre q

Fig. 3.13 The simulated conversion loss ofNMOSFET 240 as a function ofRF frequency for La power of 13 dBm.

49

Fig. 3.13 shows the conversion loss ofNMOSFET 240 versus RF frequency in range

I GHz to 3 GHz and IF frequency of 30 MHz, RF power of -40 dBm, LO power of 13

dBm. The conversion loss saturates at RF frequency of 1.9 GHz at 5.1 dB.

Fig 3.14 and 3.15 show the simulated results of conversion as a function of RF

sweep at IF frequency fIXed of 30MHz at PMOSFET 240 mixer and PMOSFET 660

mixer, respectively. A conversion loss of about 7.7 dB and 7.4 dB was achieved at the

optimum frequency.

~ 0

8, ~ c

mS R F fro q = 1 .000 E 9 o own_C onvG 0In=-9.80

2 Ffreq=2.000E9 ow n_C 0 nvG oln =-7 .719

Conversion Gain (dB) -7.5

-B.O

-8.5

-9.0

-9 ,S

-1 0.0 ~ ~ ~ ~

~ ~ i I"

~ ~ § ~ ~ ~ ~ ~ R F fre q

Fig. 3.14 The simulated conversion loss ofPMOSFET 240 as a function ofRF frequency for LO power of 13 dBm.

50

Conversion Gain (~B ) ·7 0

.- .7 .5

IE 1-

> ·s 0 c 0 '-'

i ·S.5

·9.5

'" '" '" '" ., ., .. .. .. ., ., .. .. ., ., ., ., ., ., ., ., ., ., ., ., ., ., ., ., ., ., G'> G'> G'> G'> C> G'> G'> G'> G'>

______________ ~R~F~f~re~q~--------------_. m5 m2 RFfraq01.000E9 RFfreq°1.800E8 Dow" C O"vG 01"0·9.398 0 OW" C O"vG 01"°·7.409

Fig. 3.15 The simulated conversion loss ofPMOSFET 660 as a function ofRF frequency for LO power of 13 dBm.

3.2.3 Input PI dB, HP2 and HP3

P I dB, Input IP3 and Input IP2 were simulated to examine the linearity of these three

mixers.

Fig. 3.16(a) shows the I dB compression point at RF and IF frequency of 2.4 GHz

and 30 MHz at NMOSFET mixer, respectively which is defined as the RF input power

level that causes the conversion loss to increase by 1 dB. API dB input power

compression point of about 8 dBm was achieved.

Fig 3.17 and 3.18 show the simulated results of PI dB compression point at RF and

IF frequency of2.4 GHz and 30 MHz at PMOSFET 240 mixer and PMOSFET 660 mixer

with same configuration of NMOSFET 240, respectively. A PldB input power

compression point of about 9 dBm and 8 dBm was achieved, respectively.

51

1l --'I

8

]LL ~ 0::1

..... Co

m3 -a -a

-10

-12

-14

-16

-18

-40 -30 -20 -10 0 10 20 30

P_RF

(a)

m4 P RF=8.000

1dBllne1=2.539 20~==========~~~==~======~==~

0 -20 -40 -60 -40 -30 -20 -10 o 10 20 30

(b) Fig. 3.16 Input PldB ofNMOSFET 240, RF power: -40dBm,

LO power: 13 dBm, RF frequency: 2.4 GHz, IF frequency: 30 MHz.

52

m6 m7 Indep(~~)=-40.000 plot vs Con Loss. P RF)=-7.725

Indep(m7)=9.000 plot vs'CCon Loss. P RF):- 9.005

-6.\ r m7 -8--~

-10-

~I ·12-"

S ·14- '.

·16-

·1B-

·20 I I I I I I

-40 -30 ·20 ·10 0 10 20 30

P_RF

(a)

mS m8 P RF=S.OOO indep(m8}=S.OOO

--+,p:...1:..;d:.:B:.:I;.;.;in.;.;e:;..=_1.:.;.,-=2:.:.7-=5"-",P""lo""t~VS~(P,"",,,,",,1F .... ..;P~R;",;;.;.F~}_= ... -O;;;.;.;.;;;O,=O=5 20-

0

.~ LL lB -I ·20 0.0.

-40

·ao -40 ·30 ·20 ·10 o 10 20 30

• (b) Fig. 3.\ 7 Input PldB ofPMOSFET 240,

RF power: -40dBm, LO power: 13 dBm, RF frequency: 2.4 GHz, IF frequency: 30 MH>.

S3

m2 Indep(!';I,2)=-40.000 Iplot vs\Con Loss, P

·10

~ -12

I -14

c§ -16

·18

m3 indep(m3)=8.000

RF)=-8.40~ IDiot wecon Loss, P

... 0 -30 -20 ·10 o 10 20 30

(a)

m4 m5

RFl=-9.58~

P RF=8.000 Indep(m5)=8.000 1dBllne=-0.40 lot Vs P IF, P RF =-1.582

20~~~~=-~~~~~~~~~~~~~~~

0

.~ LL III -I -20 rll. Co

.... 0

-60 -40 -30 ·20 -10 o 10 20 30

(b) Fig. 3.18 Input P I dB of PMOSFET 660,

RF power: -40dBm, LO power: 13 dBm, RF frequency: 2.4 GHz, IF frequency: 30 MHz.

54

m1 freq=30.00MHz dBmlvout)=-45.475

o

-100 ...: i -200 -

-300 -

-400

29.995 29.999

m2 freq=30.00MHz dBm(vout)=-116.997

~ r fl1~

, 30.003 30.005

freq. MHz

1IP3

9 715! -180 aoo I IIP2

66.426 I 180.000

Fig. 3.19 IIP2 and IIP3 ofNMOSFET 240, RF power: -40dBm, LO power: 13 dBm, Input frequency: 2.4 GHz.

Fig. 3.17 shows the third order inter-modulation behavior. Two RF tones with 2

KHz spacing are applied at the input of the mixer with equal power levels to perform

input third order intercept point and input second order intercept point. All other

parameters are as given in fig 3.20. An input third order intercept point (IIP3) of more

than 7 dBm for NMOSFET 240 was achieved with LO power of 13 dBm.

55

1:1

111:2

freq=30.00MHz freq=30.00MHz dBm(vout)=-49.801 dBmCvoutl=-123.079

o : 'WI ~

!

~

~f

-50 i _100

-150 ~

-

-200 29.995 29.999 30.003 30.005

freq. MHz

IIP3

13181 1_180000

IIP2

69.402/180.000

Fig. 3.20 IIP2 and IIP3 ofPMOSFET 240, RF power: -40dBm, LO power: 13 dBm, Input frequency: 2.4 GHz.

m1 freq=30.00MHz dBm(vout)=-49.128

o :

,..: -100

i -200 '-: :

,..: -300

: -400

29.998

~1 .~ ...

29.999

m2 freq=30.00MHz dBm(vout)=-79.166

30.003 30.005

freq, MHz

IIP3

15863 {180 OQO I 1IP2

30.872/180.000

Fig. 3.21 IIP2 and IIP3 of PMOSFET 660, RF power: -40dBm, LO power: 13 dBm, Input frequency: 2.4 GHz.

56

3.2.4 Flicker(J /f) Noise

Fig. 3.22 to 3.24 show the flicke r noise simulated in the frequency band of3 to 100

Hz. These simulations show that usi ng NMOS transistors for the mi xer design lead to

more I I f noise than when PM OS dev ices are used.

m 1 in dep(m 1 )=3 .000

2' .'25

~ · 130 g

d B m (plot vs(Vif.nois e . noisefreq»=·133 855

3i g

' -. , 35 -

'-. , 4 0

-~ ·14 5

-=:1 · 1 50 ' -

% E

. , 55

·' 60

-

f. 1 ....

'" "0 o

- - -

, 00

indep(dBm (plot_vs(Vlf noise . noisefreq)))

Fig. 3.22 Ilf noise ofNMOSFET 240, RF power: ·40d Bm, LO power: 13 dB m, Input frequency: 2.4 GHz.

I~~ep(m 1 )=3 .000 - IdBm(Plot v s(Vif.no ise , no isefre q » =-141 .640

.1_ · 130

g " 40 - ~ .i -'50 -

5 ·'60 -";;>

~l - 170-C.

"'~

E · '80 -+---r--~--'---~--~--r-~.--'---'--~ '" "0 0 '0 0

In dep(d8m ( pl ot_ v s(VIf.nolse . noisefreq»)

Fig. 3.23 I/fnoise of PMOS FET 240, Input RF power : -40 dBm , LO power: 13 dBm, Input frequency: 2.4 GJ-Iz.

57

" "

10

• o

1m2 lin dep(m2)=3 .000 IdBm(plot vs(Vif.no ise , nOisefreq )) =- 156 .717 f -145 --

~ ·150 -

; -155 - V o \ i - 160 - "

on -165 " ;1 '. 0. -170- ---- ---E . 175 ~--.---.-_.--.---.--.---.---.-~=-~

"' '0 o 100

tnd e p (d 8 m (p 101_ vs (V rLn 0 Ise n orsefreq))

Fig. 3.24 Iff noise of PMOSFET 660, RF power : -40 dBm, LO power: 13 dBm, Input frequency: 2.4 GH z.

3.2.5 Por-t-to-Port Isolation

-~ ---..

~

J-

112 1 4 181/12222 4 26 28 3

RF Fr.qulney (GHz)

(a)

~NMOS2~O

~PMOS2"O

PW'O ....

I "' r-- --.

"

.. '" "-< ~

1 ~ ~

2 9 20

10

0

~

u'l • ; '-1

1 1214 1618 2 2.22 4 26283

RF FrequeneYIGHz)

(b)

Fig. 3.25 Simu lated LO - RF (a) and LO - IF (b) port iso lation

at RF frequency 2.4 GHz.

58

I ~N"052'" ____ PMOS2AO

PMClSOlO

I

From th e simulated LO to RF and LO to IF isolations with NMOS 240, PM OS 240

and PMOS 660 mi xers. At NMOS 240 mixer. very high val ues of more than 54 dB in LO

to IF iso lati on have been achieved at RF freque ncy of 2.4 GHz. Compared to the LO to

RF iso lation inc reased va lues of at least 19 dB can be observed .

3.3 Mixer Layout

The ch ip layo ut of the each mi xe r is shown in Fig. 3.26 to 3.28. The chip size of

these mixers was des igned with same size of 1.22 mm x 0.83mm for convenience of

measurement after fabricatio n. The chip was submitted fo r fabrication in standa rd 0.25

Jim CMOS TSM C process. This CMOS process has 5 metal layers and I po ly layer and

uses deep n-well , thi ck top metal for inductor. The NMOS gate is fabricated on a p-type

substrate. The dra in and source are both n-p lus doped regions, with the gate being

composed of poly-silicon. The gate of NMOS and PMOS transistors is made of a

N-doped po lysi li con. The result is that the threshold voltages of NMOS and PMOS are

not symmetri c. The threshold vo ltage of MOS and PMOS is 0.48 Y and -0.45 Y,

respectively. One of PMOSFET mixer in these layouts uses device width about 2.5 times

bigge r than the NMOSFET, in order to keep the trans-conductance more or less equal.

Also, in order to prevent latch-up, the source of both NMOS and PMOSFET are

connected to their respect ive substrate reg ions. The hi gh sheet res istance of the

poly-silicon layer in the MOS transistors could degrade mi xer conversion loss, the

parasitic series resistance within the device was considered to minimize in the layout [8] .

The NMOS tra nsistors in this mi xer have the total dev ice gate width of 240 ~m

wh ich is arra nged to minimize the gate series resistances by separati ng into 20 mu lt iple

59

fingers that each one has a size of 12 fun. Also, terminal to terminal and substrate to

terminal parasitic capac itance have to be taken into account. The PM OS devices in

FigJ.24 have the same confi gu rations as NMOS ones. The PMOS devices in Fig.3.25

have the gate width of bigger size than NMOS devices, whic h have tota l gate width of

660 fll11 with separated 55 multip le fingers .

Planar spiral in ducto rs are probably th e most common ly used and discussed in

layout process. Low quality fac tor CQ) of these ind uctors can signifi cantly degrade circuit

performance in mixer. For layout of this process, fi ve meta l levels are available with 2

Jim thick top level metal for improved inductor Q value in this process. Planar spiral

inductor Q va lue for inductance of 1- 6 nl-l are arou nd 6 in RF frequency ba ndw id th .

Measured inductance and Q values for Inl-l , 3n 1-l and 6n 1-l inductors are shown in

Fig.3.22 .

35

30

25

9 20

a;i

1 5

1 0

5

o

a uallty Facto r

r-----.... / '" I ~

A I "" --/-......... '\I.. ;::::::;--' , , "'-- ~

2 3 4 5 6 7 8 9 10 1 1

Frequency (G H z)

Fig. 3.26 Measured inductance and Q va lu es fo r I nl-l ,3n l-l and 6 nl-l planar spiral inductors.

60

.----- ... -~ ... ...... -- "" ...

Fig. 3.27 Layout ofNMOSFET240 mixer, Chip size is 1.22 111m x O.83mm.

Figure 3.28 Layollt of PMOSFET 240 mixer, Chip size is 1.22 111m x O.83mm.

61

Fig. 3.29 Layout of PMOSFET 660 mi xe r at level 0 in Cadence Virtlloso, Chip size is 1.22 111m x O.83mm.

62

Chapter 4

4. Measurement Results

The ch ip was submitted for fabri cat ion in standard 0.25 !1m CMOS TSMC process.

Allan wafer measurements were carr ied out with an L.O power of 13 dBm and ~F power

of -40 dBm witho ut gate bias . The I F frequency was set to 30 M Hz in all measurements.

4.1 How to Measure

The mixers were character ized using a probe stat ion with differential probes of

SGSGS on ~F and on L.O ports, and at IF port, one IF port was terminated with 50 and

the other port was connected to spectrum analyzer or network ana lyzer. For adaptation of

the ba lanced structure to the single ended RF and L.O signal sources two 180 degree

hybrids have been used while testing the chip.

WinCal and HP 8510 vector network ana lyze r will be used to extract for th e

scallering pa rameters of the three CMOS resistive passive mi xers . Also , for FET resistive

mi xer, one spectrum analyzer for I F pori and two signal generator for RF port and L.O

port are used to measure the conversion loss versus frequency and the P I dB compression

poi nt. To measure the Inpu t Th ird Ord er Intercept Point (lIP3) and the Input Second

Order Intercept Point (111'2) in two tones test, one spectrum analyzer for IF port and two

signal generator fo r ~F port and one signal generator for L.O port are used. When

measuring LO-RF or LO-I F isolation, requiring 50n termination at un used ports, son

63

termination is connected to the IF port or RF port and the power at the RF port and IF

port is measured to obtai n the iso lat ion performance with pumped LO power of 13 dBm .

Mixer

II~ I-~~ I RF signal generator I

J~:I[J I Spectrum Analyzer

180 Balun

D I LO signal generator I

Fig. 4.1 Mixer measurement system.

4.2 Summary of MeaslIrements

4.2.1 Retu rn Loss

The measured return loss as a function of RF for each mixer looki ng at RF, LO and

IF ports are shown in Fig. 4. 1 to 4.6. As can be not iced from th e fig ures in 4. I(a) to 4.2(b),

a return loss better than -10 dB over the RF bandwidth of I GHz to 6 GHz and over th e

LO frequency bandwidth of 1.5 GHz to 4.8 GHz, respecti ve ly has been achieved for the

NMOS 240 mi xer, which demonstrates the broadband performance of the designed

match in g networks. The match at the output port is also better than - 10 dB from de up to

100M Hz in fi gure 4.2(a). In Figure 4.2(b), increased LO power up to 20 dBm resulted in

64

even better IF return loss value of -25 dB and wider frequency mnge from DC to 100

MHz.

.to -

."

.,

(a)

. m1

" o t II 3 . , , 7 8 9 10

(b)

Fig. 4.2 Measured return loss at RF and LO port ofNMOSFET 240 as a function of RF frequency.

65

m3 freq=30.00MHz S(l.l .223/·27.999 1m ce I: 72.491 • '16.011

m2 freq"'30.QOMHZ 5(1.1 aO.057 1-60.090 1m nce=S2.641-S.178

g~--------~y~---- ~f----------'''I-----

."

."

_14 ~-'

.111-

/ fraq (0 OOOOHz 10 100 OMHc:) freQ iO.OOCOHi. to 100 OMHz)

I • -or

" " fre~ MHz

m2 freqo3O.00MHz .B(S(1.1))~13.015

." .,.

" .. " freq MHz m3 ----l heq'30.00MHz , dB(~J1. ~))""24·~i

(a) (b) Fig. 4.3 Measured return loss at IF port ofNMOSFET 240

as a function of RF frequency.

.. , ..

The Figures 4.3 and 4.4 show the measured return loss better than -10 dB over the

RF bandwidth of 1 GHz to 6 GHz and over the LO frequency bandwidth of 1.2 GHz to

4.2 GHz, and RF bandwidth of 1.2 GHz to 3.2 GHz and over the LO frequency

bandwidth of 1.0 GHz to 3.0 GHz, respectively has been achieved for the PMOS 240 and

the PMOS 660 mixer. The measured return loss at the IF port is shown in figure 4.4 (a)

and 4.6(a). For the frequency range of DC to 40 MHz a conversion loss of below -6 dB

was measured with LO power of 13 dBm. The figure 4.4(b) and 4.6(b) show that return

loss of IF port with below -15 dB and -20 dB in the frequency range of DC to 40 MHz,

respectively when LO power of 20 dBm are pumped.

66

•

• • .. ,

iii ." i! ."

."

."

fr 900.0MHz to 10 OOGHz

, • ~-'~~'T'~~,'~~j ~~

23618810

freq, GHz ml freqa 2,900GHz dBeSel,I»0-17.287

(a)

'",; \. "

1req. GHz ml rreq02.500GHz dBeSel,I)I"-14.618

(b)

Fig, 4.4 Measured return loss at RF and LO port ofPMOSFET 240 as a function of RF frequency,

67

~ Ii; <Ii

~ ~--------~~------ ~ ~--------~~---------

."

."

."

."

...

. "

freq to,OOQOKl tD 100 OMHz) freq (0 OOOOHz to 100.0MHzl

"

_1'_ ..,

~ ...

~2 Ii; .., m ~ ...

.., -.---, " -,- -. I •• I I .. m .. '" " "

~eq. MHz - .,

(a) (b) Fig. 4.5 Measured return loss at IF port of PMOSFET 240

as a function of RF frequency.

68

-,

I

',-- ./ .-------.~.

traq (1'I00_0MHz to 10 QOGHz)

-~-- .

o 1 2 3 4 ~ 8 1 8 9 10

1(eq, GHz

m1 froq=2.200GHz dB(S(1.1))~17.3.2

(a)

?: .10-

ii .1e

~..,

Iraq (9OQ,OMHz 10 1000GHz] ---~

-- .,

\.

... ~~-rrr~~~~~T--rrr~ 012345618910

(b)

Fig. 4.6 Measured return loss at RF (a) and LO port (b)ofPMOSFET 660 as a function of RF frequency

69

~.

~ .. ~

~.

i ~,

~,

.1.0_

. "

m2 frecp30.00MHz S(1.1)OO.456 1·16.040 I!,"pedance= 119.405 - J37.943

~

•

freq (0 OOOOHz to 100 OMHZ)

" .. m3 freq c 30.00MHz dB(S(1.1))"-6.828

(a)

~

i

" , ..

~ m2 f-------1~---

. ..

.18_

.18-

... ·22

-24- . ,

."

freq (0 OOOOHz to HlO.OMHzJ

" " frea MHz

m3 freq--30.0OMHz dB(S(1.1))~19.788

(b)

"

Fig. 4.7 Measured return loss at IF port ofPMOSFET 660 as a function of RF frequency.

70

.. ,

4.2.2 Conversion Loss

Co n _ L o s s o f NM OSFET

60

50- f--5-0c-2 44.8

j 4-0-'-3 8-: 8

• 0

30 l 29 ~2 - • 0 . 2 0 . 45 0 . 6

-20

10 • 1l.J. 8 -..- ,Ii

- 5 0 5 1 0 1 5 20 LO Powe r(dB m )

Fig. 4.8 Measured convers ion loss versu ava ilable LO power of NMOSFET 240,

RF power -40 dBm, gate bias voltage = 0, 0.2, 0.45, 0.6 V,

RIO frequency = 2.4 GHz, LO frequency = 2.37 GHz, IF frequency = 30 MHz.

Fig 4.7 demonstrated the relat ionship between conversion loss and LO power as a

function of gate bias vo ltages when RF power is fixed at -40 dBIll. As can be seen frolll

the figure , by app lying a small gate bias vo ltage, the increased gate bias voltages by 0.6 V

(slightly hi gher than the threshold voltage of this transistor) can be achieved the better

conversion loss for low level LO power.

A measured conversion loss of 63 dB and 10. 1 dB is achieved for a 2.4 GHz input

signal to the out put using 0 dBm and 13 dBm of LO power without gate bias, respectively.

It can be seen clearly that much lower conversion loss is poss ib le if higher LO drive are

pumped. Conversion loss va lues down to 10 dB are poss ible. The difference between the

71

measured and simulated conversion loss results rrom the variation between the rabricated

transistor pa rameters and the model used in simu lation .

J

OJ :s ~ ~

a -" c a

.~

0; > c a

0

1 6

1 4

1 2

1 0

B

6

4

2

o

Con_LOSS o f NMOSFET

r

- "' ------------ --------• ~ ><-

1 2

-2 . 4

F re qu e n cy( G H z)

3 4

~o

0 .2 - )1(- 0.45

- 0 .6

Fig. 4.9 Measured conversion loss versus RF frequency ofNMOSFET 240, available LO power 13 dBm , RF power -40 dB m, I F frequency = 30 MH z,

gate bias voltage = 0, 0.2, 0.45 , 0.6 V.

16

14

12

10

8

6

4

2

0

Con_Loss of NMOSFET

11.462

09.528 • 9 .04 7

r-------==~n- O----===--,."1~-',-

2 2 .4 3 4

RF Frequency iGHz)

-+--- 0

o 0.2 - .. -0 .45

0 .6

Fig , 4, I 0 Simulated conversion loss versus RF rreq uency ofNMOSFET 240, ava ilab le LO power 13 dBm, RF power -40 dBm, IF frequency = 30 MHz,

gate bias voltage = 0, 0.2, 0.45, 0.6 V.

72

The mixer conversion loss plotted as a function of the RF frequency given LO

power 13 dBm, RF power -40 dBm with gate biased voltage from 0 to 6 V, and

downconverted output signal at 30 MHz is shown FigA.8. As can be seen in the fi gure,

the convers ion loss of NOMS 240 have the lowest va lue at the small DC gate biased

vo ltage of 0.6 V, which has a conversion loss of 7.8 dB. Without gate bias, th e

conversion loss increased to 10.1 dB at 2.0 G Hz of input signa l.

1 B

Con_Loss of P M OSFET

35

30 -- ---------25

20

1 5

1 0

5 -o

1 2.4 3 4

F reque n cy(GHz)

Fig. 4. 11 Conversion loss versus RF frequency of PMOS rET 240 and 660, ava il able LO power 13 dBm, RF power -40 dBm, gate bias vo ltage 0 V,

and IF frequency 30 MHz.

The mixer conversion loss of PMOS 240 and PMOS 660 plotted as a fun ction of the

RF in range I GHz to 4 GHz given LO power 13 dBm, R.F power -40 dBm without gate

biased voltage, I F port signal at 30 MHz is shown Fig. 4.9. As can be seen in th e fi gure,

the conversion loss of POMS 240 and PMOS 660 mixer has the lowest va lue of21.8 dB

and 14 .8 at 2.4 GHz of optimum signal , respectively.

Figure 4.10 shows the conversion performance of the PM OS 660 mi xer measured

with RF frequency of 2A GHz, IF fixed at 30M Hz and without gait bias while sweep ing

73

the LO power level from 0 dBm to 20 dBm . Better conversion loss of approx imately 14

dB can be achieved down to 20 dBm LO power.

G Co n _ L oss of PM OS FET

25

J 20

B 1 5 -

1 0

L:~

~ ~ ~ -------.

o 5 1 3 20 LO Powe r( dBrn)

Fig. 4. 12 Conversion loss versus LO power of PMOSFET 660. availab le RF power -40 dBm, gate bias voltage = 0 V,

RF frequency = 2.4 GHz, LO frequency = 2.3 7 GHz, IF frequency = 30 MH z.

4_2.3 Input PIdB, llP2 and lIP3

Fig. 4. 11 show the measured PldB compress ion point for one NMOS mixer and two

PMOS mi xers at RF frequency of 2.4 GHz, IF fixed at 30M Hz, RF power of -40 dBm,

LO power of 13 dBm, respectively. P I dB input power compress ion po int occurs at 7

dBm, 17 dBm and 14 dBm of input power in NMOS 240, PMOS 240 and PMOS 660

mixer, respectively.

74

P1 dB o f eac h mix e r

! -PMOS240 --P M O$6 60 NM OS240 I 0

-40 -20 0 5 10 1 2 13 1 5 20

-5

~ - 10 ~ ~

~I

a - 15 --~ -

~ -2 0

-25 • Input Povve r(dB rn )

Fig. 4. 1] The measurements results oreach mi xer on Pld B.

2fl -f2 fl f2 2f2-fJ

Fig. 4.14 The third ord er inter-modu lation components.

The llP] measurement value of the NMOS and PMOS res isti ve mixers when the

two tones of2 AO I and 2.399 GHz in RF frequency were mi xed with an LO frequency of

2.37 GHz with LO power of 13 dBm and RF power of -40 dBm . Resulting in IF signal at

29.999 and ]0.00 1 MHz and the third order intennodulation at 29.997 and 30.003 MHz.

Table 4. 1 are li sted the calculated and measured llP] results which shows that liP] of

each mixer is 12 dBm in NMOS 240, 7 dBm in PMOS 240, 17.25 dBm in PMOS 660.

Comparing wi th simulation results, the va lue is not much lower from simulation va lues.

75

NMOS 240 PMOS 240 PMOS 660

Ou tput Frequency Power Freq uency Power Freque ncy Power signal [MHz] [dBm] [MHz] [dBm] [MHz] [ dBm ]

FI 29.997870 -34.41 29.997870 - 38.50 29 .997870 - 43.46

2f t - f2 29.995830 - 92.00 29.995830 - 87 .60 29.995830 -85.00

f2 29.999900 - 34.51 29.999900 -38.67 29.999900 - 43.5 1

2RF- 2LO 60.0 -81 .3 60.0 -78.5 60.0 -75.9

RF- IF/2 2340.0 -44. 1 2340.0 -37.7 2340.0 -52.2

(a)

NMOS 240 PMOS 240 PMOS 660

P1dB 7 17 14 [dBm]

IIP3 t2 15 .5 19.2 5 [dBm]

IIP2 45.49 41.33 36.49 [dBm]

(b)

Table 4.1 The measurement resu lts ofP IdB, IIP2 and IIPJ.

4.2.4 Flicker(l /f) Noise

The Fl icker noi se assoc iated with MOS devices is much more severe than that with

bipolar tec hnology. However FET resistive mixers exhibits lower leve ls of t I f noise than

diode or act ive mixers, because of low surface-state density than diode and no gate bias,

lower curre nt now of sw itchi ng stages and the periodic swi tching of the transistor [ 10].

76

The Flicker nO ise has stro ng dependcnce on gate bias and surface-state den ity [II).

Fli cker noise invest igations under sw itc hing conditions we re performed from 3 Hz to 100

Hz of the measurement system. As seen in the measurement, MOSFET mi xe rs have

higher II I' noise than PMOSFET mi xers.

The physical s ize and ON resistance or the mixer, the mean DC offset leve l of the

LO signa l, the parasit ic capaci tance and the LO freq uency are all important in

determining the noise perfo rmance.

Jl' Agli ent 2 0:5 4: 12 Nay 1. 1 996 r Mark e r

File Operation Status, C:'STATE007 .. STA file saved

Fig.4.151 /f noiseofNMOSFET240.

77

)l( Agilcnt 2 1:00:11 May 1. 1996 Mar ker

File Operation Status. A:'SCREN008.GIF file SIIved

Fig. 4.16 l/ f noise of PMOSFET 240.

):' AgJlcnt 2 1:13 2:41 Ma y 1. 1996 Har ker

File Oporatlon Status9 A:\SCREN010.GIF file savod

Fig. 4.17 l/ f noise of PMOSFET 660.

78

4.2.5 Port-to-Port Isolation

L 0° L'J 80'

Mixer

Spectrum Analyzer 1180 Balun 1

D 1 LO signal generator 1

Fig. 4. I 8 Measurement system for LO to RF port iso lation.

II 50 0 TERM

RF port L-____ ...J I 50 0 TER M

Mixer

180 Balun

D LO signal generator

IF port

Spectrum Analyzer

Fig. 4. I 9 Measurement system fo r LO to IF port isolati on.

79

51

50

iii "C

~ 49 0 ." • '0 46

'" u.

'" g 47 0 -'

46

45 0

-58'

. 50.

" '"

;;

" " • 48.5 . NMOS240 • : .PMOS240 j 565

PMOS660 • • 0 58

" '"

45. " ... , 1 2 3

... , 0 , ,

RF Frequency (GHz) RF Frequ~ncy (GHz)

(a) (b)

Fig. 4.20 Measured LO - RF (a) and LO - IF (b) port isolation at RF freq uency 2.4 GHz.

r""'S2" -=

3

Iso lat ion is defined as the attenuation in dB between a signal in put at any port and it s

level measured at any other POlt. In the down-convers ion mixer, the isolati on between LO

and RF ports of th e mixer is im pOitant because LO to RF feedth rough resu lts in LO

signa l leakage through the antenna. Also, large LO and RF feedthrough signals at the IF

output port may saturate the IF output port, and decrease the P.ldB of the mixer [13].

FigA .16 and FigA. I? illustrate how to measure LO to RF and LO to IF iso lation.

When measuring LO to RF iso lation, a 50 ohm termination is connected to the two IF

ports and the one RF port, th e LO power at the RF port is obtain the iso lation

perfo rmance. Also, when measuring iso lation from LO to IF, th e power applied at the LO

port and a 50 ohm termination is connected to the one IF ports and the two RF ports, the

LO power at the IF port is measured the iso lation performance. FigA.I S shows the

measured results of the LO to RF and LO to IF iso lation performance at th e RF of 2.4

80

GHz for each MOSFET mixers with RF power of -40 dBm and LO power of 13 dBm,

respectively. At N MOS 240, PMOS 240 and PMOS 660 mixer, very high iso lation value

of 50.5 dB and 58 dB, 48.5 dB and 56.0,45 .5 dB and 54.76 dB were obtained for both

LO to RF and LO to IF measurement, respecti vely.

Name

RF Port

LO Port

I F Port

Device

Conversion Loss

Pl dB

IIP3

IIP2

LO to RF Isolation

LO to IF Isolation

Using non-ideal element (Inductor)

1.00 - 3.00

0.97 - 2.97

30

Simulated results Measured resul ts

NMOSFET PMOSFET PMOSFET NMOSFET PMOSFET PMOSFET (240[um ] ) (240[um]) (660 [um]) (240 [ um]) (240 [um]) (660[um])

5.1 to 5.9 7.7 to 9.8 7.4 to 9.4 8.1 to 10.9 19.8 12.8 to 24.8 to 28.8

8 9 8 7 17 14

9.71 13.16 15.85 12 15.5 19.25

56.43 69.40 30.87 45.5 41. 3 50.5

35. 1 33.8 30 38.0 40.1 34.4

54.6 53.5 43.9 58.0 56.0 54.76

Tab le 4.2 summarizes the sim ulated and measured results for three MOSFET mixers .

81

Unit

[GHz]

[GHz]

[MHz]

[dB]

[dBm ]

[dBm]

[dBm ]

[dB]

[dB]

Chapter 5

5. Conclusion and Future Work

5.1 Conclusions

This thesis work has presented the performance of three CM OS resistive mixers, one

NMOSFET mixer and two PMOSFET mixers built in 0.25 fI m CMOS TSMC process.

It has demonstrated 10.1 dB minimum conversion loss in NMOSFET of width 240,11 m,

12 dBm 11 P3 ald 7 dBm P1dB , in PMOSFET of width 240 ,11 m conversion loss of 21 .8

dB,? dBm 11P3 ald 17 dBm P1dB, in PMOSFET of width 660 /1 m conversion loss of

14.8 dB, 19.25 dBm 11P3 ald 14 dBm P1dB, when the consuming no DC power,

respectively. The overall performance makes the mixers wel l suited for both, direct

conversion ald heterodyne a-chitectures, offering a wide ralge of ~plicOOility . The

performance highlights are: no DC power consumption, high linearity and port-te-port

isolation, and low 1ff noise.

5.2 Future Wo rk

Conversion loss of these mixers could be improved in all mixers by using different

inductor layout model . The inductor models used in this mixer design have relatively

small center holes that make shift of center frequency to higher frequency , from the

results optimum conversion loss in the range 1 GHz to 3 GHz could not achieved. In

these mixer designs, eight spi ral inductors at NMOS 240 and PMOS 240 ald ten inductor

models at PMOS 660 mixer, respectively were used to implement the matching network

82

which could be male worse conversion loss with ohmic and substrate loss. The spiral

inductor layout coul d be further opti rnized so reduce lI'ea and parasiti c parameters.

83

References

[1) Thomas H. Lee, r1fhe Design of CMOS RcIlio-Frequa1CY Integratoo Circuitsl:) Cambridge

University Press. 1998.

[2) Stephen A. M ass, The RF and Microwave Circuit Design Cookbook, Boston. London:

Artech House, First Edition, 1998.

[3) Bosco Leung, VLSI for wireless Communication, PrentioeHall, First Edition, 2002.

[4) M.T. Tarovitis, and R G. MeyS', !:Noise in Current-Commutating CMOS MixS'SII

IEEE Journal of Solid-State Circuits, vol.34, no.6, pp 772-783, June 1999.

[5) Vinoenl Geffroy, Giuseppe DeAstis, and Eric BS'geault, IRF mixers using standard

digital CMOS 0.35 pm processQ Microwave Symposium Digest. 2001 IEEE MTT-S

I ntS'nati ona , vol 1, pp. ~86, 2001.

[6) Stephen A. Mass, Microwave MixS's, Boston. London: Artech House, Second Edition,

1993.

[7] Penny Gould, ChristophS' Zel I ey, Jenshan Lin, leMOS Resistive Ring MixS' MMICs

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[8) Penny Gould, Jenshan Lin, Boric-Lubecka. 0., ChristophS' Zelley, , LD.25-pm BICMOS

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transaction on Microwavetheory and techniques, vol. 50, NO.1, January 2002.

[9] ZhCiKlfeng Zhang, Jack Lau, lexperimental Study on MOSFETrs RickS' Noise undS'

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