Lecture18 Ee620 FracN Synth

7/29/2019 Lecture18 Ee620 FracN Synth

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Sam Palermo

Analog & Mixed-Signal Center

Texas A&M University

ECEN620: Network Theory

Broadband Circuit DesignFall 2012

Lecture 18: Fractional-N Frequency Synthesizers



Announcements and Agenda

• Exam 2 Friday 11/9

• PLL Bandwidth and Frequency Resolution

Trade-Offs• Fractional-N Frequency Synthesizers

• Modulus Randomization and Noise Shaping

2



PLL Bandwidth Constraints

• PLL loop bandwidth should be <0.1*f ref inorder to maintain loop stability

•Continuous-time model breaks down if loop

bandwidth is too high 3

θout(s)

θref (s)

20log10

ω3dB

=1.47Mrad/s



Issues with Synthesizing Frequenciesat a Tight Channel Spacing

• In a simple integer-N PLL, the output frequencyresolution is equal to the input reference frequency

4

[Perrott]



Issues with Synthesizing Frequenciesat a Tight Channel Spacing

• In integer-N PLLs, synthesizing tight channel spacings requires extremelylow effective reference frequencies

• This results in very low loop bandwidths and high divide ratios

• Slow PLL frequency switching time

• Large area passives

• High phase noise at low frequencies5

[Perrott]



Fractional-N Frequency Synthesizers

• A fractional-N frequency synthesizer allows the

effective division ratio to take on a fractional value• The output frequency can then be at a much

higher resolution than the reference frequency

• Allows a higher loop bandwidth 6



Effective Divide Ratio

7

25.44

17

5

5

4

12

512

1

cycles)VCO(5once5andcycles)VCO(12timesthree4bydivide

4.25,of ratiodivideeffectiveanrealize To :Example

1NbydividedcyclesVCOof numbertheisB

andNbydividedcyclesVCOof numbertheisAwhere

1

:RatioDivideEffective

==

+

+=

++

+=

+

++

+=

N

B

N

A

BAN

N

B

N

A

BAN

eff

eff

3TREF

4

4/5



Dual Modulus Prescalers

8

÷2/3

MC=0→ ÷3MC=1→ ÷2

÷15/16

Synchronous ÷3/4 Asynchronous ÷4

• For /15, first prescaler circuit divides by 3 once and 4 three times

during the 15 cycles

[Razavi]



Phase Error withSimple Periodic Modulus Control

• As only the average of the feedback frequency is equal tothe reference frequency, the phase error will accumulateover N reference cycles before being reset

9

[Perrott]



Fractional-N Frequency Synthesizer Spurs

• Simple periodic modulus control causesa ramp-type phase error accumulationover N reference cycles

• This is translated into periodicdisturbances in the VCO control

voltage, which causes relatively close-in spurs in the frequency domain

10



Spur Suppression with Modulus Randomization

• Instead of periodically changing the dividermodulus, randomly switch it such that the averagedivision factor still yields the desired fractional value

• This converts the systematic fractional spurs intorandom noise

11



Including Noise Shaping in Modulus Control

• This technique can be extended by in

addition to randomization, shaping thenoise in such a way that it can be filteredby the PLL

12



Sigma-Delta Modulation Noise Shaping

• High-pass noise shaping canbe realized by using asigma-delta modulator formodulus control

• The divider quantizationnoise can then be filtered bythe PLL more efficiently

13



Next Time

• Delay-Locked Loops (DLLs)

• Current-Mode Logic Gate Design

• Clock-and-Data Recovery Systems

14

Lecture18 Ee620 FracN Synth

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