Lecture 6- Analog Layout layout and to minimize the resistance of the connection Dr. Mohamed Refky...

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Lecture 6 - Analog Layout Dr. Mohamed Refky Amin Electronics and Electrical Communications Engineering Department (EECE) Cairo University elc.n 112 [email protected] http://scholar.cu.edu.eg/refky/

Transcript of Lecture 6- Analog Layout layout and to minimize the resistance of the connection Dr. Mohamed Refky...

Page 1: Lecture 6- Analog Layout layout and to minimize the resistance of the connection Dr. Mohamed Refky Layout of a Single Transistor Source and Drain Connections. Analog Layout Large contracts

Lecture 6- Analog Layout

Dr. Mohamed Refky Amin

Electronics and Electrical Communications Engineering Department (EECE)

Cairo University

[email protected]

http://scholar.cu.edu.eg/refky/

Page 2: Lecture 6- Analog Layout layout and to minimize the resistance of the connection Dr. Mohamed Refky Layout of a Single Transistor Source and Drain Connections. Analog Layout Large contracts

Outline of this Lecture

• Previously on ELCN321

• Layout of a Single Transistor

• Matching of Transistors

• Layout of Resistors

• Layout of Capacitors

Dr. Mohamed Refky

Page 3: Lecture 6- Analog Layout layout and to minimize the resistance of the connection Dr. Mohamed Refky Layout of a Single Transistor Source and Drain Connections. Analog Layout Large contracts

Previously on ELCN321

Interconnect Parasitic Parameters

Capacitance

Dr. Mohamed Refky

Page 4: Lecture 6- Analog Layout layout and to minimize the resistance of the connection Dr. Mohamed Refky Layout of a Single Transistor Source and Drain Connections. Analog Layout Large contracts

Previously on ELCN321

Dr. Mohamed Refky

Interconnect Parasitic Parameters

Resistance

Page 5: Lecture 6- Analog Layout layout and to minimize the resistance of the connection Dr. Mohamed Refky Layout of a Single Transistor Source and Drain Connections. Analog Layout Large contracts

Previously on ELCN321

Dr. Mohamed Refky

Electrical Wire Models

Page 6: Lecture 6- Analog Layout layout and to minimize the resistance of the connection Dr. Mohamed Refky Layout of a Single Transistor Source and Drain Connections. Analog Layout Large contracts

Previously on ELCN321

Dr. Mohamed Refky

Elmore delay formula

Page 7: Lecture 6- Analog Layout layout and to minimize the resistance of the connection Dr. Mohamed Refky Layout of a Single Transistor Source and Drain Connections. Analog Layout Large contracts

Analog Layout

Dr. Mohamed Refky

Layout of a Single Transistor

Page 8: Lecture 6- Analog Layout layout and to minimize the resistance of the connection Dr. Mohamed Refky Layout of a Single Transistor Source and Drain Connections. Analog Layout Large contracts

Analog Layout

Dr. Mohamed Refky

Layout of a Single Transistor

Source and Drain Connections

Page 9: Lecture 6- Analog Layout layout and to minimize the resistance of the connection Dr. Mohamed Refky Layout of a Single Transistor Source and Drain Connections. Analog Layout Large contracts

Analog Layout

Single contact must be avoided to improve the reliability of the

layout and to minimize the resistance of the connection

Dr. Mohamed Refky

Layout of a Single Transistor

Source and Drain Connections

Page 10: Lecture 6- Analog Layout layout and to minimize the resistance of the connection Dr. Mohamed Refky Layout of a Single Transistor Source and Drain Connections. Analog Layout Large contracts

Analog Layout

Large contracts must be avoided because it may cause micro-

fractures and electromigration. This this causes reliability

problems

Dr. Mohamed Refky

Layout of a Single Transistor

Source and Drain Connections

Page 11: Lecture 6- Analog Layout layout and to minimize the resistance of the connection Dr. Mohamed Refky Layout of a Single Transistor Source and Drain Connections. Analog Layout Large contracts

Analog Layout

A single tie can be used every 2 transistors or more.

Double ties on both sides of a MOSFET can also be used.

Dr. Mohamed Refky

Layout of a Single Transistor

Substrate and Well Ties

Page 12: Lecture 6- Analog Layout layout and to minimize the resistance of the connection Dr. Mohamed Refky Layout of a Single Transistor Source and Drain Connections. Analog Layout Large contracts

Analog Layout

Dr. Mohamed Refky

Layout of a Single Transistor

Page 13: Lecture 6- Analog Layout layout and to minimize the resistance of the connection Dr. Mohamed Refky Layout of a Single Transistor Source and Drain Connections. Analog Layout Large contracts

Analog Layout

Dr. Mohamed Refky

Layout of a Single Transistor

Multiple Fingers Single Transistor

2

fingers

3

fingers

Page 14: Lecture 6- Analog Layout layout and to minimize the resistance of the connection Dr. Mohamed Refky Layout of a Single Transistor Source and Drain Connections. Analog Layout Large contracts

Analog Layout

Dr. Mohamed Refky

Example (1)

one finger 5 finger 8 finger

Page 15: Lecture 6- Analog Layout layout and to minimize the resistance of the connection Dr. Mohamed Refky Layout of a Single Transistor Source and Drain Connections. Analog Layout Large contracts

Analog Layout

Dr. Mohamed Refky

Example (1)

one finger 5 finger 8 finger

Page 16: Lecture 6- Analog Layout layout and to minimize the resistance of the connection Dr. Mohamed Refky Layout of a Single Transistor Source and Drain Connections. Analog Layout Large contracts

Analog Layout

Dr. Mohamed Refky

Example (1)

one finger 5 finger 8 finger

Page 17: Lecture 6- Analog Layout layout and to minimize the resistance of the connection Dr. Mohamed Refky Layout of a Single Transistor Source and Drain Connections. Analog Layout Large contracts

Analog Layout

Many analog circuits require high matching between the building

transistors

Dr. Mohamed Refky

Matching of Transistors

Process variations result in

mismatch between transistors

Mismatch Errors

Systematic

Errors

Random

Errors

Page 18: Lecture 6- Analog Layout layout and to minimize the resistance of the connection Dr. Mohamed Refky Layout of a Single Transistor Source and Drain Connections. Analog Layout Large contracts

Analog Layout

Small nearby devices are

dominated by random errors

Large nearby devices are

dominated by systematic

errors (process gradient)

Random errors are difficult to

mitigate.

Systematic errors can be

mitigated by layout techniques

Dr. Mohamed Refky

Matching of Transistors

Page 19: Lecture 6- Analog Layout layout and to minimize the resistance of the connection Dr. Mohamed Refky Layout of a Single Transistor Source and Drain Connections. Analog Layout Large contracts

Introduction

To match two transistors, parallel elements must be used becausesilicon is un-isotropic

The current should flow in the same direction in the twotransistors

Dr. Mohamed Refky

Matching of Transistors

Matching of One Finger Transistors

Page 20: Lecture 6- Analog Layout layout and to minimize the resistance of the connection Dr. Mohamed Refky Layout of a Single Transistor Source and Drain Connections. Analog Layout Large contracts

Introduction

Dr. Mohamed Refky

Matching of Transistors

Matching of One Finger Transistors

Page 21: Lecture 6- Analog Layout layout and to minimize the resistance of the connection Dr. Mohamed Refky Layout of a Single Transistor Source and Drain Connections. Analog Layout Large contracts

Introduction

Interdigitation is 1-dimension technique to overcome the

systematic mismatch due to process gradient

Common axis provide higher degree of matching

Dr. Mohamed Refky

Matching of Transistors

Matching of Multi-Fingers Transistors

Page 22: Lecture 6- Analog Layout layout and to minimize the resistance of the connection Dr. Mohamed Refky Layout of a Single Transistor Source and Drain Connections. Analog Layout Large contracts

Analog Layout

In interdigitation technique, the two transistors are spilt in an

equal part of fingers and then the fingers are interdigitated in a

balanced fashion

Dr. Mohamed Refky

Matching of Transistors

Matching of Multi-Fingers Transistors

AABBAABB ABBAABBA

Page 23: Lecture 6- Analog Layout layout and to minimize the resistance of the connection Dr. Mohamed Refky Layout of a Single Transistor Source and Drain Connections. Analog Layout Large contracts

Analog Layout

Common centroid is another technique to overcome the

systematic mismatch due to process gradient

Dr. Mohamed Refky

Matching of Transistors

Matching of Multi-Fingers Transistors

Cross coupling Tiling pattern

Page 24: Lecture 6- Analog Layout layout and to minimize the resistance of the connection Dr. Mohamed Refky Layout of a Single Transistor Source and Drain Connections. Analog Layout Large contracts

Analog Layout

Common-centroid is considered as a 2-dimension technique to

overcome the systematic mismatch

Dr. Mohamed Refky

Matching of Transistors

Matching of Multi-Fingers Transistors

Page 25: Lecture 6- Analog Layout layout and to minimize the resistance of the connection Dr. Mohamed Refky Layout of a Single Transistor Source and Drain Connections. Analog Layout Large contracts

Analog Layout

Sketch the layout of three interdigitated transistors having the

same width. The three transistors have the source in common.

Dr. Mohamed Refky

Assignment

Page 26: Lecture 6- Analog Layout layout and to minimize the resistance of the connection Dr. Mohamed Refky Layout of a Single Transistor Source and Drain Connections. Analog Layout Large contracts

Analog Layout

Ending elements have different boundary conditions than the

inner elements. This affect the matching of the transistors

Dr. Mohamed Refky

Matching of Transistors

Dummy Devices

Page 27: Lecture 6- Analog Layout layout and to minimize the resistance of the connection Dr. Mohamed Refky Layout of a Single Transistor Source and Drain Connections. Analog Layout Large contracts

Analog Layout

To overcome this problem, dummy transistors (one at each end)

are used

Dummies transistors are shorted transistors

Dummies transistors add parasitics to the circuit

Dr. Mohamed Refky

Matching of Transistors

Dummy Devices

Page 28: Lecture 6- Analog Layout layout and to minimize the resistance of the connection Dr. Mohamed Refky Layout of a Single Transistor Source and Drain Connections. Analog Layout Large contracts

Analog Layout

Stacked Layout is a systematic use of stack of transistors

In the same stack, fingers of same width are used to represent the

transistors, possibly different length

Dr. Mohamed Refky

Stacked Layout

Page 29: Lecture 6- Analog Layout layout and to minimize the resistance of the connection Dr. Mohamed Refky Layout of a Single Transistor Source and Drain Connections. Analog Layout Large contracts

Analog Layout

The design steps of the stacked layout are:

1) Examine the size of transistors in the cell

2) Split transistors size in a number of layout oriented fingers

3) Identify the transistors that can be placed on the same stack

4) Possibly change the size of non-critical transistors

5) Use (almost) the same number of finger per stack

6) Place stacks and interconnect

Dr. Mohamed Refky

Stacked Layout

Design procedure

Page 30: Lecture 6- Analog Layout layout and to minimize the resistance of the connection Dr. Mohamed Refky Layout of a Single Transistor Source and Drain Connections. Analog Layout Large contracts

Analog Layout

Use the stacked layout technique to layout the two stages OTA

Dr. Mohamed Refky

Example (3)

Page 31: Lecture 6- Analog Layout layout and to minimize the resistance of the connection Dr. Mohamed Refky Layout of a Single Transistor Source and Drain Connections. Analog Layout Large contracts

Analog Layout

Dr. Mohamed Refky

Example (3)

The width of the second and

third stack is 10

Page 32: Lecture 6- Analog Layout layout and to minimize the resistance of the connection Dr. Mohamed Refky Layout of a Single Transistor Source and Drain Connections. Analog Layout Large contracts

Analog Layout

Dr. Mohamed Refky

Example (3)

Page 33: Lecture 6- Analog Layout layout and to minimize the resistance of the connection Dr. Mohamed Refky Layout of a Single Transistor Source and Drain Connections. Analog Layout Large contracts

Analog Layout

Dr. Mohamed Refky

AssignmentUse the stacked layout technique to layout the two stages OTA

Page 34: Lecture 6- Analog Layout layout and to minimize the resistance of the connection Dr. Mohamed Refky Layout of a Single Transistor Source and Drain Connections. Analog Layout Large contracts

Analog Layout

Dr. Mohamed Refky

Layout of Resistors

Page 35: Lecture 6- Analog Layout layout and to minimize the resistance of the connection Dr. Mohamed Refky Layout of a Single Transistor Source and Drain Connections. Analog Layout Large contracts

Analog Layout

Dr. Mohamed Refky

Layout of Resistors

Diffused resistances have large

resistance

Diffused resistances have a

large voltage and temperature

coefficient

Diffused resistances are weakly

insulated from the surrounding

Diffused Resistances

Page 36: Lecture 6- Analog Layout layout and to minimize the resistance of the connection Dr. Mohamed Refky Layout of a Single Transistor Source and Drain Connections. Analog Layout Large contracts

Analog Layout

Dr. Mohamed Refky

Layout of Resistors

Poly is the most widely used material to implement resistance

Features of Resistors

Type of layerAccuracy

%

30 - 50 20 - 40 200 – 1k 50 - 300

50 - 150 20 - 40 200 – 1k 50 - 300

2k – 4k 15 - 30 5k 10k

3k – 6k 15 - 30 5k 10k

6k – 10k 25 - 40 10k 20k

9k – 13k 25 - 40 10k 20k

First poly 20 - 40 25 - 40 500 - 1500 20 - 200

Second poly 15 - 40 25 - 40 500 - 1500 20 - 200

Page 37: Lecture 6- Analog Layout layout and to minimize the resistance of the connection Dr. Mohamed Refky Layout of a Single Transistor Source and Drain Connections. Analog Layout Large contracts

Analog Layout

Dr. Mohamed Refky

Layout of Resistors

Resistance Calculations

Page 38: Lecture 6- Analog Layout layout and to minimize the resistance of the connection Dr. Mohamed Refky Layout of a Single Transistor Source and Drain Connections. Analog Layout Large contracts

Analog Layout

Dr. Mohamed Refky

Layout of Resistors

Resistance Calculations

Page 39: Lecture 6- Analog Layout layout and to minimize the resistance of the connection Dr. Mohamed Refky Layout of a Single Transistor Source and Drain Connections. Analog Layout Large contracts

Analog Layout

Dr. Mohamed Refky

Layout of Resistors

Absolute accuracy of the resistor is

controlled by the poly line edge-shift

during processing (PR dimensional

change, lateral etching, UV diffraction,

... etc)

As inaccuracy is almost the same in

the two resistors, matching accuracy is

very high

Accuracy of Resistors

Page 40: Lecture 6- Analog Layout layout and to minimize the resistance of the connection Dr. Mohamed Refky Layout of a Single Transistor Source and Drain Connections. Analog Layout Large contracts

Analog Layout

Dr. Mohamed Refky

Layout of Resistors

Accuracy of Resistors

Page 41: Lecture 6- Analog Layout layout and to minimize the resistance of the connection Dr. Mohamed Refky Layout of a Single Transistor Source and Drain Connections. Analog Layout Large contracts

Analog Layout

Dr. Mohamed Refky

Layout of Resistors

Accuracy of Resistors

Etching

Boundary

Side diffusivity

Implant dose

Side diffusivity

Deposition rate

Doping dose

Stress

Temperature

Page 42: Lecture 6- Analog Layout layout and to minimize the resistance of the connection Dr. Mohamed Refky Layout of a Single Transistor Source and Drain Connections. Analog Layout Large contracts

Analog Layout

Dr. Mohamed Refky

Layout of Resistors

Accuracy of Resistors

Page 43: Lecture 6- Analog Layout layout and to minimize the resistance of the connection Dr. Mohamed Refky Layout of a Single Transistor Source and Drain Connections. Analog Layout Large contracts

Analog Layout

Dr. Mohamed Refky

Layout of Resistors

Accuracy of Resistors

Accurate VLSI designs should depend on

resistance ratio rather than on absolute

resistance

Page 44: Lecture 6- Analog Layout layout and to minimize the resistance of the connection Dr. Mohamed Refky Layout of a Single Transistor Source and Drain Connections. Analog Layout Large contracts

Analog Layout

Dr. Mohamed Refky

Layout of Resistors

Temperature gradient on the

chip may produce thermal

induced mismatch.

Thus, nearby heat sources, the

orientation of the resistor can

affect the matching

Accuracy of Resistors

Page 45: Lecture 6- Analog Layout layout and to minimize the resistance of the connection Dr. Mohamed Refky Layout of a Single Transistor Source and Drain Connections. Analog Layout Large contracts

Analog Layout

Dr. Mohamed Refky

Layout of Resistors

Matching between resistances can be improved by using

interdigitation, common centroid, and dummy cell techniques

121212212121

Matching of Resistors

Page 46: Lecture 6- Analog Layout layout and to minimize the resistance of the connection Dr. Mohamed Refky Layout of a Single Transistor Source and Drain Connections. Analog Layout Large contracts

Analog Layout

Dr. Mohamed Refky

Layout of Capacitors

For integrated capacitors, the electrodes are usually made of

metal, polysilicon, or diffusion

The insulator are usually made of silicon oxide, polysilicon

oxide, or CVD oxide

Page 47: Lecture 6- Analog Layout layout and to minimize the resistance of the connection Dr. Mohamed Refky Layout of a Single Transistor Source and Drain Connections. Analog Layout Large contracts

Analog Layout

Dr. Mohamed Refky

Layout of Capacitors

Oxide damage

Impurities

Temperature

Bias condition

Stress

Page 48: Lecture 6- Analog Layout layout and to minimize the resistance of the connection Dr. Mohamed Refky Layout of a Single Transistor Source and Drain Connections. Analog Layout Large contracts

Analog Layout

Dr. Mohamed Refky

Layout of Capacitors

Accuracy of Capacitors

Page 49: Lecture 6- Analog Layout layout and to minimize the resistance of the connection Dr. Mohamed Refky Layout of a Single Transistor Source and Drain Connections. Analog Layout Large contracts

Analog Layout

Dr. Mohamed Refky

Layout of Capacitors

Accuracy of Capacitors

Capacitors with large perimeter

features (like zigzags) suffers from

low accuracy

Page 50: Lecture 6- Analog Layout layout and to minimize the resistance of the connection Dr. Mohamed Refky Layout of a Single Transistor Source and Drain Connections. Analog Layout Large contracts

Analog Layout

Dr. Mohamed Refky

Layout of Capacitors

Accuracy of Capacitors

Type of layerAccuracy

%

poly - diff 15 - 20 7 - 14 20 – 50 60 - 300

poly I - diff II 15 - 25 6 - 12 20 – 50 40 - 200

metal - poly 500 - 700 6 - 12 50 – 100 40 - 200

metal - diff 1200 - 1400 6 - 12 50 – 100 60 - 300

metal I- metal II 800 - 1200 6 - 12 50 – 100 40 - 200

Page 51: Lecture 6- Analog Layout layout and to minimize the resistance of the connection Dr. Mohamed Refky Layout of a Single Transistor Source and Drain Connections. Analog Layout Large contracts

Analog Layout

Dr. Mohamed Refky

Layout of Resistors

To achieve good matching between

capacitors, copies of unit capacitor

are used and are connected in parallel.

The unit capacitor are usually made

of a fairly large square

Matching accuracy of the capacitors

is better than that of the resistors

Matching of Capacitors

Page 52: Lecture 6- Analog Layout layout and to minimize the resistance of the connection Dr. Mohamed Refky Layout of a Single Transistor Source and Drain Connections. Analog Layout Large contracts

Analog Layout

Dr. Mohamed Refky

Layout of Resistors

Matching between capacitors can be

improved by using common centroid,

and dummy cell techniques

Matching of Capacitors


Analog Layout Techniques in VLSI

Analog Layout Techniques in VLSI

High Speed Layout Analog

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