Lecture 24 Given
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Transcript of Lecture 24 Given
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8/13/2019 Lecture 24 Given
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Digital Logic Design 1
EL 114
Digital Logic Design
Instructor:
Dr. Mazad S. Zaveri
Faculty Block 4, Room 4206
Email: [email protected]
http://intranet.daiict.ac.in/~mazad_zaveri/
http://intranet.daiict.ac.in/~mazad_zaveri/http://intranet.daiict.ac.in/~mazad_zaveri/ -
8/13/2019 Lecture 24 Given
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Digital Logic Design 2
ALU Next weeks Lab The ALU consists of several logic/arithmetic blocks
The output of each block is connected (via MUX or similar method) to the final outputvia a MUX MUX based approach is much simpler (select the appropriate path/switch in the MUX)
Other approach, where the MUX (tri-state buffers) are assumed to inside the blocks Instead of a physical MUX, we simulate the behavior using floating or driven states
Required coding style Release or take-control of the output bus
Release (make it float, assign 4bzzzz) So that other blocks can drive the output if required
Take-control (drive the bus, assign some value) Any other block should not (can not) drive at the same time
Example:assign Y = (condition1)? (Y_block1) : (4bzzzz);assign Y = (condition2)? (Y_block2) : (4bzzzz);
assign Y = (condition3)? (Y_block3) : (4bzzzz);
Now depending on the above conditions (two valid cases are possible):
Only one condition can satisfy at any given time That particular blocks value will be assigned to the output
None of the conditions satisfy at any given time The output will float (none of the blocks will drive the output)
More than one conditions satisfy at any given time (Not a Valid Case)
This should never happen in your code
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Digital Logic Design 3
Example: Mealy FSM
Sequence detector Detect a sequence of two consecutive 1s in in the input (w)
Clock cycle: t0
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
w: 0 1 0 1 1 0 1 1 1 0 1
z : 0 0 0 0 1 0 0 1 1 0 0
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Digital Logic Design 4
Mealy FSM State Diagram
A
w 0= z 0=
w 1= z 1=Bw 0= z 0=
Reset
w 1= z 0=
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Mealy FSM State Table
Present Next state Output z
state w = 0 w = 1 w = 0 w = 1
A A B 0 0
B A B 0 1
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8/13/2019 Lecture 24 Given
6/9Digital Logic Design 6
Mealy FSM State Assigned Table
Present Next state Output
statew = 0 w = 1 w = 0 w = 1
y Y Y z z
A 0 0 1 0 0
B 1 0 1 0 1
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8/13/2019 Lecture 24 Given
7/9Digital Logic Design 7
Clock
Resetn
D Q
Q
w
z
(a) Circuit
t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t101
0
10
1
0
10
Clock
y
w
z
y
(b) Timing diagram
Mealy FSM Circuit Diagram
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8/9Digital Logic Design 8
Practice Example Implement a Moore FSM Switch = 2b00
Green LEDs go ON-OFF, and continues
Switch = 2b01
RED LEDs go ON-OFF, and continues Switch = 2b10
Green LEDs go ON-OFF,followed by Red LEDs go ON-OFF, and continues
Switch = 2b11 All LEDs go ON-OFF, and continues
The switch can be changed at anytime When a switch changes, turn the center LED ON-OFF for three times, and then start the new sequence
How many inputs
do we have? (two
binary inputs,
corresponding to
the switch)
How many outputs
do we have?(13 LEDs)
H d
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8/13/2019 Lecture 24 Given
9/9Digital Logic Design 9
Hazards Static Hazards
The value of a signal should ideally remain at 0, but it temporarily (glitches) goes to 1 and comes back to 0
The value of a signal should ideally remain at 1, but it temporarily (glitches) goes to 0 and comes back to 1
Dynamic Hazards The signal should ideally transition from 10
But the signal will transition from 1010 (or more transitions than necessary)
The signal should ideally transition from 01 But the signal will transition from 0101 (or more transitions than necessary)
Hazards are important for sequential circuits, because we do not want glitching behavior to happen at
the inputs of the Flip-Flops (especially during the setup and hold time windows around the active clockedge)
Generally, the outputs of a combinational block (that implements the next-state logic) will act as the inputs to a FF If the combinational blocks output glitches, the FF may capture a wrong value
1 1
0 0
1 0 0 1
(a) Static hazard
(b) Dynamic hazard
1
0
1
0