Introduction toCMOS VLSI

Design

Lecture 18: Design for Low Power

David Harris

Harvey Mudd CollegeSpring 2004

18: Design for Low Power Slide 2CMOS VLSI Design

Outlineq Power and Energyq Dynamic Powerq Static Powerq Low Power Design

18: Design for Low Power Slide 3CMOS VLSI Design

Power and Energyq Power is drawn from a voltage source attached to

the VDD pin(s) of a chip.

q Instantaneous Power:

q Energy:

q Average Power:

( ) ( )DD DDP t i t V=

0 0

( ) ( )T T

DD DDE P t dt i t V dt= =∫ ∫

avg0

1( )

T

DD DD

EP i t V dt

T T= = ∫

18: Design for Low Power Slide 4CMOS VLSI Design

Dynamic Powerq Dynamic power is required to charge and discharge

load capacitances when transistors switch.

q One cycle involves a rising and falling output.q On rising output, charge Q = CVDD is requiredq On falling output, charge is dumped to GNDq This repeats Tfsw times

over an interval of T

Cfsw

iDD(t)

VDD

18: Design for Low Power Slide 5CMOS VLSI Design

Dynamic Power Cont.

Cfsw

iDD(t)

VDD

dynamicP =

18: Design for Low Power Slide 7CMOS VLSI Design

Activity Factorq Suppose the system clock frequency = fq Let fsw = αf, where α = activity factor

– If the signal is a clock, α = 1– If the signal switches once per cycle, α = ½– Dynamic gates:

• Switch either 0 or 2 times per cycle, α = ½– Static gates:

• Depends on design, but typically α = 0.1

q Dynamic power: 2dynamic DDP CV fα=

18: Design for Low Power Slide 8CMOS VLSI Design

Short Circuit Currentq When transistors switch, both nMOS and pMOS

networks may be momentarily ON at onceq Leads to a blip of “short circuit” current.q < 10% of dynamic power if rise/fall times are

comparable for input and output

18: Design for Low Power Slide 9CMOS VLSI Design

Exampleq 200 Mtransistor chip

– 20M logic transistors• Average width: 12 λ

– 180M memory transistors• Average width: 4 λ

– 1.2 V 100 nm process– Cg = 2 fF/µm

18: Design for Low Power Slide 10CMOS VLSI Design

Dynamic Exampleq Static CMOS logic gates: activity factor = 0.1q Memory arrays: activity factor = 0.05 (many banks!)

q Estimate dynamic power consumption per MHz. Neglect wire capacitance and short-circuit current.

18: Design for Low Power Slide 12CMOS VLSI Design

Static Powerq Static power is consumed even when chip is

quiescent.– Ratioed circuits burn power in fight between ON

transistors– Leakage draws power from nominally OFF

devices

0 1gs t ds

T T

V V Vnv v

ds dsI I e e− −

= −

( )0t t ds s sb sV V V Vη γ φ φ= − + + −

18: Design for Low Power Slide 13CMOS VLSI Design

Ratio Exampleq The chip contains a 32 word x 48 bit ROM

– Uses pseudo-nMOS decoder and bitline pullups– On average, one wordline and 24 bitlines are high

q Find static power drawn by the ROM – β = 75 µA/V2

– Vtp = -0.4V

18: Design for Low Power Slide 15CMOS VLSI Design

Leakage Exampleq The process has two threshold voltages and two

oxide thicknesses. q Subthreshold leakage:

– 20 nA/µm for low Vt

– 0.02 nA/µm for high Vt

q Gate leakage:– 3 nA/µm for thin oxide– 0.002 nA/µm for thick oxide

q Memories use low-leakage transistors everywhereq Gates use low-leakage transistors on 80% of logic

18: Design for Low Power Slide 16CMOS VLSI Design

Leakage Example Cont.q Estimate static power:

18: Design for Low Power Slide 19CMOS VLSI Design

Low Power Designq Reduce dynamic power

– α:– C:– VDD:– f:

q Reduce static power