VLSI Design Chapter 5 CMOS Circuit and Logic Design VLSI Design Chapter 5 CMOS Circuit and Logic...

VLSI DesignVLSI Design

Chapter 5 Chapter 5

CMOS Circuit and Logic DesignCMOS Circuit and Logic Design

Jin-Fu Li

2EE613 VLSI DesignNational Central University

Chapter 5 CMOS Circuit and Logic Chapter 5 CMOS Circuit and Logic DesignDesign

• CMOS Logic Gate Design

• Physical Design of Logic Gates

• CMOS Logic Structures

• Clocking Strategies

• I/O Structures

• Low-Power Design


Logic Gate Design IssuesLogic Gate Design Issues

• Hierarchical design Architecture level RTL/logic gate level Circuit level Layout level

• Critical paths – the path with the longest delay that require attention to timing details

• The number of Fanins and Fanouts affects the performance of the circuits


Concept of Fanin and FanoutConcept of Fanin and Fanout

• Fanin The fanin of any complex gate is defined as the number of

inputs of this gate

• Fanout The fanout of a complex gate is defined as the number of

driven inputs attached to the output of this gate

N N

Fanout=N Fanin=N


Logic Gate Design – Logic Gate Design – NAND GateNAND Gate

• Rp = the effective resistance of p-device in a minimum-sized inverter

• n = width multiplier for p-devices in this gate

• k = the fanout

• m = fanin of gate

• Cg = gate capacitance of a minimum-sized inverter

• Cd = source/drain capacitance of a minimum-sized inverter

• Cr = routing capacitance

)( grdp

dr kCCmnCn

Rt


Logic Gate Design – Logic Gate Design – Fanins and Fanouts Fanins and Fanouts

mnCd kCg

Cr

m=3, k=4


Logic Gate Design – Logic Gate Design – NAND Gate Rise TimeNAND Gate Rise Time

)( grdp

dr kCCmnCn

Rt

kn

CRkq

n

CRmrCR

kkqmnrn

CR

kCCkqmnrCn

R

gpgpgg

gp

gggp

)(

))((

))((

))(

1(

int

int

k

kq

n

CRt

mrCRt

tktt

gproutput

gpr

routputrdr

Separate delay into internal delay and external delay caused by fanouts


Logic Gate Design – Logic Gate Design – NAND Gate Fall TimeNAND Gate Fall Time

))(( gggn

df kCCkqmnrCn

Rmt

foutputf

gngn

tktk

kq

n

CRmkrmCR

int

2 ))(

1(

np

gggn

gggp

dfdr

mRR

kCCkqmnrCn

RmkCCkqmnrC

n

R

tt

))(())((

We want the rise time to be equal to the fall time

Hence we must design , thus the delay time ism

WW n

p

))(( 2ggg

ndrdf mkCCkmqnrCm

n

Rtt


Typical CMOS NAND & NOR DelaysTypical CMOS NAND & NOR Delays

)02.0(

4

)005.04(4

g

nandfnandn

Lnandn

nandf

kCmm

tR

CmR

mt

pfCrC

kq

CkC

n

Assume

dg

Lg

005.0

0)(

4

:

ND4-Fall

NR4-Fall

NR4-Rise

ND4-Rise

0.0 0.25 0.5 0.75 1.0 0.0 0.25 0.5 0.75 1.0

10.0 ns 10.0 ns

ABCD

ABCD

Capacitive load (pf)

Delay (ns) Delay (ns)

Capacitive load (pf)


Logic Gate Design – Logic Gate Design – Gate DelaysGate Delays

GATE

NAND- and NOR-Gates Delays Measured with SPICE

tinternal-f

(ns)

INVND2ND3ND4ND8NR2NR3NR4NR8

.08.2.41.68

2.44.135.14

.145.19

toutput-f

(ns/pf)

toutput-r

(ns/pf)tinternal-r

(ns)

1.73.14.45.7

10.981.751.831.881.8

.08

.15.2.25.38.25.52.9

3.35

2.12.12.12.12.24.16.28.2

16.4


Logic Gate Design – Logic Gate Design – Efficient ResistanceEfficient Resistance

GATE

Efficient Resistance Value for a Typical 1u CMOS Process

Rn ( )

INVND2ND3ND4NR2NR3NR4

7.1K6.3K6.0K5.9K7.3K7.4K7.5K

Rp ( )

8.5K8.6K8.7K8.8K8.4K8.4K8.4K


Logic Gate Design – Logic Gate Design – 8-Input AND Gate8-Input AND Gate

Approach 1

Approach 2

Approach 3

ABCD

EF

ABCDEFGH

GH

B

CD

EF

GH

A

CL

CL

CL


Logic Gate Design – Logic Gate Design – 8-Input AND Gate8-Input AND Gate

Approach

Comparison of Approaches to Designing an 8-Input AND Gate

Delay Stage 1ns

Delay Stage 2ns

Delay Stage 3ns

Delay Stage 4ns

Total Delay (SPICE) ns

1 ND8->INV

2ND4->NR2

3ND2->NR2ND2->INV

2.82ND8

falling

3.37INV

rising

4.36NR2

rising

.88ND4

falling

.4NR2

rising

2.17INV

rising

.31ND2

falling

.31ND2

falling

6.2(6.5)

5.24(5.26)

3.19(3.46)


Basic Physical Design Basic Physical Design

• Gates: Inverter, NAND, and NOR

• Complex Gates

• Standard Cells

• Gate Array

• Sea of Gates

• Layout Optimization

• Transmission Gates

• 2-Input Multiplexer


Physical Design – Physical Design – CMOS InverterCMOS Inverter

a z

Vss

Vdd

a z

Vss

Vdd


Physical Design – Physical Design – NAND GateNAND Gate

a

z

Vss

Vdd

a

z

Vss

Vdd

b

b


Physical Design – Physical Design – NOR GateNOR Gate

a

z

Vss

Vdd

b

az

Vss

Vdd

b


Physical Design – Physical Design – Complex GatesComplex Gates

• All complex gates can be designed using a single row of N-transistors and a single row of P-transistors, aligned at common gate connections

• Design procedure Draw two dual graphs to P transistor tree and N

transistor tree Find all Euler paths that cover the graph Find a P and an N Euler path that have identical

labeling If not found, break the gate in the minimum

numbers of places to achieve step 3



A

Z

I2

I1

B

A B

C D

C

DI3

I3

I1

I2

Z

A

B

C D

VDD

Z Vss



A

B

CD

A

B

CD

z

Vdd

Vss

A B C D


Physical Design – Physical Design – XNOR Gate (1)XNOR Gate (1)

AB Z

z

Vdd

Vss

A B

Z’Z’A

B

Z’

A B

Z’


Physical Design – Physical Design – XNOR Gate (2)XNOR Gate (2)

AB

Z

z

VddVss

A

B


Physical Design – Physical Design – Automated ApproachAutomated Approach

A

BED C

E

A B EDC

Vdd

Vss

Vdd

Vss

A BED C A BED C

P

N


Physical Design – Physical Design – Standard-Cell ApproachStandard-Cell Approach

WVdd

Wp

Wn

WVss

Dnp

a b c zd


Physical Design – Physical Design – Standard-Cell LayoutStandard-Cell Layout

Vdd Vdd

Vss Vss

a b c a b c zz


Physical Design – Physical Design – Gate Array Layout (1)Gate Array Layout (1)

Vdd

Vss


Physical Design – Physical Design – Gate Array Layout (2)Gate Array Layout (2)

Vdd

Vss

Gate array cells

Routing channels


Physical Design – Physical Design – Sea-of-Gate LayoutSea-of-Gate Layout

Vdd

Vss

supply

supply

well contacts

substrate contacts

poly gates

P-transistors

N-transistors


Physical Design – Physical Design – Sea-of-Gate (NAND3)Sea-of-Gate (NAND3)

a b c

za b c

a b c

z


Physical Design – Physical Design – CMOS Layout GuidelinesCMOS Layout Guidelines

• Run VDD and VSS in metal at the top and bottom of the cell

• Run a vertical poly line for each gate input

• Order the poly gate signals to allow the maximal connection between transistors via abutting source-drain connection.

• Place n-gate segments close to VSS and p-gate segments close to VDD

• Connection to complete the logic gate should be made in poly, metal, or, where appropriate, in diffusion


Physical Design – Physical Design – Improvement in DensityImprovement in Density

• Better use of routing layers – routes can occurs over cells

• More “merged” source-drain connections

• More usage of “white” space in sparse gates

• Use of optimum device sizes – the use of smaller devices leads to smaller layouts


Physical Design – Physical Design – Layout OptimizationLayout Optimization

Fclk

A<0>

A<1>

A<2>

A<3>

F

Vdd

Vss

A<0>A<1>A<2>A<3>clk


Physical Design – Physical Design – Layout OptimizationLayout Optimization

DB

A

D

BC

2

Z

A

1

C

Z

A B C D

Vdd

Vss

A B C D

RightWrong


Physical Design – Physical Design – Transmission GateTransmission Gate


Physical Design – Physical Design – 2-Input Multiplexer2-Input Multiplexer

a

b

c

z

c

-c abz

z

c -c


CMOS Logic – CMOS Logic – Pseudo-nMOS Logic Pseudo-nMOS Logic

A

TimeL

DDV

V

F

n

p

2( ) ( | |)2n

n DD Tn OL DD TpV V V V V

( )2

pOL DD T

n

V V V

Tn Tp TV V V for


CMOS Logic – CMOS Logic – Dynamic CMOS Logic Dynamic CMOS Logic

N-logicBlock

clk

inputs

Z

clkprecharge

evaluate

clk

clk

A B

C Z=(A+B).C

clk

clk

A

B

C

Y=ABC



C 2

C 1C 1C 2

1

1

0

clk=1

clk=1A

C

C

B C

A

charge sharing model

1 2

1 2

( )DD A

A DD

CV C C C V

CV V

C C C

If for example 1 2 0.5C C C then this voltage would be VDD/2



N 1 N 2

N 1

T d1

N 2

T d2

N LogicN Logic

clock

inputs

clock

Erroneous State


CMOS Logic – CMOS Logic – Clocked CMOS Logic Clocked CMOS Logic

E

Z

D

C

B

A

clk

-clk


CMOS Logic – CMOS Logic – Pass-Transistor Logic Pass-Transistor Logic

A

-B

B

A

-A OUT

-B

B

A

-A

OUTB

A

OUT

Complementary Single-polarity Cross-coupled


CMOS Logic – CMOS Logic – CMOS Domino Logic CMOS Domino Logic

clk

D

A

C

B

E

Z

Basic gate



Static version

N-logicBlock

clk

inputs

Z

weak p device

N-logicBlock

clk

inputs

Z

Latched version



N-logic

N-logic

N-logic

N-logic

clk

A 5

A

A

A

A

A 0

1

2

3

4

C

C

C

C

C

C

C 1

3

4

5

2

6

7

clk


CMOS Logic – CMOS Logic – NP Domino Logic NP Domino Logic

N-logic

clk

N-logic

N-logic

clk

N-logic

P-logicinputsstableduring clk=1

other N blocksother P blocks

to futher P blocks

P-logicinputsstableduring clk=1

other N blocksother P blocks

to futher P blocks

clk -clk

clk-clk

other P blocksother N blocks


CMOS Logic–CMOS Logic–Advantages of Dynamic LogicAdvantages of Dynamic Logic

• Smaller area than fully static gates

• Smaller parasitic capacitance, hence higher speed

• Glitch free operation if designed carefully


CMOS Logic – CMOS Logic – CVSLCVSL

F-F

-e

-a

-d

-b

-ccbe

d aCombinationalNetwork

nMOSDifferential Inputs

-QQ

Basic version A particular function


CMOS Logic – CMOS Logic – CVSLCVSL

Clocked version A 4-way XOR gate

-Q Qclock

clock

-aa

-bb b -b

-cc-cc

-d d -d d

CombinationalNetwork

nMOSDifferential Inputs

clock

Q-Qclock

(abcd)=(0000)


Clocking Strategies – Clocking Strategies – Clocked SystemsClocked Systems

bits

clock

outputsinputs

nextstatebits

currentstate

Q D

Q D

Q D

A simple finite state machine

Combinational Logic


Clocking Strategies – Clocking Strategies – Clocked SystemsClocked Systems

A pipeline system

QD

QD

QD

QD

QD

QD

QD

QD

QD

C1 C2inputs

inputs

outputs

outputsC1 C2

10 ns 10 ns


Clocking Strategies – Clocking Strategies – Latches and Reg.Latches and Reg.

clock

Data

Q

Clock-to-Q Delay (Tq)

Hold Time (Th)

Setup Time (Ts)

Cycle time Tc


Clocking Strategies – Clocking Strategies – LatchesLatches

clk

0

1Q

D

S

clk

D

Q

clk

0

1Q

S

clk

D

Q

D


Clocking Strategies – Clocking Strategies – RegistersRegisters

clk

0

1Q

S

clk

0

1S

DQM

QM

D

clk

Q

master slave



clk=0

clk=1

slavemaster



D

clk clk

Q


Clocking Strategies – Clocking Strategies – JK RegistersJK Registers

clk -clk

clk

D

K

J

QN

Q

J K clk Q QN

0011

0101

Q01

QN

QN10Q

A

B

J=K=0; Q=D

JN=KN=1; A=QN, B=1; D=AN=Q

J=0;K=1

KN=0,JN=1; A=1, B=1; D=0

J=1; K=0

KN=1, JN=0; A=QN, B=Q; D=1;

J=1; K=1

KN=0, JN=0; A=1, B=Q; D=QN

K

J

QN

Q


Clocking Strategies – Clocking Strategies – System TimingSystem Timing

Reg.A

Reg.B

Combinational LogicTd

TsTq

clock

BCombinational Logic

TdTsTq

clock

ALatch Latch

BLatch

clock

ALatch

Tq Ts LatchC

A B

Combinational Logic Combinational LogicTda Tdb


Clocking Strategies – Clocking Strategies – System TimingSystem Timing

sb

qa

sbqacda

T

T

TTTT 1

: the clock-to-Q time of latch A

: the setup time of latch B

scqbcdb TTTT 0

Similarly,

Finally,

][2 sqdbdac TTTTT


Clocking Strategies – Clocking Strategies – Setup & Hold TimeSetup & Hold Time

Pad

Pad

dT

TD

QinD

in

tt tt

For an ideal DFF,

If is high when , then Q should be high

If becomes to low when , then Q still is high

inD tt

inD

in

inD tt



dT

T

D

inD

inD

dT

T

TTd When , should become high earlier and Q can become high

When , should retain at high longer and Q can be still at highTTd

dTTST

TTT dS

T

hT dT

TTT dh

inD

D

inD

D


QD QD

T

M 1

T c1 T c2

Td2

T c2

Td2

c1

clk

New DataOld data

Logic

clk

M 2

delay delay


Tdc

Tdq Tdl

q1 d2

Tdc

1. When Tdc>Tdq+Tdl, M2 latches

the New data

2. When Tdq+Tdl-Tdc>TC , M2

latches Old data twice

Therefore, 0<Tdq+Tdl-Tdc<TC

TC

New data


Clocking Strategies – Clocking Strategies – D RegisterD Register

D

-clk

-clk

clk clk -clk

clk

clk

-clk

Q

-Q

D Q-clk

clk

clk

-clk

clk

-clk

-clk

clk


Clocking Strategies – Clocking Strategies – Clock SkewClock Skew

clk

-clk

QD

Feedthrough condition

-clk

clkclk-in

-clk

clk

Buffers Necessary for Large Loads


Clocking Strategies–Clocking Strategies–Skew Clock PipelineSkew Clock Pipeline

clk

clk1 clk2

-2ns 0ns

CL1

(5ns)

CL2

(9ns)

CL3

(5ns)

FF FF FF FF

7ns

clk

clk1

clk2

A B C D

A B C D

A B

-2ns

clk3

Aclk3

C D

B C



D Q

-clk

clk

1. Low area cost

2. Driving capability of D must override the feedback inverter

D Q

-clk

clk

clk

-clk



D Q-clk

clk

clk

-clkD

Q

-clkclk

Vss

Vdd


Clocking Strategies – Clocking Strategies – DETDFFDETDFF

clk

clk

D -D

Q1 -Q1

Latch 1

Q1

clk



clk

clk

D -D

Q2 -Q2

Latch 2

Q2

clk



clk Latch 1 enabled Latch 2 enabled

Q2=-Q2=low Q1=-Q1=high

Latch 2

-Q

Q

Q2

-Q2

D

Latch 1

-Q1

Q1clk


Clocking Strategies – Clocking Strategies – RegisterRegister

clk

-clk

clk

-clk

-clk

-clk

clk

-clk

-reset

D

Q

Asynchronously resettable register

clk

-reset

Q


Clocking Strategies – Clocking Strategies – RegisterRegister

clk

-clk

clk

-clk

-clk

-clk

clk

-clk

-reset

D

Q

Asynchronously settable and resettable register

-set


Clocking Strategies – Clocking Strategies – Dynamic RegistersDynamic Registers

clk

-clkDDD

clk

-clk

clk

-clk

-Q

D

clk

-clk

-Q

-clk

clk

Qclk

-clkD

-clk

clkQ

Dynamic single clock latches

Dynamic single clock registers


Clocking Strategies – Clocking Strategies – Single ClockSingle Clock

Logic

Logic

L1 L2

clock

L1 opaque

L2 transparent

L2 opaque

L1 transparentclock


Dynamic Latches – Dynamic Latches – Single-Phase ClockingSingle-Phase Clocking

CLK

D X

Q

Xn QnDnCLK

0

1

1

0

H

H

L

L

1

0

1

0

1

Xn-1 Qn-1

Qn-1

CLK

D X

-Q

Clock active high latch Clock active high latch with buffer



CLK

D

X Q

Xn QnDnCLK

0

1

1

0

L

L

H

H

1

0

1

0

1

Xn-1 Qn-1

Qn-1

Clock active low latch

CLK

D

X -Q

Clock active low latch with buffer



CLK

D

X Q

Clock active high latch without feedback

Clock active low latch without feedback

CLK

D X

Q

Assume that the capacitance of node X

is 0.002pF and the leakage current I is

1nA.

Therefore, T=CV/I=0.002pFx5V/1nA=100us.

That is, the latch needs to be refreshed each 100us.

Otherwise, the output Q will become high.


Dynamic Registers – Dynamic Registers – TSPCTSPC

Positive edge trigger register

CLKD

A

-QB

CLK

D

A

B

-Q

The value of the hold time of this flip flop is close to zero.

tf

tr


• PLL for synchronization

Phase Locked Loop Clock TechniquesPhase Locked Loop Clock Techniques

T1

T2

clock

dclk

data out

clock

dclk

output pad

dclk+dpad

clock pad

clock route

chip

dclk

output pad

dclk+dpad

clock pad

clock route

chip

clock

dclk

data out

T2

T1=Input buffer delay

+routing RC delay

T2=Clock-to-Q delay

+output buffer delay

PLL

clock


Phase Locked Loop – Phase Locked Loop – Clock MultiplyingClock Multiplying

dclk

output pad

dclk+dpad

clock pad

clock route

chip PLL

/4

clock

dclk

clock

PLL PLL

system clock

clock clock

bus

Clock-multiplying PLL Synchronize data transfer between chips

Synchronize the output enable signals

1. Reduce tristate fights

2. Improve overall timing


Typical Phase Locked LoopTypical Phase Locked Loop

Phase Detector Charge Pump Filter VCO

ProgrammableFrequency divider

(/n)

reference clock fn

U

DnxfnVc

U

D

Vc

Low-pass filter

Vdd


Phase Locked Loop – Phase Locked Loop – Phase DetectorPhase Detector

S

R

Q

S

R

Q

clkext

clk

U

D

UP DNNOP

clkext

clk

clkext

clk

R

SQ


• Charge pump circuits

Phase Locked Loop – Phase Locked Loop – Charge PumpCharge Pump

Out

U

D

Out

U

D

Vrefp

Vrefn

Pref

Nref

Biased by current mirror

The output current of the charge pump can be adjusted through the control of the current mirror.


• Simple implementation of low-pass filter

• The two capacitors C1 and C2 are in the order of tens of pF

• The capacitor C2 is added in parallel to the simple RC low-pass filter to form a second order filter The stability of the system is maintained even with the process

variation of these on-chip components

• Note that these capacitors can occupy a large portion of the PLL

Phase Locked Loop – Phase Locked Loop – Low-Pass FilterLow-Pass Filter

In Out

TG

NC2NC1


Phase Locked Loop – Phase Locked Loop – VCOVCO

Odd number of stages

Control voltage

fVCO

Current-starved inverter type VCO

II

V

I

Control voltage

tin tin+t

Voltage-Controlled Delay Line (VCDL) type VCO

V-I converter

Delay cell


Phase Locked LoopPhase Locked Loop

U

D

Vc

Low-pass filter

VCOfout

fin

fout

fin

D

Phase Detector


Phase Locked Loop – Phase Locked Loop – Programmable VCOProgrammable VCO

VC

V-I

co

nve

rte

r

De

lay

cell

De

lay

cell

De

lay

cell

Shift register

Generated clock


• NP-Domino Logic Allow pipelined system architecture

Single-Phase Logic – Single-Phase Logic – NP Domino LogicNP Domino Logic

nMOS

Logic

pMOS

Logic

clk -clk

clk

-clk

clk section

The circuit performs precharge-discharge operation when clock is low,

and all stage evaluate output levels when the clock is high.


• -clk section

Single-Phase Logic – Single-Phase Logic – NP-Domino Logic NP-Domino Logic

nMOS

Logic

pMOS

Logic

-clk clk

-clk

clk

The circuit performs precharge-discharge operation when clock is high,

and all stage evaluate output levels when the clock is low.


• A pipelined NP-Domino CMOS system

Single-Phase Logic – Single-Phase Logic – NP-Domino Logic NP-Domino Logic

clk

section

-clk

section

clk

section

A B C

a0 a1A

clk

B

C c0

b0 b1 b2

a2

b1 b2


• Uses of clock skew to extend clock cycle (not recommended)

Single-Phase Logic – Single-Phase Logic – Clock SkewClock Skew

Logic

delay

Td2

Tc1clock

old data new data

Tc1

Td2

clock

< Tc1Td2


• Lock-up Latch

• Contra-data-direction clock

Single-Phase Logic – Single-Phase Logic – Avoiding Clock SkewAvoiding Clock Skew

Logic

delayclock

Lock-up latch

Logic

clockdelay


• Dynamic register

Two-Phase ClockingTwo-Phase Clocking

QD

-ph1

ph1

-ph2

ph2

ph1

ph2

ph1=1,ph2=0

ph1=0,ph2=1

C1 C2

C1 C2


• Failure due to clock skew


ph1

ph2

ph1=1,ph2=1C1 C2


• Two-phase registers with single-polarity clocks


ph1 ph2

ph1 ph2


• In a large CMOS chip, clock distribution is a serious problem Vdd=5V Creg=2000pF (20K register bits @ 0.1pF) Tclk=10ns Trise/fall=1ns Ipeak=Cdv/dt=(2000px5)/1n=10A Pd=CVdd2f=2000px25x100=5W

• Methods for reducing the values of Ipeak and Pd Reduce C Interleaving the rise/fall time

Clock DistributionClock Distribution


• Clocking is a floorplanning problem because clock delay varies with position on the chip

• Ways to improve clock distribution Physical design

Make clock delays more even At least more predictable

Circuit design Minimizing delays using several stages of drivers

• Two most common types of physical clocking networks H tree Balanced tree

Clock DistributionClock Distribution


Clocking Distribution – Clocking Distribution – H Tree H Tree

clock


Clocking Distribution – Clocking Distribution – Balanced Tree Balanced Tree

clock


Clocking Distribution – Clocking Distribution – Reducing Power Reducing Power

• Techniques used to reduce the high dynamic power dissipation Use a low capacitance clock routing line such as

metal3. This layer of metal can be, for example, dedicated to clock distribution only

Using low-swing drivers at the top level of the tree or in intermediate levels


Clocking Distribution – Clocking Distribution – Half-Swing Driver Half-Swing Driver

C1

C3

C2

C4

CA

CB

Vdd

Gnd

Clock

Vout

clkn

clkp

-clkn

-clkp


• Types of pads Vdd, Vss pad Input pad (ESD) Output pad (driver) I/O pad (ESD+driver)

• All pads need guard ring for latch-up protection

• Core-limited pad & pad-limited pad

I/O Structures – I/O Structures – Pads Pads

PAD PAD

I/O circuitry I/O circuitry

Core-limited pad Pad-limited pad


Input Pads – Input Pads – ESD Protection ESD Protection

PAD

Input pad without ESD protection

Assume I=10uA, Cg=0.03pF, and t=1us

The voltage that appears on the gate is about 330volts

Input pad with ESD protection

PAD


I/O Pads – I/O Pads – Tristate & Bidirectional Pads Tristate & Bidirectional Pads

PAD

Tristate pad

PAD

Bidirectional pad

OUT

P

N

OE

Ddata

output-enable

OUTPNOE D

0

1

1

X

0

1

0

1

0

1

1

0

Z

0

1


Input Pads – Input Pads – Schmitt Trigger CircuitSchmitt Trigger Circuit

Transfer characteristic of Schmitt trigger

Vout

Vin

VT- VT+ VDD

VDD

1. Hysteresis voltage VH=VT+-VT-

2. When the input is rising, it switches when V in=VT+

3. When the input is falling, it switches when V in=VT-



Voltage waveforms for slow input

Vout

Time

VT-

VT+

VDD

Schmitt trigger turns a signal with a very slow transition into a signal with a sharp

transition

Vin



A CMOS version of the Schmitt trigger

Vout

N1

VFP

VDD

FNinGS VVV 2

Vin

VFN

N2

P2

P1

N3

P3

1. When the input is rising, the VGS of the transistor N2 is given by

2. When , N2 enters in conduction mode which means Tin VV TnGS VV 2

3. Then TnTFN VVV

VLSI Design Chapter 5 CMOS Circuit and Logic Design VLSI Design Chapter 5 CMOS Circuit and Logic...

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Transcript of VLSI Design Chapter 5 CMOS Circuit and Logic Design VLSI Design Chapter 5 CMOS Circuit and Logic...